Commit Graph

18543 Commits

Author SHA1 Message Date
Furquan Shaikh 212820c8d7 google/reef: Use GPE0_DW1_15 as wake signal for touchpad
Due to GPE routing, raw GPIO cannot be used for indicating the wake
signal for touchpad. Instead we need to reference GPE pins.

BUG=chrome-os-partner:55670

Change-Id: Ie5d8473df4301c7beef0cae8fe84e71b2838261b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15947
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-30 00:53:38 +02:00
Furquan Shaikh 6e37e90193 soc/intel/apollolake: Include gpe.h in chip.h
This is required for using GPE_* macros in devicetree.cb.

BUG=chrome-os-partner:55670

Change-Id: I8f6f536df96cf8145bb0c03ec413fb2f374301b5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15946
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-30 00:53:27 +02:00
Zhuo-hao.Lee ce37e47f46 skylake: fix VSDIO is at 0.8V when SDCard is not inserted
1. Enable SoC SD_CMD/D* signals pull-down of 20k when SD-card
   is removed. When SD-card is disconnected, the pull-down is
   disabled.
2. Provide path for weak leakage from buffers of SD_CMD/D* signal
   to be grounded. Thus dropping voltage on the SD_CMD/D* signals to ~0V.

BUG=chrome-os-partner:54421
TEST=no power leakage when SDCard isn't inserted on skylake platform

Change-Id: I567199b172841125f8916a61a76005cfdaa62eb8
Signed-off-by: Zhuo-hao.Lee <zhuo-hao.lee@intel.com>
Reviewed-on: https://review.coreboot.org/15910
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-29 00:12:53 +02:00
Abhay Kumar ec2947fb07 soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume
Do not pass VBT table to fsp in normal mode and S3 resume so that
PEIM GFX will not get initialized.

Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14575
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-29 00:09:05 +02:00
Lin Huang 3707fc2d96 google/gru & kevin: Update DRAM configuration
We need to enable DRAM ODT on kevin/gru board to improve the
DRAM signal. Note, if the DRAM ODT is enabled and set to 120ohms,
the sdram VREF need to adjust to 840mv.

This patch also makes following changes:
1. For compatiblity with the  old board, add the
"sdram-lpddr3-hynix-4GB-666-no-odt.inc" and
"sdram-lpddr3-hynix-4GB-800-no-odt.inc" files
which do not enable sdram ODT.
2. Delete the 300MHz dram inc file. The 300MHz sdram config just
reduced 666MHz to 300MHz based on the 666MHz config file, and it is
not stable, so delete it.
3. Delete the 928MHz dram inc file, 928MHz sdram config still in
debuging, delete it for now.

BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass

Change-Id: If0248e1bc4cef2c298762080f1ca018653af0521
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 78d8a28e2d3489c99c9bba2c1c9aa76812e2e33f
Original-Change-Id: I35f0685782d6fb178a95780ec77c45f565dd2194
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358763
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15813
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28 23:54:39 +02:00
Lin Huang df5ead9d2d rockchip/rk3399: sdram: correct controller vref setting
When enabling the controller ODT, the controller vref needs to
correspond with the ODT value and DQ drive strength.

BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass

Original-Commit-Id: a7251c72b87d9f149b68d086c3252f1c668e0e80
Original-Change-Id: I7e54b3473f68a382208a0fb0b0600552fe6390ad
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358762
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>

Squashed with:

rockchip/rk3399: Halt if we get an invalid odt or drv value

When we were pushing the updated sdram.c to coreboot.org, the compiler
there found that we were not initializing vref_value_dq in all code
possible code paths.

This patch updates those code paths to halt the system.

Branch=none
Bug=none
Test=Built with coreboot.org toolchain and verified that the compile
errors were gone.

Change-Id: I0ad4207dc976236d64b6cdda58d10bcfbe1fde11
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362726
Reviewed-by: Julius Werner <jwerner@chromium.org>

Change-Id: I22a0cef6f12d9aae2ea4dcb99e7ebdd788f2cdd1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15812
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-28 23:53:57 +02:00
Lee Leahy 47bd2d957d drivers/intel/fsp2_0: Update the copyrights
Update the copyright dates in the FSP 2.0 files.
Add a copyright to Kconfig.

TEST=Build and run on Galileo Gen2

Change-Id: I0ad0c5650bde0e31d01a04bcc7d22a19273fe29b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15852
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28 23:46:57 +02:00
Susendra Selvaraj ab88c7d366 google/reef: Write protect GPIO relative to bank offset
Update the write protect GPIO reported in ACPI to GPIO_75.
Also update the controller ID to "INT3452:01" which will
point at the goldmont device and includes write protect GPIO.

BUG=chrome-os-partner:55604
BRANCH=none
TEST=verify crossystem output for wpsw_cur.

Change-Id: Ibe6a013aaab18bfa2436698298177218ca934fab
Signed-off-by: Susendra Selvaraj <susendra.selvaraj@intel.com>
Reviewed-on: https://coreboot.intel.com/7929
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 23:06:10 +02:00
Brandon Breitenstein df12d1923f soc/intel/apollolake: Update FSP Header files for version 146_30
Add new UPDs for Fspm and Fsps. Update headers to make new UPDs
available for use. New UPDs enable various memory and trace funtionality
options as well as support for zero sized IBB region.

BUG=chrome-os-partner:55513
BRANCH=none
TEST=built and tested with no regressions

Change-Id: Id1573baaa306ed4fe4353df5f27e5963cb1a76e6
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15815
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-28 21:21:06 +02:00
Paul Kocialkowski fde3275fb4 Makefile: Include $(top) in DOTCONFIG definition to allow override
Including $(top) in the DOTCONFIG definition allows getting rid of the
$(top) prefix in payloads, which in turns allows providing a full path
for DOTCONFIG via the command line.

Change-Id: I7546a12cf4a2a146e32fef81121f45f83ba67ac8
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15826
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-28 20:27:42 +02:00
Paul Menzel aad4587c03 viatool/quirks: Add newline to end of file
Change-Id: If505021c6dd4bc1c98094dc6e4a3da1ea7753859
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/15916
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-07-28 20:18:10 +02:00
Martin Roth 2b119b380f checkpatch: add .checkpatch.conf
Try to make checkpatch a little friendlier to the coreboot project.

This is the checkpatch .conf from the Chrome OS tree.

Change-Id: Ie45d5c93f97bd58f3ea31341b47c4ee2a8f02b1e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15919
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-07-28 20:16:25 +02:00
Shaunak Saha cd9e1e423f intel/apollolake: Update gnvs for dptf
This patch updates dptf variable in gnvs based on device
configuration by reading the device tree structure.

BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
       under /sys/class/thermal in Amenia and Reef board.
       Navigate to /sys/class/thermal, and verify that a
       thermal zone of type TCPU exists there.

Change-Id: I8ab34cdc94d8cdc840b02347569a9f07688e92cd
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15620
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 20:13:34 +02:00
Shaunak Saha 5dd2b18540 intel/apollolake: Add soc specific DPTF values
This patch adds apollolake soc specific change. DPTF
ASL files are now in src/soc/intel/common so that
they can be reused but different soc can have different values
e.g., for skylake cpu soc thermal reporting device is at
Bus 0, Device 4, Function 0 while for apollolake it is Bus 0, Device 0,
Function 1. This patch adds a dptf asl file in soc directory where we
can define all values which can change across soc's and can be
included in mainboard dptf asl.

BUG=chrome-os-partner:53096
TEST=In Amenia and Reef board verify that the thermal zones are
       enumerated under /sys/class/thermal in Amenia and Reef board.
       Navigate to /sys/class/thermal, and verify that a thermal
       zone of type TCPU exists there.

Change-Id: I888260a9c799d36512411a769f26dd30cf8d5788
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15619
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 20:10:15 +02:00
Shaunak Saha 44887c3e36 intel/common: Add ASL code for DPTF
This patch adds the common ASL code for Intel
platforms. This is the basic ASL needed to add support
for DPTF controlled devices. We are moving
these commmon ASL files to src/soc/intel/common/acpi as
these are same codes used in all Intel platforms and
hence no need to duplicate.

BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
	under /sys/class/thermal. Navigate to
	/sys/class/thermal, and verify that a thermal
	zone of type TCPU exists there.

Change-Id: I01078382a9008263c6ad99f6bf07558885af6a63
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15093
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 20:09:58 +02:00
Elyes HAOUAS e51387896f Documentation: Capitalize RAM, ROM and ACPI
Change-Id: I06c1d0fe0e3d429e54d3777de679f9fc641f4eed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15927
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28 20:03:36 +02:00
Martin Roth 2098778726 intel/common/opregion.c: only write 16 bytes to 16 byte field
Including the terminating null, 17 characters were being written to the
field, overwriting the a byte of the size field.

Fortunately, the size was updated soon after this.

Fixes coverity warning 1229570 - Destination buffer too small.

Change-Id: I39285a9283dd9a17d638afe5b2755c7e420d7698
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15889
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-28 19:22:35 +02:00
Jonathan Neuschäfer 8e63017096 arch/riscv: Refactor bootblock.S
A few things are currently missing:
- The trap handler doesn't set the stack pointer, which can easily
  result in trap loops or memory corruptions.
- The SBI trampolin page (as described in version 1.9 of the RISC-V
  Privileged Architecture Specification), has been removed for now.

Change-Id: Id89c859fab354501c94a0e82d349349c29fa4cc6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15591
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-28 18:31:28 +02:00
Jonathan Neuschäfer 62bd9f93dd arch/riscv: Only initialize virtual memory if it's available
And do the detection just before the initialization.

Change-Id: I9a52430262f799baa298dc4f4ea459880abe250e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15831
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-28 18:20:05 +02:00
Jonathan Neuschäfer 0cc02efb23 arch/riscv: Remove spinlock code from atomic.h
These functions are not used anywhere.

Change-Id: Ica1f4650e8774dd796be0aff00054f3698087816
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15829
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-28 18:18:44 +02:00
Subrata Banik a90f41bdd7 intel/fsp1_1: Add C entry support to locate FSP Temp RAM Init
FSP temp ram init was getting called earlier from ROMCC bootblock.
Now with C entry boot block, it is needed to locate FSP header and
call FspTempRamInit.

Hence add fsp 1_1 driver code to locate FSP Temp ram and execute.

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built kunimitsu and ensure FSP Temp Ram Init return success

Change-Id: If40b267777a8dc5c473d1115b19b98609ff3fd74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15787
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 05:29:46 +02:00
Subrata Banik 89f6d6079e skylake/devicetree: Add LPC EC decode range
Define LPC decode ranges for EC communication.

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu to ensure no EC timeout error

Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15898
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 05:17:56 +02:00
Subrata Banik 50b9258a0b skylake/mainboard: Define mainboard hook in bootblock
Move mainboard post console init functionality (google_chrome_ec_init &
early_gpio programming) from verstage to bootblock.

Add chromeos-ec support in bootblock

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu till POST code 0x34

Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15786
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 05:17:03 +02:00
Subrata Banik e4a8537ce2 soc/intel/skylake: Add C entry bootblock support
List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34

Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 05:15:58 +02:00
Subrata Banik 68d5d8b28a soc/intel/skylake: Do cache as ram and prepare for C entry
Enable cache-as-ram and prepare for c entry in bootblock.

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x2A

Credits-to: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>

Change-Id: I3412216cdf8ef7e952145943d33c3f07949da3c1
Reviewed-on: https://review.coreboot.org/15784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 05:14:38 +02:00
Elyes HAOUAS e3e2bb0a89 util: Correct typo in MSR_EBC_SOFT_POWERON
Change-Id: Iba5fc92d8740d0bb7d41f8a83513ba7fb97be592
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15900
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28 01:09:37 +02:00
Elyes HAOUAS 7ab98fb790 util/msrtool: update register for Pentium4_later
Update MSR's registers regarding "Intel® 64 and IA-32
Architectures Software Developer’s Manual"- April 2015.
"64-ia-32-architectures-software-developer-manual-325462.pdf"

Change-Id: I71e399c4a6fef9de6a5581b64a6918660b2f8445
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15798
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2016-07-28 01:09:02 +02:00
Elyes HAOUAS e5a5084b70 msrtool/README: Remove trailing spaces
Change-Id: I8b7d2263591608e0ab9504262bb06eac4cb52850
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15779
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28 01:08:47 +02:00
Furquan Shaikh 3339861435 soc/intel/skylake: Use init_vbnv_cmos from vboot vbnv
BUG=chrome-os-partner:55639

Change-Id: I7a536bc1cab51e7c942b2e0e48dfe18d8de08a6e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15925
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:41:55 +02:00
Furquan Shaikh 0faf401823 soc/intel/broadwell: Use init_vbnv_cmos from vboot vbnv
BUG=chrome-os-partner:55639

Change-Id: Ie38cdbec513e2bb66e276399c8b4490cbe34a747
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15924
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:41:40 +02:00
Furquan Shaikh baf88d3703 chromeos/gnvs: Clean up use of vboot handoff
BUG=chrome-os-partner:55639

Change-Id: I40a28f921499ddf43d8b423f5192ac93b40254c1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15903
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 00:40:20 +02:00
Furquan Shaikh 0d9cd92efb chromeos: Clean up elog handling
1. Currenty, boot reason is being added to elog only for some
ARM32/ARM64 platforms. Change this so that boot reason is logged by
default in elog for all devices which have CHROMEOS selected.

2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that
want to add details about watchdog reset in elog. This requires a
special region WATCHDOG to be present in the memlayout.

3. Remove calls to elog add boot reason and watchdog reset from
mainboards.

BUG=chrome-os-partner:55639

Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:40:03 +02:00
Furquan Shaikh c66a02634c google/urara: Provide dummy implementations of rec/dev functions
This is required to enable elog support in ChromeOS by default.

BUG=chrome-os-partner:55639

Change-Id: I9c97143d794de4bf220ddf67c0ca2eac2f7a326d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:39:20 +02:00
Furquan Shaikh faf07a8fab qualcomm/gale: Add required files to enable elog in ramstage
BUG=chrome-os-partner:55639

Change-Id: Idbad4f8763be18002907a62be755b2fdf7e479ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15895
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:38:44 +02:00
Furquan Shaikh a7f11b8ecf qualcomm/storm: Add required files to enable elog in ramstage
BUG=chrome-os-partner:55639

Change-Id: Ie859ec3ff682e91a4d7d38d3c3cd6badf7385431
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15894
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:38:25 +02:00
Furquan Shaikh 01ac811b08 i2c/ww_ring: Add ww_ring files to ramstage
These files are required by storm and gale boards for enabling elog
support in ramstage.

BUG=chrome-os-partner:55639

Change-Id: I2bbfee2acf2bfe2f896a8619b1276dcea1b87f16
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:38:09 +02:00
Furquan Shaikh 18b02c5630 google/chromeos: Use vboot bootmode functions for elog add boot reason
BUG=chrome-os-partner:55639

Change-Id: I3ac2b256862758bb5c9e6c2f1311972af474e8f6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15870
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 00:36:48 +02:00
Furquan Shaikh 0325dc6f7c bootmode: Get rid of CONFIG_BOOTMODE_STRAPS
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.

BUG=chrome-os-partner:55639

Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 00:36:22 +02:00
Furquan Shaikh 2a12e2e8da vboot: Separate vboot from chromeos
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.

BUG=chrome-os-partner:55639

Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 00:36:00 +02:00
Furquan Shaikh af8ef2a810 drivers/intel/fsp2_0: Update MRC cache with dead version in recovery
If the system is in recovery, store the newly generated MRC data using a
dummy version which is not legit. This ensures that on next normal boot,
new MRC data will be generated and stored.

BUG=chrome-os-partner:55699

Change-Id: Ib13e8c978dc1b4fc8817fab16d0e606f210f2586
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15828
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27 23:53:13 +02:00
Furquan Shaikh c31973760f soc/intel/common: Store MRC data in next available slot in the cache
Currently, coreboot performs an erase of the entire MRC cache region on
flash if there is a version mismatch for the MRC data. Instead of doing
that, store the new MRC data in the next available slot, if there is
enough space available in the cache region.

BUG=chrome-os-partner:55699

Change-Id: Ib24a94f0a47c79941ed9f60095360ae3aad5540b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15915
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27 23:53:03 +02:00
Aaron Durbin bc24b85e6a mainboard/google/slippy: remove unobtainable mainboard
The slippy board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.

Change-Id: I24fb08d9be35b2367e7aa64520ce5778ab861535
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15902
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-27 21:25:23 +02:00
Aaron Durbin 139314bffd mainboard/google/bolt: remove unobtainable mainboard
The bolt board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.

Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15901
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-27 21:25:06 +02:00
Bora Guvendik 60cc75df83 soc/intel/apollolake: Disable monitor mwait
The monitor/mwait is broken on Apollolake. So use ACPI legacy
mwait IO redirection as a work around

BUG=chrome-os-partner:55110

Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/15890
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-27 19:36:01 +02:00
Paul Kocialkowski 46114517d7 Rename VB_SOURCE to VBOOT_SOURCE for increased clarity
This renames the VB_SOURCE variable to VBOOT_SOURCE in the build system,
providing increased clarity about what it represents.

Since the submodule itself is called "vboot", it makes sense to use that
name in full instead of a very shortened (and confusing) version of it.

Change-Id: Ib343b6642363665ec1205134832498a59b7c4a26
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15824
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-27 17:26:05 +02:00
Paul Kocialkowski 94938fb2a8 chromeec: Use CHROMEEC_SOURCE with fallback instead of hardcoding path
This introduces a CHROMEEC_SOURCE variable used for indicating the CrOS
EC source path, with a fallback to 3rdparty/chromeec.

This allows specifying an external path for the CrOS EC source path.

Change-Id: I9792c7f21597127a385b961b65a00d44cfa37146
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-27 17:25:49 +02:00
Lee Leahy 5f4b4c4296 arch/x86: Add bootblock and postcar support for SOC MTRR access
Quark does not support the rdmsr and wrmsr instructions.  Use SOC
specific routines to configure the MTRRs on Quark based platforms.
Add cpu_common.c as a build dependency to provide access to the routine
cpu_phys_address_size.

TEST=Build and run on Galileo Gen2

Change-Id: I43b7067c66c5c55b42097937e862078adf17fb19
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15846
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27 13:50:39 +02:00
Lee Leahy ae738acdc5 cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions.  In this case
use a SOC specific routine to support the setting of the MTRRs.  Migrate
the code from FSP 1.1 to be x86 CPU common.

Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c.  Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.

TEST=Build and run on Galileo Gen2

Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27 13:50:11 +02:00
Damien Zammit 7c2e5396a3 nb/intel/x4x: Fix CAS latency detection and max memory detection
Now hardcode maximum memory frequency capability to 800MHz, as
all chipsets in x4x family support PC2-6400 according to the datasheet.
CAS latency detection also relies on this, and has been cleaned up.

Ram initialization does not work with FSB 1333MHz / DDR2 800MHz combination,
so disable this combination for now, and reduce to 667MHz instead.
Still don't know why this is the case, but FSB1333/667 works.

These changes should now allow existing configurations to continue working,
while providing support for previously unworking configurations, due to
previous buggy CAS latency detection code.

TESTED: on GA-G41M-ES2L
CPU: E5200 @ 2.50GHz (FSB 800MHz)

2x 1GB 667MHz hynix	worked @ 667
1x 2GB 800Mhz ARAM	worked @ 800
1x 1GB 667Mhz StarRam	worked @ 667
2x 2GB 800Mhz (generic)	worked @ 800

Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15818
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-27 11:40:33 +02:00
Aaron Durbin 40d93494c3 device: include devicetree in bootblock stage
Allow bootblock to get access to the static device tree like
other early stages. device_romstage.c was renamed to
device_simple.c to better articulate the usage since it's not
just being used in romstage.

BUG=chrome-os-partner:55357

Change-Id: I3d63d2754c737cc738c09a3e3b3b468362fb78d1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15837
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins)
2016-07-27 00:40:05 +02:00