Commit Graph

18543 Commits

Author SHA1 Message Date
Aaron Durbin 9cbc90a1f6 soc/nvidia/tegra124: remove cache_policiy option
All mainboards (nyans) utilizing the cache_policy option
has it set to DCACHE_WRITETHROUGH. This option is for setting
the framebuffer's cache attribute. However, this option is
reliant on an architecture-specific enumeration. Just remove
the option and use DCACHE_WRITETHROUGH across the board. If
someone wants to reconfigure it at a later date one can
introduce a non-architecture specific option.

Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-27 00:39:48 +02:00
Lee Leahy aa3e8a8124 drivers/intel/fsp2_0/header_util: Convert UPD headers
Convert the FSP 2.0 UPD headers from typedef to struct:
* FSP_UPD_HEADER
* FSPM_ARCH_UPD

TEST=Build and run on Galileo Gen2

Change-Id: Iab241ea07c955e95ff988a4a30103d2a112179b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15856
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 23:23:31 +02:00
Martin Roth c7dfbe26fd google/oak: dsi: set mipi pin driving control on
We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.

When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown(floating). This creates a chance that MIPI
output would be influenced. The DSI's LP signal will be half voltage
attenuation. There will be no display on panel.

When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
effective and termination is fixed OFF. The DSI won't be influenced.

We only need to set this register once, so we set it here to prevent
repeat setting in the kernel when the system goes to recovery mode.

BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui

The original commit in the cros repo combined the chipset and mainboard
code changes.  This has been split for the push to coreboot.org

Change-Id: I733bdd115950b71493856220414ac0dd75d28122
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360850
Original-Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15808
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-26 17:48:56 +02:00
Jitao Shi 700b03962b meditek/mt8173: dsi: set mipi pin driving control on
We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.

When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown (floating). This creates a chance that
MIPI output would be influenced. The DSI's LP signal will be half
voltage attenuation. There will be no display on panel.

When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
effective and termination is fixed OFF. The DSI won't be influenced.

We only need to set this register once, so we set it here to prevent
repeatedly setting in the kernel when the system goes to recovery mode.

BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui

Change-Id: Ie3ccf6fb611dd5a1e2c02b7825d42a92e61268c0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360850
Original-Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15807
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-26 17:48:38 +02:00
Lee Leahy 4cfde2a389 arch/x86: Generate a map file for the postcar stage
Place a map file for the postcar stage and place it into
build/cbfs/fallback.

TEST=Build and run on Galileo Gen2

Change-Id: I349c06e3c610db5b3f2511083208db27110c34d0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15845
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 16:16:37 +02:00
Lee Leahy 99f1b2f755 arch/x86: Organize ramstage to match other stages
Move the ramstage files to the beginning of the section.  Eliminate
duplicate conditionals.

TEST=Build and run on Galileo Gen2

Change-Id: I461a5b78a76bd0d2643b85973fd0a70bc5e89581
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15892
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 16:15:24 +02:00
Lee Leahy e82b5057e3 arch/x86: Move romstage files into romstage section
Move the romstage files into the romstage section of the file.
Eliminate duplicate conditional statements.

TEST=None

Change-Id: Ie2d65cef3797a2c091c0cd76b147b30a765332ad
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15891
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-26 16:14:53 +02:00
Lee Leahy a7491502dc arch/x86: Move postcar stage commands into place
Move the postcar commands to in between romstage and ramstage.  Add the
stage header.

TEST=Build and run on Galileo Gen2

Change-Id: I530da6afd8ccbcea217995ddd27066df6d45de22
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15844
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 16:14:15 +02:00
Aaron Durbin 49d233006b drivers/elog: put back 4KiB limit
The removal of ELOG_FLASH_BASE and ELOG_FLASH_SIZE resulted
in the FMAP region for the eventlog to be honored. However,
certain systems seem to have a large eventlog region that
wasn't being used in practice. Because of the malloc() in the
eventlog init sequence a large allocation was now being requested
that can exhaust the heap. Put back the 4KiB capacity until
the resource usage is fixed.

BUG=chrome-os-partner:55593

Change-Id: Ib54b396b48e5be80f737fc3feb0d58348c0d2844
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15835
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-26 15:35:37 +02:00
Kyösti Mälkki dc4820baed intel car: Use MTRR WRPROT type for XIP cache
XIP cachelines contain the executable to run, we never want
that to get modified. With the change such erronous writes
are ignored and next cacheline miss will fetch from boot
media (SPI / FWH flash).

Change-Id: I52b62866b5658e103281ffa1a91e1c64262f3175
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15778
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 12:38:01 +02:00
Kyösti Mälkki 9551bed306 intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.

Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15761
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 07:09:24 +02:00
Lee Leahy d950f5191d lib: Don't require ULZMA compression for postcar
The build fails during postcar when ULZMA compression is not selected.
Fix cbfs.c to support LZ compression for ramstage as well.

The build error is:
build/postcar/lib/cbfs.o: In function `cbfs_load_and_decompress':
/home/lee/coreboot/public/src/lib/cbfs.c:116: undefined reference to
`ulzman'
make: *** [build/cbfs/fallback/postcar.debug] Error 1

TEST=Build and run on Galileo Gen2

Change-Id: I7fa8ff33c0d32e0c5ff5de7918e13e6efb1df38e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15841
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 04:53:33 +02:00
Lee Leahy 27cd96a661 drivers/intel/fsp2_0: Enable XIP romstage with loaded FSP-M
Separate NO_XIP_EARLY_STAGES from loading FSP-M into cache-as-RAM.
Quark executes romstage directly from the SPI flash part (in-place),
but loads FSP-M into ESRAM.  This split occurs because ESRAM is too
small to hold everything while debugging.

Platforms executing FSP-M directly from the SPI flash need to select
FSP_M_XIP.

TEST=Build and run on Galileo Gen2.

Change-Id: Ib5313ae96dcec101510e82438b1889d315569696
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15848
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 01:21:58 +02:00
Lee Leahy e2422e38ce src/lib: Enable display of cbmem during romstage and postcar
Enable the display of cbmem during romstage and postcar.  Add a Kconfig
value to prevent coreboot images from increasing in size when this
feature is not in use.

TEST=Build and run on Galileo Gen2

Change-Id: Ib70ad517ebf7d37a7f46ba503b4432c7c04d7ded
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15842
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 01:18:09 +02:00
Lee Leahy 3eabe6e9ec drivers/uart: Enable debug serial output during postcar
Build the UART drivers for the postcar stage.

TEST=Build and run on Galileo Gen2

Change-Id: I8bf51135ab7e62fa4bc3e8d45583f2feac56942f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15843
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 23:28:32 +02:00
Furquan Shaikh b8257df83b intel/skylake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.

With recovery module in vboot handling the saving of recovery reason
across reboots, there is no need to have special fsp reset handling
under soc.

BUG=chrome-os-partner:55431

Change-Id: I0b7ce14868a322072d3e60c1dae43f211b43fdbf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15804
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 18:58:38 +02:00
Furquan Shaikh 7c7b291e55 intel/apollolake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.

BUG=chrome-os-partner:55431

Change-Id: If71802d2cba52a426f4c2db90d6c5384ed03ce68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15803
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:58:03 +02:00
Lin Huang 9dc00ef625 rockchip/rk3399: set CA drive strength to 48ohms
As shown in testing, if CA use 34.3ohms drive strength, it leads
to an overshoot. To fix this, change the drive strength to 48 ohms.

BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass

Change-Id: I8666474fc18391da14a3338611f962f2f08f36d0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: fbc1c13f9ab808fc907b2e3f9bde1d09f92980f1
Original-Change-Id: I231f5b1bd45ff262686fbacbaf119a8a57fad27b
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358761
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15811
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25 18:57:55 +02:00
Julius Werner de110ee07d google/gru: Change UART _Static_assert() condition to #if
_Static_assert() gets evaluated even when the code path it's in is
unreachable (e.g. inside an if (0) block). Unfortunately, Kconfigs that
depend on a disabled Kconfig are always 0, meaning that
CONFIG_CONSOLE_SERIAL_UART_ADDRESS on Gru cannot evaluate to UART2 when
CONFIG_CONSOLE_SERIAL (which it depends on) is disabled. Switch the
condition it is wrapped in to a preprocessor #if so that the
_Static_assert() is not evaluated when building without serial support.

BRANCH=None
BUG=None
TEST=Built and booted Kevin without serial

Change-Id: I391325fcc4b7d64b4866a7fce4444e2f28365b7d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: f5e5cf0644154eca5b347ea381df3f6b28287524
Original-Change-Id: I33d51d4ef09b218c14173d39a12795f0cef6bb40
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/361581
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15810
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25 18:57:32 +02:00
Furquan Shaikh 85aa135326 google/chromeos: Add support for saving recovery reason across reboot
On some x86 platforms (skylake, apollolake), we observe reboots at
different steps during the FSP initialization. These additional reboots
result in loss of recovery request because vboot_reference library
clears recovery request on vbnv once verification is complete and it has
made a decision about which boot path to take(normal/dev, slot-a/slot-b,
recovery).

Provide a way to allow mainboards/chipsets to inform recovery module in
vboot2 to save recovery reason to survive unexpected reboots. The
recovery reason is set in vbnv after vboot_reference library completes
its verification and clears the reason in vbnv while jumping to
payload.

BUG=chrome-os-partner:55431

Change-Id: Ie96be9aeb42c8209d8215943409e6327d6a8bf98
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15802
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 18:57:15 +02:00
Kan Yan 041bc76386 google/gale: Fix board ID and GPIO config.
Fix the board ID handling.
Recovery switch and WP status GPIO has been reassigned in board rev3.
Configure related GPIOs based on Board ID.

BUG=chrome-os-partner:55320
TEST=Verified GPIO assignment for Rev.1 board.
BRANCH=None

Change-Id: Id8e1ba1c039f8b5b503f0da038e5cfc84b72678f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: d295ab514e31d9ebd1b77e0af9b769e64cbf567e
Original-Change-Id: I6d3d5df2e9017f7845edc3cd0b2c19ad7c58a97c
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/361393
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/15809
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25 18:56:58 +02:00
Furquan Shaikh 8edfc1c512 lib/bootmode: Use newly-add recovery module
Use the newly added check recovery request function from recovery module
in vboot2 to check for a pending recovery request.

BUG=chrome-os-partner:55431

Change-Id: I354cc094f1e5d0044cf13e5bc28246f058d470c6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:56:06 +02:00
Furquan Shaikh 6d448e3aa6 google/chromeos: Add recovery module in vboot2
Add recovery module in vboot2 that checks if a recovery request is
pending and returns appropriate reason code:
1. Checks if recovery mode is initiated by EC.
2. Checks if recovery request is present in VBNV.
3. Checks if recovery request is present in handoff for post-cbmem
stages.
4. Checks if vboot verification is complete and looks up selected region
to identify if recovery is requested by vboot library.

BUG=chrome-os-partner:55431

Change-Id: I31e332a4d014a185df2434c3730954e08dc27281
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15800
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:51 +02:00
Furquan Shaikh a6c5ddd595 vboot: Clean up vboot code
1. Remove unused functions/structures.
2. Add checks for NULL return values.
3. Change prefixes to vb2 instead of vboot for functions used internally
within vboot2/
4. Get rid of vboot_handoff.h file and move the structure definition to
vboot_common.h
5. Rename all functions using handoff structure to have prefix
vboot_handoff_*. All the handoff functions can be run _only_ after cbmem
is online.
6. Organize vboot_common.h content according to different
functionalities.

BUG=chrome-os-partner:55431

Change-Id: I4c07d50327d88cddbdfbb0b6f82c264e2b8620eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:35 +02:00
Furquan Shaikh 610a33a7f4 skylake: Move CHROMEOS config to SoC
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.

BUG=chrome-os-partner:55431

Change-Id: Iafabb6373dfe16aaf0fe2cbc4e978952adeb403e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15822
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:21 +02:00
Furquan Shaikh 87b1bcc4af apollolake: Move CHROMEOS config to SoC
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.

BUG=chrome-os-partner:55431

Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:01 +02:00
Furquan Shaikh b1b465f093 intel/amenia: Add chromeos.c to verstage
BUG=chrome-os-partner:55431

Change-Id: I94fe54c12d7438a71f81a9053cc9785c0aa1e6cf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15823
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 18:54:50 +02:00
Daisuke Nojiri 5dd6a910da google/jecht: Increase RO coreboot size on flash
Bitmap images have been moved to CBFS from GBB. This patch adjusts the flash
size accordingly for jecht.

BUG=chromium:622501,chromium:628494
BRANCH=none
TEST=emerge-jecht chromeos-bootimage
CQ-DEPEND=CL:361380

Change-Id: I941df04b4999d35bd652e4ee1664c032cb550b29
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: c859ce04d2df5f21c47a164cabbc9ef6dec61818
Original-Change-Id: I50a9ade2e90237b0a7c277bffd7b540132415f13
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/361370
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15806
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25 18:54:01 +02:00
Subrata Banik 168eb6ad6f Makefile: Add uCode binary to FIT
Currently, on Intel Skylake the uCode binary is added to
CBFS based on the config option CBFS_EXTERNAL_HEADER. But
the entry is missing into the Firmware Interface Table, so
add it there.

BRANCH=none
BUG=chrome-os-partner:55403, chrome-os-partner:53077
TEST=built and verified FIT table has ucode entry.

Change-Id: I7dd7459ff7d2468f0aff66eb3ee9c2e3d7eda501
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15783
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-24 00:09:14 +02:00
Duncan Laurie 1e4c091e9b google/reef: Enable PS/2 keyboard driver by default
This device has a built-in keyboard that should be enabled by default
or it will not work in firmware.  This was tested to ensure that TAB
(display info) and Ctrl+D (enter developer mode) are functional at the
Chrome OS recovery screen.

BUG=chrome-os-partner:55549

Change-Id: I60156f1fc001b88deac69e03e02e9d8277fbc38d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15782
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-24 00:08:51 +02:00
Aaron Durbin 2c29d34b37 soc/intel/apollolake: ensure usb port 0 is in host mode
The controller for device mode USB is not plan of record
on apollolake. However, one still needs to configure the
one port to be host mode by default such that the devices
work as expected when plugged into the board.

BUG=chrome-os-partner:54581,chrome-os-partner:54656
TEST=Enabled xdci controller. Used USB type C->A dongle to
     check that a mass storage device worked on port 0 on
     reef.

Change-Id: Ia9ec5076491f31bc5dc3d534e235fb49f7b2efac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15781
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-24 00:08:22 +02:00
Aaron Durbin 5d208ff395 drivers/elog: remove elog Kconfig variables
Now that FMAP is a first class citizen in coreboot
there's no reason to have alternate locations for ELOG.
If one wants eventlog support they need to specify the
ELOG entry in the FMAP. The one side effect is that
the code was previously limiting the size to 4KiB
because the default ELOG_AREA_SIZE was 4KiB. However,
that's no longer the case as the FMAP region size is
honored.

Change-Id: I4ce5f15032387155d2f56f0de61f2d85271ba606
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15814
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-24 00:07:54 +02:00
Kyösti Mälkki e9a9c6a33c intel/haswell: Remove useless MTRR clear
At this state, variable MTRRs are disabled. We overwrite this MTRR entry
before they are re-enabled.

Change-Id: Ieedf90f65514d848905626e75be496e08f710d91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15794
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-23 19:15:20 +02:00
Kyösti Mälkki 3f22abb0a7 intel/haswell post-car: Minor fix on MTRR setting
Change-Id: I65f0ad430bdcc2065c1e873743da04201a68d9c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15796
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-23 19:10:21 +02:00
Kyösti Mälkki b37d01d309 intel/haswell: Add asmlinkage for romstage_after_car()
Change-Id: Ib3c973d2e89d4c25c3bf1e52662fbfcb4b1e4355
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15789
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-23 19:09:49 +02:00
Aaron Durbin a38677b664 cpu/x86/mtrr: correct variable MTRR calculation around 1MiB boundary
The fixed MTRRs cover the range [0:1MiB). While calculating the
variable MTRR usage the 1MiB boundary is checked such that
an excessive number of MTRRs aren't used because of unnatural
alignment at the low end of the physical address space. Howevever,
those checks weren't inclusive of the 1MiB boundary. As such a
variable MTRR could be used for a range which is actually covered
by the fixed MTRRs when the end address is equal to 1MiB. Likewise,
if the starting address of the range lands on the 1MiB boundary
then more variable MTRRs are calculated in order to meet natural
alignment requirements.

Before:
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x0000000000100000 size 0x00060000 type 0
0x0000000000100000 - 0x000000007b800000 size 0x7b700000 type 6
0x000000007b800000 - 0x00000000b0000000 size 0x34800000 type 0
0x00000000b0000000 - 0x00000000c0000000 size 0x10000000 type 1
0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6
CPU physical address size: 39 bits
MTRR: default type WB/UC MTRR counts: 7/17.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000007ffff00000 type 0
MTRR: 1 base 0x000000007b800000 mask 0x0000007fff800000 type 0
MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
MTRR: 3 base 0x0000000080000000 mask 0x0000007fe0000000 type 0
MTRR: 4 base 0x00000000a0000000 mask 0x0000007ff0000000 type 0
MTRR: 5 base 0x00000000b0000000 mask 0x0000007ff0000000 type 1
MTRR: 6 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0

After:
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x0000000000100000 size 0x00060000 type 0
0x0000000000100000 - 0x000000007b800000 size 0x7b700000 type 6
0x000000007b800000 - 0x00000000b0000000 size 0x34800000 type 0
0x00000000b0000000 - 0x00000000c0000000 size 0x10000000 type 1
0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6
CPU physical address size: 39 bits
MTRR: default type WB/UC MTRR counts: 6/8.
MTRR: WB selected as default type.
MTRR: 0 base 0x000000007b800000 mask 0x0000007fff800000 type 0
MTRR: 1 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
MTRR: 2 base 0x0000000080000000 mask 0x0000007fe0000000 type 0
MTRR: 3 base 0x00000000a0000000 mask 0x0000007ff0000000 type 0
MTRR: 4 base 0x00000000b0000000 mask 0x0000007ff0000000 type 1
MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0

BUG=chrome-os-partner:55504

Change-Id: I7feab38dfe135f5e596c9e67520378a406aa6866
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15780
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-22 21:38:54 +02:00
sselvar2 9d29c3cc31 intel/amenia: Write protect GPIO relative to bank offset
Update the write protect GPIO reported in ACPI to GPIO_75.
Also update the controller ID to "INT3452:01" which will
point at the goldmont device and includes write protect GPIO.

BUG=none
BRANCH=none
TEST=verify crossystem output for wpsw_cur.

Change-Id: Id6b172e289976072836746c1814e0300544a06cb
Signed-off-by: sselvar2 <susendra.selvaraj@intel.com>
Reviewed-on: https://coreboot.intel.com/7771
Reviewed-by: Sparry, Icarus W <icarus.w.sparry@intel.com>
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22 18:59:36 +02:00
Jagadish Krishnamoorthy df7ad44853 soc/intel/apollolake: Correct the gpio bank irq
The gpio bank irq is not correct and hence gpio
bank handler is never called in case of gpio based irq.
Correct the gpio bank irq to enable gpio based irq.

BUG=chrome-os-partner:55433
TEST=cat /proc/interrupts | grep INT3452 should
output 14.

Change-Id: I54253786425b7d4c2007043d49a91dfa6db0397b
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15756
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-22 18:57:48 +02:00
Fabian Kunkel cc19806ae7 amd/agesa/f16kb: Allow SATA Gen3
YangtzeSataResetService implements the SataSetMaxGen2 double.
The value should be only set, if the condition is met.
For testing, add
FchParams_env->Sata.SataMode.SataSetMaxGen2 = FALSE;
to your BiosCallOuts.c, which enables GEN3 for the SATA ports.
Patch is tested with bap/e20xx board, Lubuntu 16.04 Kernel 4.4.
$ dmesg | grep ahci #before patch
ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
$ dmesg | grep ahci #after patch
ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode

Change-Id: I17a493b876a4be3236736b2116b331e465b159af
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15728
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-22 18:56:42 +02:00
Sathyanarayana Nujella fc4c15b9e2 google/reef: Update gpio config for audio
This changelist updates gpio config for speaker SDMODE pin.
It disables speaker by default.
Audio kernel is expected to enable this when audio rendering starts.

Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8983e7
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/15433
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22 18:53:14 +02:00
Aaron Durbin 48f662d941 soc/intel/apollolake: clarify meaning of LPDDR4 density meaning
The 'dram density' is a misnomer because the memory initialization
code treats that input parameter as a per rank density. Therefore,
update the variables to further clarify how it's actually being
used.

BUG=chrome-os-partner:55446

Change-Id: Ie4c944f35b531812205ac0bb1c70f39ac401495e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15773
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22 18:51:29 +02:00
Aaron Durbin dd8ed42ed6 mainboard/google/reef: indicate dual rank LPDDR4 skus
The 16Gb devices use two ranks per channel within the DRAM module.
However, the density settings are really on a per rank basis so
indicate dual rank with a device density of 8Gb.

BUG=chrome-os-partner:55446

Change-Id: Ib5dba6f9ed248750d68b726996c71def9b75961e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15772
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-22 18:51:08 +02:00
Aaron Durbin 17dbec1593 soc/intel/apollolake: add dual rank option to meminit
Despite the UPD comments the Chx_RankEnable fields are a bit
mask which indicates which ranks are enabled for physical
channel. Add the ability to set the rank mask correctly for
dual rank LPDDR4 modules.

BUG=chrome-os-partner:55446

Change-Id: I9dbed7bb6a4b512e57f6b4481180932a7cce91ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15771
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22 18:50:49 +02:00
Aaron Durbin aa00e0893e soc/intel/apollolake: die() when FSP silicon init fails
The reset requests are handled in the FSP 2.0 wrapper, but
the current code doesn't check any non-successful return
values. Provide parity with the memory init path which die()s
under those circumstances.

Change-Id: I9df61323f742b4e94294321e3ca3ab58a68ca4dd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15766
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-22 18:50:40 +02:00
Kyösti Mälkki 8a2f167e7b intel car: Unify postcodes
Not all are matched, but this makes it easier to backport
MTRR changes from haswell.

Change-Id: Ida5943b1469fc0089a31ff3b18131fb82b0941c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15760
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22 05:40:13 +02:00
Kyösti Mälkki eb61ea84f7 intel car: Unify whitespace and comment fixes
Change-Id: Icd0cc7d27f38bdaee6addb98abec6f310cdd9fae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15759
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22 05:39:39 +02:00
Kyösti Mälkki 9ec691429f intel car: Remove guard on XIP_ROM_SIZE
These guards have been removed starting with model_206ax.

Change-Id: Id63034ec4080e37eee2c120aa1f1ef604db5b203
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15758
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-22 05:39:03 +02:00
Kyösti Mälkki a27fba67a0 intel model_106cx: Include CAR from socket directory
Since the socket layer is implemented with this CPU model, there
could potentially be multiple CPU models included.  There can be
only one cache_as_ram include, so select it directly within
the socket directory.

Change-Id: Ia52bb152276eddfd1fb33ddb7f5d153ab8e8163c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15757
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22 05:38:38 +02:00
Aaron Durbin 81527e8d7f mainboard/google/reef: handle eMMC power signal polarity change
The EVT board uses an active high power control signal while
the previous board used an active low signal. Update the tables
to reflect the differences.

BUG=chrome-os-partner:55470

Change-Id: I198c0e4e019fcffe2cf748d382351ac965a81077
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15763
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21 16:38:18 +02:00
Aaron Durbin ede69f0d62 mainboard/google/reef: reverse the memory config bits
I mistakenly assumed the order of the bits matched how one
would assign values as they wrote them msb .. lsb. However, the
gpio lib doesn't do that. Correct the order so that values are
read out correctly.

BUG=chrome-os-partner:54949t

Change-Id: I5304dfe2ba6f8eb073acab3377327167573ec2cc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15753
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21 15:57:16 +02:00