Commit Graph

31324 Commits

Author SHA1 Message Date
Arthur Heymans 5331a7cff9 Program loading: Handoff cbmem_top via calling arguments
There are a lot of different implementations to pass information from
romstage to ramstage. These could all be unified by passing this
information via cbmem. Often however these methods exist for that very
purpose. This solves this by passing cbmem_top via the programs
arguments.

Change-Id: Id2031f7bb81ce65fc318313c270eb1fbae3b2114
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36272
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:33:07 +00:00
Arthur Heymans b7cc68ae6a arch/x86/boot.c: Pass arguments when running programs
Payloads can use coreboot tables passed on via arguments instead of
via a pointer in lower memory.

Stages can make use of the argument to pass on information.

Change-Id: Ie0f44e9e1992221e02c49d0492cdd2a3d9013560
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36143
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:32:39 +00:00
Michael Niewöhner 9b8d28f013 soc/intel/apollolake: set FSP param to enable or skip GOP
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to
enable or skip GOP.

Change-Id: I3546371dd18120e3fbd1179a79b2bdc0a7436726
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30 08:31:43 +00:00
Michael Niewöhner 1f30de08f6 soc/intel/cannonlake: set FSP param to enable or skip GOP
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to
enable or skip GOP.

Change-Id: I7f7b2c688e46534046dc0976458c4c96614100b0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30 08:31:22 +00:00
Michael Niewöhner e0ad1fa7c8 soc/intel/common: move common memmap functionality from skl,icl,cnl,apl
This moves common memmap functionality from skl,icl,cnl,apl to the common tree.

Change-Id: I45ddfabeac806ad5ff62da97ec1409c6bb9e89ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36410
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:30:16 +00:00
Arthur Heymans a1dbcb9332 arch/x86/Makefile.inc: Use the 'all' target to add common sources
Change-Id: Ibbd418656c32f56be2b00481068e8499421b147c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30 08:28:50 +00:00
Arthur Heymans 5e5fd41fcf Makefile.inc: Add a class 'all' to link files in all stage except SMM
Change-Id: I955dd2dc22cb3cfc4fdf1198cfd32f56475f97c9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33198
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:26:54 +00:00
Paul Fagerburg 4d77bf2a23 hatch: refactor gpio table into baseboard, allow empty SPDs
Each variant needed to define variant_early_gpio_table(), even if
it didn't need to make any changes. Added a __weak version of the
function into baseboard/gpio.c.

Certain upcoming Hatch variants will not use SPD files. Allow
SPD_SOURCES in spd/Makefile.inc to be empty.

BUG=None
BRANCH=None
TEST=Build coreboot and see that it builds without error

Change-Id: Ie946cfd7c071824168faa38fd53bd338a5a451e1
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36068
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:26:31 +00:00
Paul Fagerburg f1ca63ca40 automation: add GPIOs and version number, change branch name
* Add defines for GPIO_MEM_CONFIG_0:3 in the template file, so
that code that relies on these defines can compile. Because they
are preprocessor symbols, there is no way to define them as
__weak in the baseboard header and allow the variant to override
as needed, so they need to be defined here and changed if needed.
* Add a version number for the script and an "auto-generated by"
line in the git commit message.
* Change the branch name so that it's not the same as the ones
that the other scripts will create, so that repo upload on those
CLs won't affect this one.

BUG=b:140261109
BRANCH=None
TEST=Create and build the "sushi" variant:
$ util/mainboard/google/hatch/create_coreboot_variant.sh sushi
$ util/abuild/abuild -p none -t google/hatch -x -a

Prior to this CL, you would get an error message that SPD_SOURCES is
not set. If you fixed that, then you would get failures for
GPIO_MEM_CONFIG_0, _1, _2, and _3 not defined, and/or gpio_table[]
and early_gpio_table[] not defined. After the CL, the build proceeds.

Change-Id: I0f48d6bb9544cad6d419d3a6fbb17f57200938b2
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36408
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:26:16 +00:00
Martin Roth 480d927b02 LICENSES: Add licenses used in the coreboot repo
Here are example locations of these licenses:
    Apache-2.0 - src/soc/sifive
    BSD-3-Clause - Throughout coreboot & libpayload source
CC-BY-4.0 - Documentation
CC-BY-SA-3.0 - Documentation/community/code_of_conduct.md
    GPL-2.0-only - Throughout coreboot source
    GPL-2.0-or-later - Throughout coreboot source
    GPL-3.0-only - util/amdtools
    GPL-3.0-or-later - src/lib/[gcov/libgcov/gnat]
    ISC - src/lib/ubsan.c, soc/qualcomm/ipq806x/include/soc/gsbi.h, others
    MIT - soc/nvidia/tegra210/mipi_dsi.c, files in mainboard/cavium/
    X11 - include/device/drm_dp_helper.h, drivers/aspeed/common/ast_tables.h

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icf20c0227d4fe8efb0d337a76935797a1bc33f0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-30 08:23:51 +00:00
Iru Cai b559432604 mainboard: Add Lenovo ThinkPad T440p
The code is based on autoport.

This port is tested on a T440p without a dGPU and can boot Arch Linux
from SATA disk with SeaBIOS payload. The tested components and issues
are in the documentation.

Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:21:13 +00:00
Tim Wawrzynczak eef992deac commonlib/helpers: Add alloca() macro
If there is no alloca() macro defined, then define it as
__builtin_alloca(), as most compilers support that as an intrinsic
instead, if no alloca.h is included.

Change-Id: I8730d57ce7c2f323b52e7a5720c598fb7af16b44
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36387
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:20:39 +00:00
Patrick Rudolph 776da0872e arch/x86/*.S: use defines instead of hardcoded values
As preparation for x86_64 clean the assembly code and introduce
arch/ram_segs.h similar to existing arch/rom_segs.h.

Replace open coded segment values with the defines from the new
header.

Change-Id: Ib006cd4df59951335506b8153e9347450ec3403e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36321
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-29 19:41:19 +00:00
Maxim Polyakov 5f2576089f soc/skylake/vr_config: print mch_id in hex
Change-Id: I89e2bccf3fb99b20dde38745fc124d5dc95feb78
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-29 15:15:07 +00:00
Joe Moore b7f117dd52 Documentation/releases: Note pending AMD fam12h removal
Change-Id: I386572c772ea9de571bbb9d51ef9090e9c429b99
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-29 13:13:18 +00:00
Tim Wawrzynczak b5c345ab44 ec/google/chromeec: Clean up ec.[ch]
Change all uN integral types to uintN_t.  Make the names of host
command params/responses consistent.  Use static struct initialization
to ensure all fields are initialized.

BUG=none
BRANCH=none
TEST=compiles

Change-Id: Ibe1e29e88975c85eea215adedc5f5e483243e0d6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-29 13:12:55 +00:00
Elyes HAOUAS 44b275e209 nb/intel/{nehalem,x4x}: Remove unused 'include <pc80/vga_io.h>'
Change-Id: If9c743335ab09038c9e22d1f4d3b7411585b2c8c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-29 13:07:27 +00:00
Matt DeVillier 4223880d54 purism/librem_skl: add libgfxinit support
Panel settings taken from KBL FSP sample vbt.bin

Test: build/boot librem13v2/15v3 with libgfxinit init,
verify both LFB and text modes functional

Change-Id: I9582065603417e53704244e95dde51a59f709664
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-29 12:57:02 +00:00
Nico Huber 21961fc092 3rdparty/libgfxinit: Update submodule pointer
This includes a huge set of refactorings to support Core Display Clock
(CDClk) frequency switching based on the current mode requirements.

The CDClk is configurable since Haswell and runtime switching is suppor-
ted since Broadwell. Always using the lowest possible frequency setting
should allow some power-savings. While, on the upper end, we can support
higher resolution panels now, without having to change the static confi-
guration.

There have also been some smaller changes and fixes, including:
  o Parsing of eDP 1.4+ DPCD link rates, enables panels that don't
    advertise a maximum link rate but only individual ones.
  o DP support for Ibex Peak.
  o Corrected limit for HDMI on G45 to 165MHz.
  o Reworked GMBUS reset handling and timeouts, should help with
    stalled GMBUS controllers when unimplemented ports were probed
    by accident.

Tested on various boards from GM45 to KBL-R.

Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-29 10:46:41 +00:00
Michael Niewöhner 7f57dd4b65 src/soc/intel: skl,cnl,icl: remove unneeded check in cbmem_top()
As stated in CB:36334 cbmem_top() should not be called before memory is
initialized. Therefore drop the check to see if MRC finished.

Change-Id: I964a20a5e9aa69fdb75413c36a17d34b7ba00098
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36386
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28 18:54:13 +00:00
Andrey Petrov 0108c8b742 soc/intel/broadwell_de: Implement smbios_cpu_get_maximum_freq_mhz()
Determine maximum speed by looking at either turbo flex limit or
uncore ratio limit.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I0f3a64a40cb1d28d8eb9380c2071ec748e345b88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28 18:27:35 +00:00
Andrey Petrov 2e032f07df arch/x86: Populate more fields in SMBIOS type 4
If CPUID leaf 0x16 is available (Skylake and later) use it to obtain
current and maximum speed. Otherwise call weak function that can be
provided elsewhere (cpu/soc/mainboard). Also, populate "core enabled"
with the same value as "core count".

TEST=tested on OCP Monolake with dmidecode -t processor

Change-Id: Ie5d88dacae6623dfa0ceb3ca1bb5eeff2adda103
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28 18:27:24 +00:00
Andrey Petrov b8eaa6a584 arch/x86: Move max cpuid leaf function into arch/x86
This cpuid function (0) is same across Intel and AMD so having it in
arch/x86 seems like a good idea.

Change-Id: I38f1c40bceac38ed6428f74b08bf60b971644f5a
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28 18:26:50 +00:00
Felix Singer 19e353473d inteltool: Add method 'print_system_info'
To get a better idea what this code does, this patch adds
a new method called 'print_system_info'.

Change-Id: I16f1c9cdc402b1a816fac65d1490432e39c07baf
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36315
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28 12:00:46 +00:00
Arthur Heymans be9533aba9 nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support
The i82801ix_early_init is now called both in the bootblock and
romstage. The rationale behind setting this up twice is to ensure
bootblock-romstage compatibility in the future if for instance VBOOT
is used.

This moves the console init to the bootblock.

The romstage now runs uncached. Adding a prog_run hooks to set up an
MTRR to cache the romstage will be done in a followup patch.

The default size of 64KiB is not modified for the bootblock as trying
to fit both EHCI and SPI flash debugging needs a more space and 64KiB
is the next power of 2 size that fits it.

TESTED on Thinkpad X200.

Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-28 11:59:17 +00:00
Arthur Heymans 942ad6a137 cpu/intel/car: Correctly cache the bootblock with C_ENVIRONMENT_BOOTBLOCK
With CONFIG_C_ENVIRONMENT_BOOTBLOCK it makes more sense to rely on the
size of the bootblock over CONFIG_XIP_ROM_SIZE. To make this work,
only powers of 2 are allowed as bootblock size.

Change-Id: Ic8104ca9c51e4d2eccdb277e4c2111d2da662f3e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-28 11:59:03 +00:00
Yu-Ping Wu 947916eb2d soc/mediatek/mt8183: Pass MR values as function arguments
To make data flow more explicit, global variables 'MR01Value' and
'MR13Value' are replaced with local variables, which are passed as
function arguments.

BRANCH=kukui
BUG=none
TEST=1. emerge-kukui coreboot
     2. Fast calibration succeeded

Change-Id: Id21483092c86c3ae7dbb1173a2b943defe41a379
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-28 11:58:24 +00:00
Elyes HAOUAS 845652b8bb src/cpu: Use 'include <stdlib.h>' when appropriate
Also:
 add some missing includes spotted by Jenkins.
 Including <types.h>, is supposed to provide stdint and stddef.

Change-Id: I7bd999b59d1c0bdfa5999bf5805576f94c9a2390
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-28 11:57:23 +00:00
Elyes HAOUAS 400f9ca261 src/southbridge: Use 'include <stdlib.h>' when appropriate
Also, including <types.h>, is supposed to provide stdint and stddef.

Change-Id: I7e1a3483aae0e3f0a7bc2eb2c1862ae7a325fd9c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-28 11:57:01 +00:00
Elyes HAOUAS 34715df801 src: Remove unused '#include <cpu/cpu.h>'
Change-Id: Ibcb1cafe36c255b4c5bd0a4faeedb95e91048709
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-28 11:56:38 +00:00
Bill XIE d8b6e671f1 mb/lenovo/x200: Correct device tree override logic
If a device node should be enabled on some variants, but disabled on
others, it had better be declared as disabled (rather than absent) in
base device tree (rather than override tree for the variant disabling
it), and enabled in override tree for the variant needing it, so that
it does not need to be declared once more when adding another variant
with such node disabled.

Change-Id: I4b28360905ae38149ace9ac5d21cd6d5045b7584
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-28 11:55:59 +00:00
Arthur Heymans 7c24de9cb7 lib/cbfs: Don't load XIP stages from bootblock
This should improve boot times as it skips unnecessary read and
writes.

Change-Id: I8cf36613903783e741b2e3bfeeee5bc29ab26d5b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-28 11:55:31 +00:00
Karthikeyan Ramasubramanian 158e8d1e92 mb/google/sarien/arcada: Add support for Cirque Touchpad
Add Cirque Touchpad devicetree configuration to export relevant ACPI
objects to the kernel.

BUG=b:141259109
BRANCH=sarien
TEST=Boot to ChromeOS. Ensure that relevant ACPI objects are exported in
the SSDT.

Change-Id: I91dcb27b86c6a2bed5579f1f6c1102871d55b315
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-28 11:54:56 +00:00
Frans Hendriks fc58034a11 lib/prog_loaders.c: Add prog_locate_hook()
There is no posibility to prevent loading images from cbfs at this stage
For security features prog_locate_hook() is added. This hook can be used
to prevent loading the image.

BUG=N/A
TEST=Created verified binary and verify logging on Facebook FBG-1701

Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-28 11:54:44 +00:00
Arthur Heymans 11b910281e Documentation/writing_documentation.md: Explain how to use docker
Using docker to build to documentation eases the process of building
the documentation. Given that some versions of sphinx are
incompatible, the option to use docker is presented first.

Change-Id: I6c18f81a829364ada1859c04ba2dc4f886934bcc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36105
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27 23:36:07 +00:00
Nick Vaccaro 523ca8d9b0 mb/google/poppy/variant/nocturne: don't invert GPP_D17
This change removes an inversion of GPP_D17 that caused the
device to get stuck in a reboot loop because the kernel was crashing
within the first couple seconds of kernel boot.

BUG=b:142515200
BRANCH=none
TEST=Flash and boot nocturne, verify boot is stable and that device
doesn't reboot after jumping into kernel, and that it passes the
'tast -verbose run <ip> hardware.SensorRing' test.

Change-Id: Ia1408ef6ea92f6b31a9f3eee8720954af3a7c382
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35967
Reviewed-by: Yicheng Li <yichengli@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27 23:33:01 +00:00
Wisley Chen d3856aad79 Dragonair: Add sku23
BUG=b:142987639
TEST=emerge-hatch coreboot

Change-Id: I0ff1a81d0579d0b328a48bc7d4f867592ec63e8b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-27 22:43:02 +00:00
Michael Niewöhner f7856800b4 mb/supermicro/x11-lga1151: use the new Kconfig to hide GOP
The board does not have any graphics port connected to the SoC. Hence,
use the new Kconfig to hide GOP initialization.

Change-Id: Ia88e062bea243369da27b94608f89f0808257688
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-27 22:17:29 +00:00
Michael Niewöhner d61a40e291 device: add Kconfig option to hide GOP initialization option
There are mainboards that do not have any graphics ports connected to
the SoC. It would be senseless to initialize the iGD, thus add a new
mainboard Kconfig to hide the GOP option.

Change-Id: Ica3b3a7a0c8120c95412369a24d8d669fb59fded
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-27 22:17:06 +00:00
Martin Roth 57e8909081 src/soc: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I9c1228d3f9e7a12fe30c48e3b1f143520fed875c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27 21:08:58 +00:00
Martin Roth ad0f485361 src/mainboard: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I46d131f76ec930d2ef0f74e6eaabae067df10754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27 21:08:49 +00:00
Martin Roth 38ddbfb325 src/[arch-lib]: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27 21:08:39 +00:00
Elyes HAOUAS e74ca4ffc2 mb/supermicro/h8scm_fam10: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Found-by: ACPICA 20191018
Change-Id: I9f6c025a548e60a91d8064b0aeaf4d8530d78305
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 20:59:51 +00:00
Elyes HAOUAS bdc761e338 mb/amd/serengeti_cheetah_fam10: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: I1650df927aa6d4a1282ed50b2bcbb63d5bd04347
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 19:05:02 +00:00
Elyes HAOUAS 8896dc85de mb/msi/ms7721: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: Ib70b349742fb636e25f1369d54641997e57a2045
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 19:04:24 +00:00
Elyes HAOUAS d115940d80 mb/lippert: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: I5761b093b43aa7d97a6b84730a4009a5d163550d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 19:04:00 +00:00
Elyes HAOUAS 6c361d6838 mb/jetway: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: Ib454fc76db0b45332326772b8d1f295429107133
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 19:03:03 +00:00
Martin Roth 468d02cc82 src/[northbridge,security]: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If6b5930f78c3da6dcefaa7b6202cd0424a24525b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-27 18:12:50 +00:00
Elyes HAOUAS 36fcc85be4 mb/iei: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: I547be16285787ee3578f855111ca177be047ced2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 18:12:17 +00:00
Elyes HAOUAS 8484a12a9c mb/gigabyte: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: Ia27308ba17c6b5c836ada6278f7d26631e09c022
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 18:11:43 +00:00