Commit Graph

23953 Commits

Author SHA1 Message Date
Shaunak Saha cf1ba95fa4 mb/glkrvp: Set PNP config to PNP_PERF_POWER
This patch sets the PNP config value to PNP_PERF_POWER.
The config values for soc can be found in chip.h

TEST = Built and booted glkrvp, verified warm and cold
reboot and suspend resume.

Change-Id: Ia390c0fafe2de64bd9e4ca44e5ed5d904663ae3c
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-25 17:55:53 +00:00
Furquan Shaikh d18f42ab6f mb/google/octopus: Select TPM options only if mocktpm is not selected
This change adds a new Kconfig option for mainboard octopus "HAS_TPM"
that auto-selects all TPM related options only if VBOOT_MOCK_SECDATA
is not selected.

BUG=b:76203913
TEST=Compiles fine with mocktpm.

Change-Id: Ib28fc47a70be58cd9a9ec65ce3b1cda68d558437
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25340
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-24 05:17:07 +00:00
Raul E Rangel 80d042c467 soc/amd: Print dimm_info and TYPE17_DMI_INFO to help debug incorrect values
Example output:
AGESA TYPE 17 DMI INFO:
  Handle: 1
  TotalWidth: 64
  DataWidth: 64
  MemorySize: 8192
  DeviceSet: 0
  Speed: 1200
  ManufacturerIdCode: 44416
  Attributes: 1
  ExtSize: 0
  ConfigSpeed: 933
  MemoryType: 0x1a
  FormFactor: 0xd
  DeviceLocator:   DIMM 0
  BankLocator:  CHANNEL A
  SerialNumber(8):  00000000
  PartNumber(20): HMAA51S6AMR6N-UH

CBMEM_ID_MEMINFO:
  dimm_size: 0
  ddr_type: 0x1a
  ddr_frequency: 1200
  rank_per_dimm: 1
  channel_num: 0
  dimm_num: 0
  bank_locator: 0
  mod_id: 44416
  mod_type: 0x1a
  bus_width: 64
  serial(4): 0000
  module_part_number(23): HMAA51S6AMR6N-UH   ��@

dimm_size, mod_type, bus_width need to be updated so they return the
correct values. module_part_number is missing a null terminator due to
the AGESA part number being larger than the dimm_info buffer.

Example dmidecode output:
Memory Device
        Array Handle: 0x0000
        Error Information Handle: Not Provided
        Total Width: 8 bits
        Data Width: 8 bits
        Size: No Module Installed
        Form Factor: Unknown
        Set: None
        Locator: Channel-0-DIMM-0
        Bank Locator: BANK 0
        Type: DDR4
        Type Detail: Synchronous
        Speed: 1200 MT/s
        Manufacturer: Hynix/Hyundai
        Serial Number: 0000
        Asset Tag: Not Specified
        Part Number: HMAA51S6AMR6N-UH
        Rank: 1
        Configured Clock Speed: 1200 MT/s
        Minimum Voltage: Unknown
        Maximum Voltage: Unknown
        Configured Voltage: Unknown

To enable the output set CONFIG_DEBUG_RAM_SETUP.

The Kconfig change is required in order to enable
CONFIG_DEBUG_RAM_SETUP, otherwise it's not a valid option.

BUG=b:65403853
TEST=Test output shown above

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5eac00b9400056357915761287770a400b3f9f8b
Reviewed-on: https://review.coreboot.org/25303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-23 15:33:27 +00:00
Raul E Rangel 50021cdb06 arch/x86/smbios: Strip trailing whitespace on DMI 17 part number.
dmidecode used to print

    'HMAA51S6AMR6N-UH  '

it now prints

    'HMAA51S6AMR6N-UH'

BUG=b:65403853
TEST=Verified using dmidecode

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia10ef434a2377e34ae7a8f733c6465c2f8ee8dfa
Reviewed-on: https://review.coreboot.org/25302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-23 15:33:16 +00:00
Raul E Rangel 5041e9b416 include: Update dimm_info documentation
Reference the JEDEC SPD spec and clarify some comments.

BRANCH=dimm-info
BUG=b:65403853
TEST=Documentation change only

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1f2a3a70919c34f17472904323ec5accdfc876be
Reviewed-on: https://review.coreboot.org/25301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-23 15:33:09 +00:00
Vaibhav Shankar 8cf149007f mainboard/intel/cannonlake_rvp: Enable S0ix
This patch enables S0ix from the devicetree.

Change-Id: I38662dc7203366bdee5f1c7aaa18979867a79ba1
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25293
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23 08:56:34 +00:00
Vaibhav Shankar 2da6ec40bb soc/intel/cannonlake: Enable low power S0 Idle capability
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0
if S0ix is enabled for the platform. This also sets the
FSPUPD to indicate the status of S0ix on the platform.

TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag
      is set in FACP table - FADT.Flags[21] bit.

Change-Id: I6214ebb61f25ef8b704e60c8474808493c92e6f6
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25292
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23 08:56:19 +00:00
Nick Vaccaro 8330866067 mb/google/zoombini: always report EC is in RO mode
Always report that EC is in RO mode.  This is a temporary workaround
for a hardware issue that is causing EC to appear to be in RW mode
when it is not.  This change will be reverted once transition is made
to newer hardware.

BUG=b:74215817
BRANCH=master
TEST=Verify meowth can boot to recovery's insert screen.

Change-Id: Ib3705bba0bb1f351da79e599566fbffab94428f3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-23 08:54:59 +00:00
V Sowmya efce854fc6 mb/intel/kblrvp8: Add KBLRVP8 support
Add the config for setting SPD DIMM size to 512 bytes
for KBLRVP8 with DDR4 memory. Configure the DIMM1 memory
SPD data for channel0 and channel1. Set the UserBd UPD to
BOARD_TYPE_DESKTOP for kblrvp8.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I985968d331991884050c3920ec9798cd4cb371c7
Reviewed-on: https://review.coreboot.org/25194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-03-23 08:54:33 +00:00
Patrick Rudolph 57afc5e0f2 arch/arm64/armv8/mmu: Add support for 48bit VA
The VA space needs to be extended to support 48bit, as on Cavium SoCs
the MMIO starts at 1 << 47.

The following changes were done to coreboot and libpayload:
 * Use page table lvl 0
 * Increase VA bits to 48
 * Enable 256TB in MMU controller
 * Add additional asserts

Tested on Cavium SoC and two ARM64 Chromebooks.

Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/24970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-03-23 04:09:50 +00:00
Shamile Khan 3d9462a07f soc/intel/apollolake: Bypass FSP's deassertion of PERST# signal.
BUG=b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I1858c7843d16b6b63fc30762a889916bbb9b781a
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23 01:23:20 +00:00
Srinidhi N Kaushik 5b2a4b4087 vendorcode/intel: Update FSP Header files per v2.0.0
Update FSP header files to match GLK FSP Reference Code Release v2.0.0

Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/25247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-23 01:23:14 +00:00
Paul Menzel 4183260304 payloads/seabios: Update stable from 1.11.0 to 1.11.1
SeaBIOS 1.11.1 was released with the changes below.

```
$ git log --oneline rel-1.11.0..rel-1.11.1
0551a4b paravirt: Only enable sercon in NOGRAPHIC mode if no other console
        specified
a7aa43e pci: fix 'io hints' capability for RedHat PCI bridges
0e739f2 shadow: Don't invoke a shutdown on reboot unless in a reboot loop
5d9a515 build: Use git describe --always
```

Change-Id: Ia77e98edcd42b28677de9670ce13c2ea5d327315
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/25284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-03-22 15:28:33 +00:00
Nick Vaccaro 579d4550d2 mb/google/zoombini: Enable NVMe
BUG=b:72120814
BRANCH=master
TEST=none

Change-Id: I64ab38dda78345c1f3d7d3f2bf3cb04c19290ceb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-22 09:01:54 +00:00
Shamile Khan 25c1781cba mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FI
BUG=b:73292699
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: Ic73ad38ad9a12bec614e530f7f35619246b9f57f
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25288
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-22 09:01:38 +00:00
Marshall Dawson 70f051f236 amd/stoneyridge: Add PM1 wake status to boot log
Print the wake status bits to the console.  The format is kept similar
to Intel's to maintain compatilibity with inspection utilities.  Add
relevant wake events from the register to the ELOG.  Clear the register
before continuing.

TEST=Inspect console and ELOG for Grunt
BUG=b:75020968

Change-Id: Idc9d12326abb290e4f7a5c60677eb6e057d475b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-03-22 09:01:03 +00:00
Lijian Zhao 5479525c74 intel/fsp: Update Cannonlake FSP header
Update Cannonlake FSP header to version 7.x.2A.20, the following changes
were made:
    1. Add MemtestonWarmBoot option.
    2. Add enable8254clockgatingonS3 option.
    3. Default disable Tccoffsetlock

BUG=None
TEST=None

Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-03-22 09:00:48 +00:00
Furquan Shaikh a3ad990089 soc/intel/skylake: Define IFD_CHIPSET
This change defines IFD_CHIPSET as sklkbl to allow ifdtool to set the
right access control bits for SKL/KBL platforms.

BUG=b:76098647
BRANCH=poppy
TEST=Verified that the access control bits on KBL platforms are set correctly.

Change-Id: I7b2131caa06d6a975e703262931ec0ea519a86aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-22 05:04:06 +00:00
Furquan Shaikh 088b6e8f8b util/ifdtool: Fix region access control for SKL/KBL
The default values used by ifdtool for setting region access control
do not match the expected values for SKL/KBL as per the SPI
programming guide. This change adds platform "sklkbl" that sets region
access control bits differently for SKL/KBL images.

BUG=b:76098647
BRANCH=poppy
TEST=Verified that the access control bits on KBL images is set
correctly.

Change-Id: I1328d8006c25be282b3223268d8f1fd0a64e2ed3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-22 05:03:58 +00:00
Piotr Król 5044b01697 MAINTAINERS: change second PC Engines maintainer
Change-Id: I5eac0ae55e759ac9eb26783c11057db15fa62574
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/25254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-21 18:25:49 +00:00
Zhongze Hu 1fa724b40c mb/google/fizz: Enable I2C bus 2
I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase
it was idle.

Google CFM add-in card is going to use this I2C bus so it needs to be
re-enabled.

BUG=b:73006317
TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is
working properly.

Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/25258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2018-03-21 18:25:25 +00:00
Srinidhi N Kaushik d90d17c544 mb/intel/glkrvp: Re-size flash WP_RO segment
Update the size in WP_RO segment of the flash to accommodate builds using
debug FSP.

Change-Id: I8b24422e1eef2d0a81006286d4fc58f238fdce11
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/25255
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21 18:24:53 +00:00
Srinidhi N Kaushik 445d553af8 mb/google/octopus: Re-size flash WP_RO segment
Update the size in WP_RO segment of the flash to accommodate builds using
debug FSP.

Change-Id: I0a0d1d0121b503ff390adf3ce25973d72e59fdeb
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/25253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-21 18:24:26 +00:00
Justin TerAvest 4a664fa61b mb/google/octopus: Create bip variant
This creates a bip variant for octopus. Nothing is set in the variant
files here-- everything is picked up from baseboard.

BUG=b:75976864
TEST=None

Change-Id: I7a8ac3d8bb71416f05ef1a605684d92d5902abda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25285
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21 18:24:05 +00:00
Martin Roth d0bc79be47 mainboard/google/kahlee: Update GPIOs based on board ID
BUG=b:73078053
TEST=build & boot Grunt

Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-21 18:23:07 +00:00
Zhuohao Lee f7b5955b36 mb/google/poppy/variants/nami: change type of board_sku_id() to uint32_t
Tools/scripts, like mosys/arc-setup, use int (4 bytes) to
read the sku id. In order to support "-1", we need to use
uint32_t (4 bytes) instead of using uint16_t (2 bytes) data type.
Otherwise, tools/scripts will read 65535 instead of -1.
Another reason to change this is that sku_id can be
supported by ec up to 4 bytes.

BUG=b:73792190
TEST=mosys output "Platform not supported" for -1 sku id
     arc-setup read -1 sku id

Change-Id: Ib3baa8419f138abeb412ac09c2e7dc608e3b758b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/25252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-21 16:02:26 +00:00
Ravi Sarawadi c293496f41 mb/google/octopus: Enable TPM on GSPI
BUG=b:73133848
BRANCH=None
TEST=Build coreboot for Octopus board. Tested the GSPI interface
with a SPI EEPROM and got correct response to a RDID command

Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/24907
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21 16:01:05 +00:00
Maulik V Vaghela 794d097072 drivers/i2c/designware: Fix indentation
Remove extra tab before printk statement.

Change-Id: Id82239f74ac030f25000a08764637f6d1b52b87b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/25295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-21 15:56:55 +00:00
Seunghwan Kim 05132707ca mb/google/poppy/variant/nautilus: Enable CABC feature as default
This change configures GPP_E22 to GPO_HIGH to enable CABC feature
on nautilus board.

BUG=b:68789889
BRANCH=poppy
TEST=emerge-nautilus coreboot

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: Ifed0d37bf8147aa1b580f594f36f186051c2eb52
Reviewed-on: https://review.coreboot.org/25120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-21 05:12:56 +00:00
Akshu Agrawal e11a11265b mb/google/kahlee: Add register address mapping for FCH MISC
Audio machine driver will enable/disable clock by making it as
a CCF clock in kernel.

BUG=b:74570989
TEST=cherry-picked https://patchwork.kernel.org/patch/10291875/
on 4.14 kernel
aplay -vv <file>
check register to see clock enabled
kill aplay
check register to see clock disabled

Change-Id: Ia553e55ffb358415067000d2d2d2744322d1c4db
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-21 03:55:11 +00:00
Martin Roth bf7dea0028 mainboard/google/kahlee: Initialize EC earlier in the bootblock
Set up the EC communication a little earlier so we can read the board
ID before programming GPIOS.

BUG=b:73078053
TEST=Build & Boot grunt, board_id() now gets ID correctly

Change-Id: Icf3f598824cfed69fa03ba2bb86503bb3c3699a5
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25286
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-20 22:44:57 +00:00
Ravi Sarawadi 3669a06c95 soc/intel/apollolake: Add support for GSPI
BUG=b:73133848
BRANCH=None
TEST=Build coreboot for Octopus board. Tested the GSPI interface
with a SPI EEPROM and got correct response to a RDID command

Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/24906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-20 02:04:06 +00:00
Lijian Zhao f46bd35663 drivers/intel/wifi: Add Jefferson Peak Device ID
The following PCI device ID can be included for jefferson peak wifi
devices driver support, and they are:
	9df0 for jefferson peak on Cannonlake-LP w/CNVi
	A370 for jefferson peak on Cannonlake-H w/CNVi
	31dc for jefferson peak on Geminilake w/CNVi

BUG=None
TEST=None

Change-Id: I48886cea5578a302f6ef033cb35df4a38bd64ea8
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19 22:37:52 +00:00
Justin TerAvest 3cb00ef84e mb/google/octopus: Configure PERST_0 pin
According to the schematic, Octopus boards have WLAN_PE_RST connected to
GPIO_164. This change configures that properly in devicetree.

BUG=None
TEST=None

Change-Id: I2ba4839e036f02c5e0316d08599894879133894a
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25248
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19 15:31:48 +00:00
Justin TerAvest 22595f6e45 mb/google/octopus: Fix GPIO config for DRAM_IDs
The GPIO pad configurations for GPIO68-71 are incorrectly configured as
outputs. This change corrects them to be inputs.

BUG=b:74932341
TEST=None

Change-Id: I319f8a64d83c29ed150316c15a8d429cc7c024f3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25217
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19 15:09:10 +00:00
amanda_hwang 04ccd5f9b5 mb/google/poppy: Config GPIO for DMIC by different sku id
BUG=b:74177699
BRANCH=poppy
TEST=Verify audio recorder function by different SKU ID

Change-Id: Ic6570703f6ab4a1b03cbba8370fc0f597ab6bcf2
Signed-off-by: amanda_hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19 15:08:41 +00:00
Shamile Khan c4276a3fdc soc/intel/apollolake: Add PCIe de-emphasis enable configuration.
PCIe de-emphasis is enabled by default. Thunderpeak Wi-Fi requires
it to be disabled. Therefore allow it to be configured via a
device tree setting.

TEST=On GLKRVP, verify Thunderpeak Wi-Fi card shows up in lspci when
de-emphasis is disabled in device tree.

Change-Id: Iae204768dfe00a638c764644c44c7cda269e73e0
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19 14:25:04 +00:00
Justin TerAvest cc6953bb34 mb/google/octopus: Configure PCH_WP_OD early.
The GPIO for EEPROM write-protect should be configured early, before
romstage. This change configures that pad earlier. This pad is the same
on the existing Octopus schematics.

BUG=None
TEST=None

Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19 14:24:04 +00:00
Shelley Chen f12bb7bcf2 mb/google/fizz: Enable VMX
We are enabling at the kernel level, but that is triggering an issue
where FSP expects it to be disabled so it forces a cold reboot on
every warm reboot, clearing the ramoops logs.  Enabling in BIOS so it
matches what the kernel expects.

This is the same change that were done for eve:
https://review.coreboot.org/#/c/22449/

BUG=None
BRANCH=None
TEST=echo PANIC >  /sys/kernel/debug/provoke-crash/DIRECT
     check for /dev/pstore/console-ramoops

Change-Id: Icd0bd01f5aee4c89f503eebba0808a1f3059e739
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19 14:23:03 +00:00
Richard Spiegel 6dfbb59307 soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uart
The GPIO programming of configure_stoneyridge_UART() can be done by the early
GPIO table, AOAC enabling was already removed. So  configure_stoneyridge_uart()
became redundant. Remove procedure  configure_stoneyridge_uart().

BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.

Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25192
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19 14:19:46 +00:00
Furquan Shaikh 6bff3bf4be mb/google/octopus: Do not configure GPIO_149 as GPO
GPIO_149 is used as ESPI clock feedback and configuring it as a GPO
results in EC communication failure. This change removes the
configuration of GPIO_149 as GPO in ramstage so that it remains
configured for ESPI (as it was when AP came out of reset).

BUG=b:75348718

Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-17 21:52:13 +00:00
Garrett Kirkendall 64294eb5e2 soc/amd/stoneyridge: Call sb_spibase() early
Call sb_spibase() early so that it will set up the SPI base address.
This is another step to moving AGESA calls out of the bootblock.

BUG=b:74427893
BRANCH=master
TEST=Build and boot Grunt.

Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-17 16:32:15 +00:00
Aaron Durbin fd228e979c soc/intel/apollolake: handle different memory profiles for apl and glk
glk has different memory profile values than apl. Therefore, a
translation is required to correctly set the proper profile value
depending on what SoC (and therefore FSP) is being used. Based on
SOC_INTEL_GLK Kconfig value use different profiles.

BUG=b:74932341

Change-Id: I6ea84d3339caf666aea5034ab8f0287bd1915e06
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25249
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-17 02:06:08 +00:00
Richard Spiegel a9f49366c0 soc/amd/stoneyridge: Create a HALT_THIS_AP callout
It was required for all cores use the same CAR teardown function
(exit_car.S and gcccar.inc). AGESA has already been modified to do the
AP to do the call out. Create assembly code to call chipset_teardown_car
and then enter an endless loop with halt instruction. Then create the
call out that will call this new assembly code.

BUG=b:70338633
AGESA COMMIT=3313d277
TEST=Created a debug version of AGESA that would print the returned
status of HALT_THIS_AP. Build code without the fix, see the return.
Build code with the fix, see that there's no return.

Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/24999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-16 19:01:46 +00:00
Richard Spiegel 013f1024c3 stoneyridge: Update AGESA binary and AGESA.h
AGESA.bin was updated in the binary repo, so update the submodule pointer.
Among other changes, this added a callback "AGESA_HALT_THIS_AP", which
requires updated header files.

BUG=b:70338633
TEST=build kahlee.

Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25183
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-16 19:01:30 +00:00
Richard Spiegel 0e0e93cce1 soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code
Devices that need to have their AOAC register enabled do have a delay before
they become available. Currently each device has their own wait loop. Create
a procedure that initializes all AOAC devices in a table and wait for all
AOAC to become alive, then call this new procedure before the call to
initialize the UART. Then change all procedures that initialize some AOAC by
moving the devices to the table and removing AOAC initialization code.

BUG=b:74416098
TEST=Build and boot kahlee checking that UART is sending debug messages out.

Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-16 15:24:44 +00:00
Furquan Shaikh 2cfc862a3e soc/intel/apollolake: Add config option for enabling hotplug
PcieRpHotPlug in apollolake UPD is default enabled. This change adds a
config option to enable hotplug only if explicitly requested by
mainboard. This changes the default behavior on all apollolake boards
to have hotplug disabled.

BUG=b:74633273
BRANCH=reef,coral

Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-16 04:43:11 +00:00
Furquan Shaikh 6d5e10c05d soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.

BUG=b:74633273
BRANCH=reef,coral

Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-16 04:43:01 +00:00
Duncan Laurie 211bb97c67 mb/google/eve: Update DPTF parameters
1) Set the critical temperature threshold to 100C to match changes
on other boards.  This is intended to reduce DPTF-initiated thermal
shutdowns before it has had a chance to react.

2) Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.

BUG=b:67459049
BRANCH=eve
TEST=manual performance/power testing on Eve hardware

Change-Id: Ib660dcb25422fea0aa692fac5ba65b49808965ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-16 04:18:51 +00:00
zaolin 1356d6288b security/tpm: Fix TPM software stack vulnerability
* Fix tlcl_read() for TPM 1.2
* https://github.com/nccgroup/TPMGenie

Change-Id: I1618b2cc579d189bccca7a781e2bed0976a8b471
Signed-off-by: zaolin <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/25184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-16 04:13:26 +00:00