Commit Graph

9755 Commits

Author SHA1 Message Date
Aaron Durbin d0f6165923 cbfstool: introduce struct parsed_elf and parse_elf()
In order to make the ELF parsing more flexible introduce
a parse_elf() function which takes a struct parsed_elf
parameter. In addition take a flags parameter which instructs
the ELF parser as to what data within the ELF file should be
parsed.

Change-Id: I3e30e84bf8043c3df96a6ab56cd077eef2632173
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5373
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14 21:50:42 +01:00
Aaron Durbin 19a11d6fe9 cbfstool: remove incorrect section size check
I was overzealous in checking the section size with respect
to the file size. That check makes no sense as the section only
deals with link sizes -- not on-disk sizes. Remove the check as
it doesn't make any sense.

Change-Id: I348e7847ae3a50badc22693439614f813462445a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5384
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 23:02:46 +01:00
Edward O'Callaghan ed2bcaa731 mainboard/jetway/nf81-t56n-lf: Fix HWM base addr.
The target board has a different base addr. for its hardware
monitor (fans, temp, etc) from the Fintek Super I/O datasheet.

Change-Id: Ifc025cb92d0fc4e8f813091d00a6c87deae05863
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5383
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13 20:25:44 +01:00
Edward O'Callaghan 236cf47513 mainboard/jetway/nf81-t56n-lf: Remove hard-coded IMC fan craft.
Fan controls in 0x400-0x4ff are not programmed here. Thus fan
control from amd/persimmon in the devicetree.cb does not apply
to this board.

Change-Id: I9156143476df0a7b44c7af90fa2107e8a8ba851e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5381
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13 20:25:22 +01:00
Aaron Durbin a31ff73e8d cbfstool: elfparsing: check segment and section regions
While parsing the section and program headers ensure the
locations of their contents are within the elf file proper.

Change-Id: I856f7de45f82ac15977abc06e51bedb51c58dde1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5372
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:31:49 +01:00
Aaron Durbin b1b5118c71 cbfstool: elfheaders: use proper parameters to calloc()
Though the result doesn't matter much, the callers of calloc()
should order the parameters correctly. i.e. the first paramter
is the number of elements in an array and the second is the
size of each element.

Change-Id: Ic7c2910d623d96f380feb4e5f6fa432376f49e9b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5371
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:28:57 +01:00
Aaron Durbin 54ef306377 cbfstool: add eflparsing.h
elfparsing.h serves as the header to working with the elf
parser. Additionally, only include what is needed by the other
files. Many had no reason to be including elf.h aside from fixing
compilation problems when including cbfs.h.

Change-Id: I9eb5f09f3122aa18beeca52d2e4dc2102d70fb9d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5370
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:28:44 +01:00
Aaron Durbin aa8784c2d1 cbfstool: move iself() to eflheaders.c
The only user of iself() was in elfheaders.c. Move it there,
and make it local to the compilation unit.

Change-Id: I0d919ce372f6e2fce75885fb4fcba20d985979b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5369
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:28:07 +01:00
Aaron Durbin a983cea5b9 cbfstool: elfheaders: use common checks and buffer helpers
The elfheaders code was manipulating struct buffers. Use
the introduced buffer helper functions. Additionally fix
up offset and size checks for the program headers and section
headers by using common code paths.

Change-Id: I279c77f77aaa1860a0be43fb111df890dd1d84d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5368
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:27:54 +01:00
Alexandru Gagniuc 0c54bfa0ee Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs"
This reverts commit b845636ce6.
This commit changed the board status script to describe all boards in
terms of x86 terminology, such as CPU->southbridge->northbridge.

This terminology does not apply to a number of SoCs, in which the
buses are not connected via successive bridges, and as such it is
misleading and misguided to describe ideas of southbridge and
northbridge for these devices.

Change-Id: I98ba24ee00b816bf20d507c6d313ec2946acaedf
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5177
Tested-by: build bot (Jenkins)
2014-03-12 16:37:41 +01:00
Chris Douglass b34739b4b0 drivers/spi: Add support for adesto SPI flash parts
Adds support for the following Adesto Technologies
SPI Flash parts.

AT25DF081
AT25DF321
AT25DF641

It has been tested on an Orion VPX7654 board populated
with an AT25DF321A part. The "08" and "64" densities have not
been tested.

These parts are the successors of the Atmel AT26DF line that
was spun out or purchased by Adesto.

In this patch, adesto.c is identical to winbond.c with part
entries for the Adesto parts. The datasheet for the AT25DF parts
includes a "100MHz" programming command in addition to the "85MHz"
command that is currently used but this patch does not add support
for that enhanced programming mode.

Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5225
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-12 01:03:31 +01:00
Aaron Durbin 06ece7de93 chromeos: provide option to dynamically allocate ram oops buffer
Fixing the location of the ram oops buffer can lead to certain
kernel and boot loaders being confused when there is a ram
reservation low in the address space. Alternatively provide
a mechanism to allocate the ram oops buffer in cbmem. As cbmem
is usually high in the address space it avoids low reservation
confusion.

The patch uncondtionally provides a GOOG9999 ACPI device with
a single memory resource describing the memory region used for
the ramoops region.

BUG=None
BRANCH=baytrail,haswell
TEST=Built and booted with and w/o dynamic ram oops. With
     the corresponding kernel change things behave correctly.

Change-Id: Ide2bb4434768c9f9b90e125adae4324cb1d2d073
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5257
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 21:37:36 +01:00
Duncan Laurie e7e78d61a9 baytrail: Reserve memory between ASEG and 1MB and for ramoops
Low system tables are in this region, and it is probably safer
to keep ASEG reserved.

Also keep the region used by ramoops from being used by the OS
and from being cleared by developer mode boots.

Lots more work needed to make the ACPI tables fully functional.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=boot on rambi and see that the kernel finds RSDP and uses ACPI

Change-Id: I4f7064d3cff14a3ecf15b194a1f20c1fa9d5e134
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4932
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-11 19:56:17 +01:00
Duncan Laurie 714b1e8b6c rambi: Enable USB boot with EHCI controller
This adds the EHCI driver back to libpayload and configures
the devicetree to route ports to EHCI.

This is hopefully just temporary until the issues with XHCI
can be worked out.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi

Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175513
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4931
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:55:58 +01:00
Duncan Laurie 3c9f17462a baytrail: Add EHCI initialization
This adds required steps to initialize the EHCI controller
on the baytrail platform.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi

Change-Id: I3a5487791e2305616036d4550e260a178c0e1c4d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175512
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4930
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:55:30 +01:00
Duncan Laurie f81a91a768 baytrail: Add XHCI initialization
This adds required steps to initialize the XHCI controller
on the baytrail platform.

Actually using XHCI is causing lots of bad behavior including
apparent memory corruption.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Ic43e04f4b47e107ec3bb0c387a9fc72c3cae0271
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175511
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4929
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:55:12 +01:00
Aaron Durbin 97651c55a3 baytrail: add audio clock workaround for LPE
Apparently the LPE device needs a 25MHz clock. Provide
the work around to enable this clock.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Confirmed setting being applied.

Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175493
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4928
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:54:58 +01:00
Aaron Durbin 65ad521f8a baytrail: add ccu iosf access functions
The clock control unit needs to be accessed to configure
some of the devices properly. Therefore. provide a way
to access the CCU.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built.

Change-Id: I30ed06e6aef81ee99c6d7ab3cbe8f83818b8dee5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175492
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4927
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:54:04 +01:00
Aaron Durbin 46ab8cdc68 baytrail: HDA function disable workaround
Parts of the audio path are common between the HDA and LPE.
However, those parts are power-controlled by the D-state of
the HDA device. Therefore, one cannot put the HDA into D3Hot
because those audio paths will be shutdown.

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Disabling HDA still
     causes a shutdown when performing warm reset, however I
     was able to verify the magic sequence was being performed.

Change-Id: I3b01356d85a4b7b902bd896b8eb9e7bc509fcc42
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175491
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4926
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:53:51 +01:00
Aaron Durbin 1eae3eed29 baytrail: allow function disable on TXE
Previously it was not known how to put the TXE pci device
into D3Hot. It's been disseminated that this is not a requirement
for disabling the TXE pci device in the function disable register.
Therefore, allow this by returning 0 from place_device_in_d3hot().

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Temporarily set TXE to be disabled. Noted FUNC_DIS was being
     set accordingly.

Change-Id: Ibf537bf8ba718859591dc89bdf41e57c1ea9d836
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175490
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4925
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:53:17 +01:00
Duncan Laurie 223d4a4ff6 baytrail: Switch graphics init to use reg_script
This is an example consumer of the register script handler.

BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=build and boot on rambi and see recovery screen

Change-Id: I4954a5defd0a345b179819b9f6bb15ea340a6715
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175214
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4924
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:52:06 +01:00
Aaron Durbin 6e8c2790bb cbfstool: add struct buffer helper routines
There are some open-coded manipulation of the struct buffer
innards in the elf parsing code. Add helper functions to avoid
reaching into the struct itself.

Change-Id: I0d5300afa1a3549f87f588f976184e880d071682
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5367
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:46:45 +01:00
Aaron Durbin 1240d29209 cbfstool: add bputs() to store a byte stream to a buffer
There was already a bgets() function which operates on a buffer to
copy a byte stream. Provide bputs() to store a byte stream to a
buffer, thus making the API symmetrical.

Change-Id: I6166f6b68eacb822da38c9da61a3e44f4c67136d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:43:17 +01:00
Aaron Durbin 01650045f4 cbfstool: add get8/put8 variants to xdr structures
In order to provide consistent usage provide the get8()
and put8() callbacks to xdr operations. That way no futzing
needs to be done to handle 8-bit reads and writes.

Change-Id: I1233d25df67134dc5c3bbd1a84206be77f0da417
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5365
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:42:50 +01:00
Aaron Durbin fae75172d1 cbfstool: move verbose to common.c
In order for multiple tools to use the common code found
in common.c place the verbose variable within common.c's
compilation unit.

Change-Id: I71660a5fd4d186ddee81b0da8b57ce2abddf178a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5364
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:42:30 +01:00
Aaron Durbin 4e6ad1bcaf rmodule: allow rmodule header structure to be used by userland
In order for userland to create rmodules the common code should be
shareable.  Therefore, convert the short u<width> name types to the
posix uint<width>_t types. Additionally, move the definition of the
header structure to a new rmodule-defs.h header file so that userland
can include that without pulling in the coreboot state.

Change-Id: I54acd3bfd8c207b9efd50a3b6d89efd5fcbfc1d9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5363
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:42:15 +01:00
WANG Siyuan 62a3f6f665 AMD Olive Hill: add IMC fan control
There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Olive Hill.

Change-Id: I1748e8c92fb72a82bac0506ecdf98304a5bd8239
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4301
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-10 18:07:53 +01:00
WANG Siyuan d5813530fa AMD Parmer: add IMC fan control
There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Parmer.

Change-Id: Id11d5c5da30346c034d155a73749e7f4c9c980eb
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4302
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-10 18:06:09 +01:00
Kyösti Mälkki 7841ece730 CBMEM console: Fix build for ARM
This preprocessor guard was used to disable CBMEM console from
romstage of ROMCC boards. It unintentionally disabled it for ARM
too as they do not have CACHE_AS_RAM selected.

Option EARLY_CBMEM_INIT implies CAR migration which is required
to have CBMEM console in romstage. This change should have been
done in commit f8bf5a10 already, but we missed it.

Change-Id: I03e95183be0e78bc7dd439d5fef5b10e54966dc3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5356
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-10 15:30:44 +01:00
Vladimir Serbinenko afc62a7631 intel/gma: Remove MCH register declarations.
i915_reg.h re-declares some of MCH registers as seen through MCHBAR mirror.
It's not currently used and we don't want any MCH registers in GFX.

Change-Id: I5fa4711fee60d64316696b7ed713013de8759b54
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5318
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09 21:22:15 +01:00
Vladimir Serbinenko 47089f29f0 smbios: Supply tag type 2 (base board information)
Information really contained in it is mostly the same as in type 1 tag.
However Linux uses type 2 to match hardware. Duplicate the info.

Change-Id: I75e13d764464053ecab4a833fbb83836cedf26e6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5322
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09 21:21:46 +01:00
Vladimir Serbinenko 7d48f04bb4 lbtdump: Dump forwarded tables.
Recent coreboot puts real tables in high memory and only pointer
is remaining at traditional location.

This patch makes lbtdump work with recent coreboot.

Change-Id: I1c4945909da16c0ec81e59c2d94d9a7d27e2aba5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4830
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09 21:19:29 +01:00
Edward O'Callaghan b66d53ac10 mainboard/jetway/nf81-t56n-lf: Turn PS/2 driver on by default.
This board has a working PS/2 port for a keyboard. Thus, it
makes for a good option to have on by default.

Change-Id: Ifcde0474d7be26152f1b5e19fe4906e87732b9a4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5357
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09 16:20:09 +01:00
Edward O'Callaghan bfa29dc021 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
The platform dependent mainboard.c was incorrectly disabling the
second clock signal feeding the GPP ports. This results in
spurious hangs by calling the set_pcie_dereset() SB CIMx callback
many times. This also stops coreboot from finding the second NIC
behind the pci 15.0 bridge.

Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5355
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-03-09 13:38:49 +01:00
Kyösti Mälkki 8340666cb1 intel/jarrell: Apply ROMCC workaround
Taken from intel/xe7501devkit, maybe it had same symptoms once.

The call to ich5_watchdog_on() has side-effect of exploding the
requirements for ROMCC internal arrays at compile-time. The hard-coded
limit in question is MAX_RHS in util/romcc.c, the default of 127 comes
from the rhs field defined with 7 bits.

Before this patch intel/jarrell builds were using upto MAX_RHS=102, while
other ROMCC boards built even with MAX_RHS=10. This workaround brings
intel/jarrell to the same level.

Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5348
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-09 13:09:48 +01:00
Kyösti Mälkki 233f5b3b0e ROMCC: Trigger internal compiler failure and apply the workaround
These boards first failed when attempting to change print_err() from
direct function call to console_tx_XX() to a code block in the form of

 do { if (y) console_tx_XX(x); } while(0)

Removing the label dummy_romcc_workaround_label added here will
trigger the following compiler error for the two boards:

  Internal compiler error: no edge to block->last->next

Change-Id: I997adfaf586d7fa2096401dd574b07ce676d0ac6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5349
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-08 19:24:22 +01:00
Edward O'Callaghan 2cf9715c9a utils/romcc.c: Fix spurious unsigned integer comparisons.
Clang warns about comparisons of unsigned integers with being below
zero. Remove spurious logic checks that are always false.

Change-Id: I70c4d5331df81e48bf7ef27ff98400c4218f7edc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5275
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-08 15:48:13 +01:00
Patrick Georgi 946923b0fb qemu-i440fx: add a prototype for main()
This probably belongs elsewhere, but I haven't found a nice place yet.

Change-Id: I9ca52db33905cf4ee229d7ff44012105915271a8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4720
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-08 15:05:53 +01:00
Paul Menzel 1386d5ccb0 lib/dynamic_cbmem.c: Include `cbmem_console.h`
Broken with commit 1d7541fe (console: Fix includes).

Change-Id: If41f9e08df98d79b7bbf740b1a5634d0140207be
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5351
Tested-by: build bot (Jenkins)
2014-03-08 13:06:34 +01:00
Aaron Durbin c34713d33e x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option
Boot speeds can be sped up by mirroring the payload into
main memory before doing the actual loading. Systems that
would benefit from this are typically Intel ones whose SPI
are memory mapped. Without the SPI being cached all accesses
to the payload in SPI while being loaded result in uncacheable
accesses. Instead take advantage of the on-board SPI controller
which has an internal cache and prefetcher by copying 64-byte
cachelines using 32-bit word copies.

Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5305
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-07 15:30:27 +01:00
Duncan Laurie 7274800ea3 Add a generic register script handler
This is based on the RCBA configuration setup from haswell.
It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF.
I did not extend it to handle MSR yet but that would be another
potential register type.

There are a number of approaches to this kind of thing, but in the
end they have a lot of switch statements and a mass of #defines.
I'm not particularly set on any of the details so comments welcome.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=emerge-rambi chromeos-coreboot-rambi

Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175206
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4923
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04 16:31:14 +01:00
Kyösti Mälkki 0567c91b22 console: Use single driver entry for UARTs
UARTs now have unified prototypes and can use a single entry
in the list of drivers for ramstage.

Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5308
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:40:34 +01:00
Kyösti Mälkki ab94bbf072 usbdebug: Move Kconfig under drivers/usb
This menu may become a bit more complicated with addition of
new USB hardware so move it out of console/.

Change-Id: Ieb330675b9227a3e53d093f7c2b5a65e3842dc82
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5307
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04 15:38:12 +01:00
Kyösti Mälkki 9c479c9a3e SMM: Only have console with DEBUG_SMI
Existing code compiled serial communication and printk() for SMM
even when DEBUG_SMI was not selected.

Change-Id: Ic5e25cd7453cb2243f7ac592b093fba752a299f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5142
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-03-04 15:36:27 +01:00
Kyösti Mälkki bea6bf07df uart8250: Move under drivers/uart
Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5236
Tested-by: build bot (Jenkins)
2014-03-04 15:34:27 +01:00
Kyösti Mälkki 2b95da01e6 uart8250mem: Unify calls with generic UART
NOTE: UART base for SMM continues to be broken, as it does not use
the address resource allocator has assigned.

Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:28:41 +01:00
Kyösti Mälkki 4770749edc uart8250io: Unify calls with generic UART
Change-Id: I6d56648e56f2177e1d5332497321e718df18300c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5234
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:27:53 +01:00
Kyösti Mälkki 1d7541feeb console: Fix includes
Do not pull in console hw-specific prototypes everywhere
with console.h as those are not needed for higher levels.

Move prototypes for UARTs next to other consoles.

Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5232
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:26:08 +01:00
Kyösti Mälkki 7e75f20477 pl011 UART: Move under drivers/uart
Currently this is only a minimal stub to get console on qemu-armv7.

Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5162
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:25:15 +01:00
Kyösti Mälkki 2cbcd2b710 ti/am335x: Fix baudrate calculation
UART input clock is platform dependent. Also account for possible
use of get_option() where baudrate is not compile-time constant.

The hardware reference on BeagleBone is from a 48 MHz oscillator input.
With pre-divisor of 16 we get same register values as in table 19-25.

Change-Id: I89aee27c958f8618ce79a968ae7520a867e7e8a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5290
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:24:50 +01:00