Commit Graph

36291 Commits

Author SHA1 Message Date
Frank Wu 9c7c09fbfa mb/google/volteer/halvor: Enable card reader function on Halvor
Configure gpio settings for enabling card reader function.

BUG=b:153680359
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Verify that the sd card is mount on /dev/mmcblk0 successfully.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I51752f47bc8d31d3a11da728ce00ca754381fde9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44169
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13 11:14:25 +00:00
Qii Wang 160b3d7e9d soc/mediatek/mt8192: Add spi driver
Add driver for MT8192 SPI controller

TEST=Boots correctly on MT8192EVB

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Change-Id: I2094dd2f14ad19b7dbd66a8e694cc71d654a2b4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-13 10:12:32 +00:00
Angel Pons 053fe8a3b2 sb/intel/bd82x6x/me_8.x.c: Relocate `mkhi_end_of_post`
This reduces the differences between both ME source code files.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: I08e07ca2691bb854682692476153a98967bf05da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-13 06:59:29 +00:00
Sridhar Siricilla b2353a7bdc soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitions
Add Kconfig option for CSE me_rw blob path and stitch the me_rw blob
into FW_MAIN_X partitions.

BUG=b:145796136

Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35406
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13 05:44:24 +00:00
Sridhar Siricilla 77025b3f56 security/vboot/Makefile.inc: Update regions-for-file function
This patch updates regions-for-file function in the
security/vboot/Makefile.inc to support adding a CBFS file into
required FMAP REGIONs in a flexible manner. The file that needs to be
added to specific REGIONs, those regions list should be specified in the
regions-for-file-{CBFS_FILE_TO_BE_ADDED} variable.

For example, if a file foo.bin needs to be added in FW_MAIN_B and COREBOOT,
then below code needs to be added in a Makefile.inc.
	regions-for-file-foo := FW_MAIN_B,COREBOOT
	cbfs-file-y := foo
	foo-file := foo.bin
	foo-type := raw

TEST=Verified on hatch

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I1f5c22b3d9558ee3c5daa2781a115964f8d2d83b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-13 05:43:53 +00:00
CK Hu 02bab4ddcf mb/google/asurada: Add new MT8192 mainboard "Asurada"
The placeholder functions and build rules for generating a minimal
firmware to run on MT8192 SOC based mainboard "Asurada".

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13 05:34:50 +00:00
CK Hu 958ab46dda soc/mediatek/mt8192: Add DRAM resource in ramstage
Add DRAM resource in ramstage to load payload.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-13 05:34:18 +00:00
CK Hu 5559a449d4 soc/mediatek/mt8192: Initialize build rules
The first Makefile to support building minimal stage files for MT8192 SOC.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I2cf68805532f70f072b4e9a21ee61e2ebe4ebd9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43962
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13 05:33:57 +00:00
CK Hu ad700565ef soc/mediatek/mt8192: Add a placeholder for the EMI driver
Add minimal function to report SDRAM size.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: If74b6b52dd6e91d1ff40cf8460b6a03b2f3bb6f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43961
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13 05:33:45 +00:00
Furquan Shaikh a396c0a7ee mb/google/zork: Update PICASSO_FW_*_POSITION to match new layout
CB:44362 ("mb/google/zork: Reorganize chromeos.fmd to increase WP_RO
to 8MiB") updated the flash layout which moved RW_SECTION_A and
RW_SECTION_B to different addresses than before. PICASSO_FW_A_POSITION
and PICASSO_FW_B_POSITION configs need to be updated accordingly to
retain the same behavior as before i.e. amdfw_a/b are placed at the
start of FW_MAIN_A/B by placing them right after the CBFS header.

This change fixes the value of PICASSO_FW_A_POSITION and
PICASSO_FW_B_POSITION to maintain amdfw at the start of RW-A/B CBFS.

BUG=b:161949925

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I177fb38af6380c36397d2a72d5ec00965087d528
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44425
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13 04:02:28 +00:00
Furquan Shaikh fd8840880d mb/google/zork: Disable ACP I2S wake for schematic version 3.6+
Starting with v3.6 of reference schematics, headphone jack interrupt
is moved to a standard GPIO instead of using CODEC_GPI. Thus, we no
longer need I2S wake to be enabled in the ACP for boards using v3.6+
version of schematics.

This change sets `acp_i2s_wake_enable` and `acp_pme_enable` to default
0 in baseboard devicetrees and overrides to 1 in update_hp_int_odl()
if the board is still using older version of reference schematics.

BUG=b:159934887

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I44b40db95b5148fe483c7340c5bd0d58627970a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44403
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13 03:29:10 +00:00
Subrata Banik ef04f4e3d3 drivers/intel/fsp2_0: Fill EFI_CPU_PHYSICAL_LOCATION structure information
Latest EDK2 code inside
"UefiCpuPkg\Library\RegisterCpuFeaturesLib\CpuFeaturesInitialize.c"
is now looking for EFI_CPU_PHYSICAL_LOCATION structure variables hence
coreboot need to fill required information (package, core and thread
count).

TEST=Able to see package, core and thread information as part of FSP
debug log.

Change-Id: Ieccf20a116d59aaafbbec3fe0adad9a48931cb59
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-08-13 02:39:51 +00:00
Srinidhi N Kaushik e0836b0fcb vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3313
Update FSP headers for Tiger Lake platform generated based FSP
version 3313. Previous version was 3274.
Changes Include:
1. Update comments
2. Fix comment typos
3. UPD offset updates

BUG=b:163582213
BRANCH=none
TEST=build and boot volteer proto2

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I2784c5b7c8f71c1355c1c36a27cc88080c7c2647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-08-13 02:16:56 +00:00
John Zhao 90883287b5 mb/intel/tglrvp: Add interrupt _CRS under CREC scope
Interrupt _CRS is missing under CREC scope. TGLRVP U/Y has GPP_A15
assigned to MECC_HPD2 as EC_SYNC_IRQ. Configure this GPP_A15 GPIO as
active low and level interruptible for EC sync interrupt configuration.

BUG=None
TEST=Booted to kernel and verified EC_SYNC_IRQ in the scope of CREC
current resource settings.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44103
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12 19:43:07 +00:00
Frank Wu 1d7ba15aa2 mb/google/volteer/halvor: Update settings for WiFi/BT functions
Configure gpio/overridetree settings for WiFi/BT functions.
Then WiFi/BT functions are enabled on Halvor.

BUG=b:153680359, b:163004808
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Verify that WiFi/BT can scan devices successfully.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I085b192bb768c2c1238f3f857d315502ac10857e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44372
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12 19:42:48 +00:00
Aaron Durbin e915cfc0d8 mb/google/zork: expose stop gpio for trembyle
In CB:43701 the trembyle touchscreen parameters were not updated
to expose the stop gpio properly.

BUG=b:162973325

Change-Id: I6f5da1c556ba1c6ccabf699491d3b635aa79f7c0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-12 17:56:23 +00:00
Sridhar Siricilla a91c919611 soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddress
The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between
coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address
for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR
address is overridden with 0xfed1a000. This causes HECI transactions to
fail between FSP-M call and postcar.

BRANCH=puff
TEST=Verified sending HECI commands before and after FSP-M call on hatch.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-12 17:39:49 +00:00
Sumeet R Pawnikar 4dfdce4223 mb/google/dedede/variants/drawcia: add DTT support
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia
system. Add information on sensors, power limits and tcc_offset for DTT
based thermal control.

BRANCH=None
BUG=b:161993459
TEST=Built for dedede system

Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-12 16:36:06 +00:00
Felix Held 1ba3833ba3 soc/amd/common/espi_util: rename espi_check_status
espi_poll_status describes better what the function actually does, since
it polls the status register instead of just doing a single read to
check.

Change-Id: I0feeef5504bd911e1fb0a00d4f4c546df3548db2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-12 14:20:58 +00:00
Angel Pons d703c5b1b3 sb/intel/bd82x6x: Make `pch_silicon_supported` static
It's not needed anywhere else.

Change-Id: Ibc02e432bbc669b3fcfcb8add3c7b0c2a9f77d77
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44339
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12 11:02:34 +00:00
Angel Pons 2178b7286b sb/intel/lynxpoint: Move IOBP API to its own compilation unit
Change-Id: Icb6114302cebe19bc3c1971929ea4fc085b454be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41946
Reviewed-by: Michael Niewöhner
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12 11:02:16 +00:00
Angel Pons 19c5cd210d nb/intel/sandybridge: Add comments to `struct iosav_ssq`
Add the ranges of bitfields as comments on the struct.

Change-Id: Ib20a233806bfbdc9a81a77f4ef10f67a3cd2dc0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
2020-08-12 11:01:44 +00:00
Angel Pons c27571dbc0 sb/intel/i82801jx/sata.c: Simplify constant is_mobile parameter
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.

Change-Id: I30cdca0240afced2949639193caa2f11aca1c60d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
2020-08-12 11:00:26 +00:00
Angel Pons d1ccecf6ea sb/intel/i82801jx/sata.c: Drop always-false is_mobile check
Also remove the meaningless `sata_traffic_monitor` devicetree option.
Function parameters will be removed in a reproducible follow-up.

Change-Id: I70cf1e06cc8ace504a22be9f9c4441e3070f9e29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12 10:59:21 +00:00
Angel Pons 851fe8334e sb/intel/i82801jx: Drop is-mobile checks
There's no mobile ICH10 variant. This was copied from i82801ix.

Change-Id: I141da407e336f6fbbf84d0e2cee55b0c12931c7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
2020-08-12 10:56:24 +00:00
Angel Pons bcc2c729dd sb/intel/i82801ix/lpc.c: Align with i82801jx
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I9445fac7db0a96b6a28ccf307f5ccedc1f94b8ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12 10:56:13 +00:00
Angel Pons 28d10a2384 sb/intel/i82801ix: Use macros for LPC_EN
Taken directly from i82801jx code.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I0a5dc274e0058144e6e7f734c848b6b5962cba85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12 10:56:02 +00:00
Angel Pons 05a8c0aa69 sb/intel/i82801jx/early_init.c: Drop double blank line
Change-Id: Ia37c5feb5a61793c10496a2d9cabb7661aa758b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
2020-08-12 10:55:49 +00:00
Angel Pons c5b22c8097 sb/intel/i82801ix/early_init.c: Drop unnecessary initial value
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I17903dfe7b18a9244d0c102768dd153941f125a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
2020-08-12 10:55:43 +00:00
Angel Pons d5fde1c922 sb/intel/i82801ix/i82801ix.c: Align with i82801jx
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: Icbb6cb45155991f9d4b3bcff37e1e9d99483acdc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12 10:54:46 +00:00
Angel Pons ab6ecb4d08 sb/intel/bd82x6x: Remove incorrect RCBA registers
These were probably copy-pasted from some ICHx southbridge, and then
some were corrected because native PCH init uses them. Delete the
definitions which are unused and are invalid for this southbridge.

Change-Id: I0be72f76c7fcc63316ae8566891e0732456a8c55
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12 10:54:30 +00:00
Angel Pons bfb3b460ed sb/intel/lynxpoint: Remove incorrect RCBA registers
These were probably copy-pasted from some ICHx southbridge. However,
datasheet shows that some of these are located elsewhere, and some
others have disappeared completely. As they aren't in use, drop them.

Change-Id: I2d09547bdbfd5f8f72ce3541347d9fec28630c79
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
2020-08-12 10:54:18 +00:00
Angel Pons 0b3512b495 sb/intel: Remove inexistent references to IDE controller
This device doesn't exist on these southbridges.

Change-Id: Ie17427ba044c465adf95300ff7f5610c25ae3373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12 10:54:06 +00:00
Julia Tsai 1d68d6d14d volteer: Create lindar variant
Create the lindar variant of the volteer reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.2).

BUG=b:161089195
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_LINDAR

Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com>
Change-Id: I08923cde932b7304bcb01cd747530c87949e4692
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-12 06:40:54 +00:00
Subrata Banik 41934bfe94 soc/intel/common/block/sata: Add common SATA driver
Enable PCI_COMMAND_MASTER for SATA controller to ensure device can
behave as a bus master. Otherwise, the device can not generate PCI
accesses.

BUG=b:154900210
TEST=Able to build and boot CML and TGL platform.

Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44299
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12 06:00:35 +00:00
Christian Walter 2276ffa380 mb/prodrive/hermes: Add multifunction device for UART 2
On CNP-H, only four I2C controllers are available, so PCI devices 19.0
and 19.1 are missing. However, PCI device 19.2 still exists as UART 2.

That function 0 is missing means UART 2 can only be used in ACPI mode.
Both devices need to be marked as hidden on the devicetree so that the
allocator takes UART 2 into account.

Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-12 05:36:18 +00:00
Patrick Rudolph 3299b2ded5 soc/intel/tigerlake: Add IRQs for LPSS uart
Values are taken from pci_irqs.asl.
The common code will make use of those defines to generate ACPI
SSDT code for LPSS uarts operating in "ACPI mode".

Change-Id: I5ef93493965834cda30d70918e65de3129e547b7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44260
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12 05:30:28 +00:00
Furquan Shaikh 988da3142d mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB
This change reorganizes flash map layout for zork to allow WP_RO to
grow to 8MiB. This is to allow more space for the firmware UI screens
in RO. Following changes are made in the layout:

1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for
MRC cache. Next section can start on 64K boundary immediately after
MRC cache.
2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB
each. Each region is currently at ~2MiB of usage.
3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size
supported by coreboot.
4. SMMSTORE is restricted to 4K.
5. RW_LEGACY region is dropped down to ~1.9MiB.

BUG=b:161949925
TEST=Verified that write-protection for RO still works fine, device
boots in recovery and non-recovery mode. Also, verified that the dump
of fmap looks correct:
dump_fmap -h firmware/image-trembyle.serial.bin
name                     start       end         size
WP_RO                      00800000    01000000    00800000
  RO_SECTION                 00804000    01000000    007fc000
    COREBOOT                   00875000    01000000    0078b000
    GBB                        00805000    00875000    00070000
    RO_FRID                    00804800    00804840    00000040
    FMAP                       00804000    00804800    00000800
  RO_VPD                     00800000    00804000    00004000
RW_LEGACY                  0061d000    00800000    001e3000
SMMSTORE                   0061c000    0061d000    00001000
RW_NVRAM                   00617000    0061c000    00005000
RW_VPD                     00615000    00617000    00002000
RW_SHARED                  00611000    00615000    00004000
  VBLOCK_DEV                 00613000    00615000    00002000
  SHARED_DATA                00611000    00613000    00002000
RW_ELOG                    00610000    00611000    00001000
RW_SECTION_B               00310000    00610000    00300000
  RW_FWID_B                  0060ff00    00610000    00000100
  FW_MAIN_B                  00312000    0060ff00    002fdf00
  VBLOCK_B                   00310000    00312000    00002000
RW_SECTION_A               00010000    00310000    00300000
  RW_FWID_A                  0030ff00    00310000    00000100
  FW_MAIN_A                  00012000    0030ff00    002fdf00
  VBLOCK_A                   00010000    00012000    00002000
RW_MRC_CACHE               00000000    00010000    00010000
SI_BIOS                    00000000    01000000    01000000

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2020-08-12 04:32:07 +00:00
Hung-Te Lin 45701fd96e mb/google/kukui: revise per-device memory mapping table
In order to help identifying right DRAM info (especially in user space),
we want to unify the mapping table and do the device-specific mapping by
a virtual offset based on build config.

BUG=b:161768221,b:159301679
BRANCH=kukui
TEST=emerge-jacuzzi coreboot

Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-12 02:54:28 +00:00
Weiyi Lu a4cad368a2 soc/mediatek/mt8192: Add PLL and clock init support
Add PLL and clock init code.

TEST=Boots correctly on MT8192EVB.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-12 02:51:39 +00:00
CK Hu 8fcc246a56 soc/mediatek/mt8192: Add gpio driver
Add MT8192 GPIO driver.

Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Change-Id: I4b230aebc9eb4ca1bbf444c3a2f30159d707f37b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43959
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12 02:51:28 +00:00
Huayang Duan 6e57b1cf6d soc/mediatek/mt8183: Transfer ddr geometry type to dram blob
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: I3a677195f5036321939c60c8f9f1bace7c4a2e3f
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-12 02:50:59 +00:00
Kangheui Won 7fe005ff30 amd/picasso/acpi: Add power resources for UART0
Follow-up for a31a769 -
"amd/picasso/acpi: Add power resources for I2C and UART".
Now PSP properly handles UART0 D3, we can shutdown UART0.

BUG=b:158772504
TEST=suspend_stress_test for 50 cycles,
* echo 1 > /sys/module/acpi/parameters/aml_debug_output
* dmesg | grep FUR to check on&off for FUR0
[ 2413.647500] ACPI Debug:  "AOAC.FUR0._OFF"
[ 2413.736265] ACPI Debug:  "AOAC.FUR0._ON"

Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11 23:16:42 +00:00
Angel Pons 108570654e cpu/intel: Remove Core 2 Duo E8200 CPUID from model_6fx
With a CPUID of 10676, it is clearly model_1067x... Wait, it's already
there, but the comment is wrong. This ID isn't for Core Duo CPUs.

Change-Id: Ia4b73537805e2a8fa9e28bde76aa20a524f8f873
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-11 21:43:47 +00:00
Jes Klinke 739c503404 soc/intel/common/block/gspi: Recalculate BAR after resource allocation
The base address of the memory mapped I/O registers should not
be cached across resource allocation.  This CL will evict the cached
value upon exiting the BS_DEV_RESOURCES stage.

Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11 20:54:34 +00:00
Jonathan Zhang 89ed790028 vendorcode/intel/fsp/fsp2_0/CPX-SP: remove non-existing PSTACKs
CPX-SP has a CSTACK and 3 PSTACKs. Clean up the HOB header
file to remove reference to non-existing PSTACKs.

Adjust mainboard code accordingly.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ic52b01cd89fb5b3fce64686d91f017f405566acd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-11 20:15:30 +00:00
Johnny Lin ec886ec6fa xeon_sp/cpx: Enable PCH thermal device via FSP
Tested=On OCP Delta Lake, OpenBMC sensor-util can see PCH Temp readings.

Change-Id: I39d0d0a982476f9fece51cfa19dcbd0da5dea690
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44075
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11 20:15:10 +00:00
Jason Glenesk f2a59a4de2 soc/amd/picasso: Correct processor ACPI scope
Change namespace from _PR to _SB.

Cq-Depend: chrome-internal:3208104
BUG=b:153242529
TEST=Boot a trembyle with change applied and dump SSDTs to ensure
processors are in _SB scope.

Change-Id: I534f02dc50756759da945cf64d5b3623b0ec9db1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44325
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11 20:00:29 +00:00
Felix Held 316d59c1aa soc/amd/common/espi_util: espi_send_command: improve error message
It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set
in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the
command failed, so we expect that one to be set.

Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11 19:10:54 +00:00
Felix Held c0d4eeb387 soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug
When address and data register for the SIO control register access is
passed as one I/O region with a size of 2, the corresponding special
decode enable register should be used instead of a generic one to save
the rather limited generic ones for other decode ranges.

Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11 19:10:08 +00:00