This enables runtime power management for the UART controllers.
BUG=b:183983959
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e57d6312feda459cec65f330c6d2072774d4eb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Apart from the bool type, uint8_t, uint32_t and uint64_t are used in
this file, so include types.h instead of stdbool.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I30088d68132058f40b974fbaa822f322b58ed6c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
When using a debug build of the FSP, the FSP-M binary is larger than the
memory region we have allocated for it, so increase the size to make the
binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so
that it starts right after the the FSP-M memory region.
TEST=coreboot builds now successfully when using a debug version of the
FSP
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
We use cpuid_eax to get the cpuid family.
BUG=b:179699789
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib73e66241bb0cfd99a035c217c527338aa2d0e4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This reverts commit b90e6fdd25. Latest
releases of PSP does not load PSP verstage on S0i3 resume. Hence no need
to skip PSP verstage on S0i3 resume.
BUG=b:196400450
TEST=Build and boot to OS in Guybrush. Trigger a suspend/resume cycle
and then a reboot and ensure that the system boots to OS.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Iaeb92edb69662e6c06f4d0e3d7b760d4597bf650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the pin definitions for the remote GPIOs and the GPIO pin mux values
for the GPIO mode of those pins. For now, accessing the remote GPIOs is
only supported from the native coreboot code running on the x86 cores
and not from verstage on PSP or ACPI.
BUG=b:194524995
TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and
then toggling that GPIO in an infinite loop in the mainboard's bootblock
code results in GPIO 262 toggling as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Right now the ACPI code doesn't support accessing the remote GPIO block
yet, so don't generate invalid remote GPIO access functions and warn
about those being unsupported.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id364a59c9650bf4e3633b494b01ab23c0bbc50b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Some AMD SoCs have a 5th GPIO bank, the remote GPIO bank, which isn't
located right after the 4th GPIO bank, but instead at a different
location inside the APCIMMIO region. A difference to the first 4 GPIO
banks is that the corresponding GPIO MUX registers aren't in a separate
bank, but at the end of the remote GPIO region. So this remote GPIO
region only supports 48 GPIOs with a 32 bit configuration register each
and has the 8 bit GPIO MUX registers beginning at offset 0xc0 in the
remote GPIO region.
For now using the remote GPIOs from verstage on PSP isn't supported. To
support this, it would need to map acpimmio_remote_gpio and update the
pointer like it already does for acpimmio_gpio0, acpimmio_iomux and a
few others.
BUG=b:194524995
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8d7ff677a99381a5558782b80b0c4cae67602db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Currently coreboot for the AMD SOCs only supports accessing the up to 4
main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne
have another GPIO bank in the ACPIMMIO region that can contain up to 48
GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The
first 48 DWORDs of that ACPIMMIO bank are the 32 bit wide GPIO registers
and beginning at offset 0xc0 it has the corresponding 8 bit wide GPIO
MUX registers.
BUG=b:194524995
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins
array that is used for the sb_reset_i2c_peripherals call to bring the
I2C buses into a defined state.
TEST=Timeless build results in identical image for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Setting the usb_phy version and length in the soc code instead of devicetree.
That way the devicetree code does not have to reapeat it for different
AMD Cezanne based systems.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc`
is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig
option is enabled.
Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and
drop the now-redundant inclusions from platform code. Also, deduplicate
the `UDELAY_TSC` guards.
Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since both functions are only called from one function each, inline them
into those functions. Also get_gpio_mux just returned the return value
of iomux_read8, so there were two functions with identical functionality
which shouldn't be the case.
Suggested-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5662d0226edb25a9954fa47b42e208729a79e5a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56830
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This aligns the GPIO MUX access more with the GPIO control register
access and will facilitate adding support for the remote GPIO bank. Also
change the GPIO number argument type to gpio_t.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4054656c5cc23ea942e8dd370fbbffca304755d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC
chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers
while only allowing GPIO accesses through the GPIO API on the SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Move those two functions near the top of the file to have all functions
that do the hardware accesses in one place.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If787e6e1d124a932beafd73e5ce7d0ce4869e800
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use unsigned integers for variables that aren't supposed to become
negative.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ee037221b9818b0474fe0376323e522c1b3b516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since the raw GPIO MMIO register access is now only used inside the
gpio_banks block, the gpio_read32 and gpio_write32 functions can be
moved to that block to reduce the visibility and enforce the usage of
the functions provided by the gpio_banks block.
The iomux_read8 and iomux_write8 functions can't be easily moved to the
gpio_banks block, since it's also used in the pre-SOC AMD chipsets that
use the ACPIMMIO access functions directly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia0d6dea72c6bebbbe6ce545bedfc74f91e0042c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
The I2C code should use some GPIO API to access the GPIO registers
instead of accessing the GPIO MMIO regions itself.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84dff381ad86e0c7f879f0f079186aec9cafc604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
No need to do raw GPIO MMIO accesses when basically the same
functionality can be achieved by using existing APIs. Using the existing
GPIO API instead of raw GPIO MMIO register accesses allows containing
all direct GPIO MMIO accesses inside the common AMD GPIO code which will
be done in subsequent patches. Since the value parameter of gpio_set is
int, change the type of the val parameter of drive_scl to int as well
even though I'm not sure why a signed integer was used for this in the
common GPIO API. Since program_gpios already configures the SCL GPIOs as
outputs, gpio_set can be used in drive_scl which only sets the output
value, but doesn't configure the direction.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks similar to the same as before during the reset_i2c_peripherals
call, but due to the additional overhead of the read-modify-write to the
GPIO register instead of just a write, the pulse width gets about 50%
longer. Since the udelay call in drive_scl still has an open TODO to
make this configurable and the pulses being longer is in the safe side,
this side-effect can be addressed in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic323cebc1c83ecd6f0e1fbab419c69489d77face
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO
configuration register and drives it as output, so don't initially
configure the GPIO as input with no pull up/down. This is a preparation
to use the common AMD GPIO access functions instead of the raw register
accesses, since the gpio_set function only sets the output value, but
doesn't reconfigure the direction. Using gpio_output there instead would
reconfigure the direction as well, but would result in doubling the
number of MMIO accesses, so just configure the GPIOs correctly right
away to avoid that.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks exactly the same as before during the reset_i2c_peripherals call.
This was probed at the SCL pad of the unpopulated I2C level shifter on
the side that is connected to the SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56807
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the FSP binaries for Picasso are present in the amd_blobs repo,
select the ADD_FSP_BINARIES option if the Kconfig option to check out
that repo is set.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9a8571730cf271ad5e113e5df87700882b3c5475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
southbridge/amd/pi/hudson uses the common GPIO bank access code from
soc/amd, but doesn't provide all functionality that would be needed to
use the full functionality. Add a Kconfig option that switches off some
functionality in the common SoC GPIO access code, so that more of the
functionality proviced by the common SoC GPIO code can be used in the
AMD binaryPI chipset and board code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On mainboards with Cezanne SOC, serial enabled FSP_M binary size is
greater than the size allocated in DRAM. Increase the allocated size for
FSP_M binary in DRAM to handle both debug and release FSP_M binaries.
Also adjust the verstage load address accordingly.
BUG=None
TEST=Build and boot to OS in guybrush with both debug and release FSP_M.
Perform warm, cold reboot and suspend/resume cycling for 10 iterations.
Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In CB:56884 we discussed changing the default fast_read speed from
66MHz, which some platforms may not be capable of running, to 33MHz,
which should be generally suitable for all platforms. This same
change has been applied to the default for all SPI speeds.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibf926df6829ffdcbae947aaa245356f219615ce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57148
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit de7262f82c (soc/amd: remove special
GPIO_2 override soc_gpio_hook) removed the workaround that needed those
definitions, so remove the now unused GPIO_2_EVENT definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3f3e3061eade0e0cd25e2263451ccf6cefdc4ea4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56812
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make sure that the 48MHz clock output that is typically used as a clock
source for an I2S audio codec or a Super I/O chip.
TEST=On Guybrush before and after this patch the final state of
MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds code to print the current SPI speeds for each of the 4
different speeds, Normal, Fast-read, Alt-mode, & TPM. It also displays
the SPI mode and whether or not SPI100 mode is enabled.
BUG=b:194919326
TEST: Display the speed, change speeds, show that new speeds are the
expected values.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add the fch_spi_early_init call in fch_pre_init to perform early SPI
initialization which enables SPI ROM and setting the speed & read modes.
BUG=b:194919326
TEST=Build and boot to OS in Guybrush.
Change-Id: Ibfbe6e16bd6b0dd46c13cecf2a35f0c0b4576b88
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56684
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get the settings for fast-read and mode from EFS, and reprogram those.
Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings.
BUG=b:195943311
TEST=Boot and see that SPI was set to the correct speed & mode
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The common_i2c_save struct isn't specific to the I2C code and since it
contains the state of the GPIO control & status register and the state
of the GPIO MUX register, move it to include/amdblocks/gpio_banks.h and
rename it to soc_amd_gpio_register_save.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7cd47e5a32427d856948e319de8dfad8c928e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
No need to strip the quotes of the FSP-M file path in the size check and
it's always a good idea to not remove the quotes around file paths that
will get passed as parameters to shell programs so that spaces in the
path can't cause malfunction.
TEST=All cases still behave as expected for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ieeea84b5861f9d15b2472208432169dc8e3f0049
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Power down the eMMC controller via the AOAC interface when it's not
enabled in the devicetree.
BUG=b:184978118
TEST=On guybrush the unused eMMC controller is disabled in AOAC after
applying this patch. Before this patch it was enabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18f4626a29fdc422218777058341b0eae401bcd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
When CONFIG_FSP_M_FILE isn't defined, the parameter of the file-size
call evaluates to an empty string, so the file-size call will run
"cat | wc -c" which will cause make to get stuck in there. Also print a
message when no FSP-M file is specified that the resulting image won't
boot successfully.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b02774e2c79d12554fd076aa01bbe972176f372
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, The SPI speed/mode configuration is split between Kconfig
and devicetree. We'd like to have everything in one place. Since we
need the fast-read speed and the mode available in the Makefile to build
the AMD EFS table, we currently need it in Kconfig. Move all of the
settings to Kconfig and remove them from Devicetree in a later commit.
BUG=b:195943311
TEST=boot majolica & guybrush, verify spi settings
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56884
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When modules are added to the FSP and they won't fit into the FSP binary
any more, the size can be increased in the FSP build. Especially in the
case of debug builds the increased size might not fit into the memory
region it gets decompressed into which starts at FSP_M_ADDR and has a
size of FSP_M_SIZE. SoCs can implement the soc_validate_fspm_header
function that ends up being called by the FSP driver in romstage to do
some additional checks on the FSP binary's header that includes the
version number and the image size. We can use the image size field to
check if it fits into the reserved region. Since the FSP-M memory region
is located after romstage loading it won't clobber the romstage code
where we do the check.
This runtime check is added in addition to the build-time check to also
cover the case when the FSP binaries in CBFS get replaced with ones that
don't fit into the reserved memory region after the coreboot build.
BUG=b:186149011
TEST=Mandolin still boots fine with the patch applied. When as a test
the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000
which is by far not enough for the decompressed FSP-M binary to fit into
it prints the newly added error message on the console and then stops.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57068
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP-M binary needs to fit into the memory region that starts at
FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time
if the uncompressed FSP-M file is larger than the size of the region it
will be copied into.
BUG=b:186149011
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
PSP_Verstage will take almost the entire time to run that
is allotted to S0i3 resume. Since coreboot isn't running,
the PSP needs to handle any security requirements. The long-
term plan is that the PSP won't even load psp_verstage on S0i3
resume, but when it is loaded, this makes sure we exit
immediately
BUG=b:177064859
TEST=Verify that PSP_verstage doesn't run on S0i3 resume
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There are gremlins in the system. thread_coop_enable has an assert. This
is currently problematic for two reasons.
assert(current->can_yield <= 0);
When doing smm_do_relocate we are entering a deadlock. The root cause
hasn't been quite found yet, but it's related to co-op multi-threading.
For some reason the assert in thread_coop_enable is firing when
releasing the console_lock spin lock. I'm assuming cpu_info hasn't been
initialized yet. The assert tries to perform a printk, but since the
console_lock is still held we end up in a dead lock. This dead lock will
generally not happen after a warm reset. Again I'm assuming because the
cpu_info struct has some valid values at this point.
For now disable multi-tasking until we fix the cpu_info initialization.
BUG=b:194391185
TEST=Boot guybrush to OS
Co-developed-by: nikolai.vyssotski@amd.corp-partner.google.com
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia3143f538a31b5aaaea104aa1d8bcf44e6dcb528
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57005
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use correct format for constraint list as expected by kernel driver.
With this change, kernel is able to correctly list dummy device in
constraint list.
BUG=b:194687976
TEST=Build and boot to OS in Guybrush.
Change-Id: I7af1941ffd21cd5864c7285f44cb2d063d2f225f
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57012
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disabling the 4 DWORD bursts causes SPI DMA operations to stall, so
leave it enabled when SPI DMA is used.
BUG=b:194919326
TEST=Build and boot to OS in Guybrush.
Change-Id: I363acdcdb4178a10e4f7eb2bbcbd6d0ca7924f2d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
