Commit graph

5544 commits

Author SHA1 Message Date
Vaibhav Shankar
db54bb5e3a mainboard/intel/amenia: Configure PERST_0 pin
Configure PERST_0 and assign the pin in devicetree.

BUG=chrome-os-partner:55877
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.

Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16350
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 22:20:18 +02:00
Sumeet Pawnikar
7e10c8209b mainboards/apollolake: Set RAPL power limit PL1 value to 12W.
This patch sets tuned RAPL power limit PL1 value to
12W in acpi/dptf.asl for RAPL MSR register. With PL1
as 12W for WebGL and stream case, we measured SoC power
reaching upto 6W. Above 12W PL1 value, we observed that
Soc power going above 6W. With PL1 as 12W, system is
able to leverage full TDP capacity.

BUG=chrome-os-partner:56524
TEST=Built, booted on reef and verifed the package
power with heavy workload.

Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 22:19:08 +02:00
Vaibhav Shankar
8cdeef1c0d mainboard/google/reef: Configure PERST_0 pin
This configures PERST_0 in devicetree. For boards without
PERST_0, the pin should be disabled. For boards with PERST_0
the correct GPIO needs to be assigned.

BUG=chrome-os-partner:55877

Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16603
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-09-14 22:18:15 +02:00
Gwendal Grignou
6d8e39127b mainboard/google/reef: add MKBP EC event as SCI event.
Add MKBP as a SCI event: the EC is then able to send events coming from
the sensors.

BUG=b:27849483
TEST=With EC configure to send MKBP events, check sensor information are
retrieved by the kernel.

Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/16594
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 18:17:54 +02:00
Antonello Dettori
ec4555b96d lenovo/t60: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/lenovo/t60.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16405
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:24:20 +02:00
Antonello Dettori
30d55bf001 mainboard/bcom/winnetp680: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/bcom/winnetp680.

Change-Id: I6f57a669f83bed190e90e1b7be01f8c886546e2e
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16465
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:16:49 +02:00
Antonello Dettori
ef8021cc1b mainboard/gigabyte/*: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/gigabyte/*.

Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:16:35 +02:00
Antonello Dettori
837618bf20 mainboard/asus/*: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/asus/*.

Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:16:24 +02:00
Hakim Giydan
e889b19ba0 soc/marvell/mvmap2315: Add DDR driver
This driver is only a prototype driver, real driver
will be integrated at a later time.

Testing: booted successfully.

Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16554
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:03:53 +02:00
Hakim Giydan
65c7ccc8b1 google/rotor: Add support for the Rotor mainboard
Change-Id: I1f97b6f159a0ac36c96636066332ba355c056186
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15507
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:56:18 +02:00
Werner Zeh
9d18e330fd siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPC
Since this mainboard provides 4 COM ports on LPC, enable decoding of
the corresponding addresses using the generic LPC decode registers.

Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16535
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 22:41:45 +02:00
Arthur Heymans
a761fa5ec9 lenovo/t60: add hda_verb.c
This creates a config for the Lenovo T60 sound card based
on values taken from vendor bios
(in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16).
The sound card configuration on the vendor bios is the same
as the one on the Lenovo x60.

It improves the default behavior of the sound card:
- internal microphone is chosen by default
- when jack is inserted it is chosen instead of internal speaker

Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-09-12 20:00:40 +02:00
Rizwan Qureshi
06868f8154 kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake
uses FSP2.0 driver, keeping the fsp1.1 flow intact.

Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:56:09 +02:00
Venkateswarlu Vinjamuri
d2e92e461d mainboard/google/reef: Enable lpss s0ix
This setting enables lpss to power gate in S0ix.

BUG=chrome-os-partner:53876

Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:49:28 +02:00
Venkateswarlu Vinjamuri
6584973bdc mainboard/google/reef: Disable CLKREQ of unused PCIe root ports
1. Removes PCIe blocker for S0ix.
2. Set the correct PCIe root port for wifi/bt on EVT.
3. Turn off CLKREQs of unused PCIe root ports to power gate the IP.

Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:49:08 +02:00
Damien Zammit
55a54f662e mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridge
Although the goal was to hide the ME device by disabling
the PCI bridge, the original comment that this bridge was ME related
was a mistake, this bridge is for PEG not for ME.
We still need this PCI bridge "on" to enable pci express graphics
add-on cards.

Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16496
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-09 19:40:34 +02:00
Aaron Durbin
e642b2d1d3 mainboard/google/reef: move devicetree to baseboard
Move the current devicetree.cb to be under variants/baseboard.
New variants can provide their own devicetree as needed.

BUG=chrome-os-partner:56677

Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16510
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-08 16:24:33 +02:00
Kyösti Mälkki
e0d7e2690f intel/i82801gx 82801ix: Remove OpRegion of SMBus host
Defining this OpRegion for SMBus controller prevents linux kernel
driver i2c-i801 from registering SMBus under sysfs, with following
error in dmesg:

  ACPI Warning: SystemIO range .. conflicts with OpRegion .. (\_SB.PCI0.SBUS.SMBI)

Solution taken from intel/bd82x6x. Worth noting we do not
define ENABLE_SMBUS_METHODS anywhere currently.

Removed remaining reference to HSTS from GETAC P470.

Change-Id: I7c13d344b0343387681b46019cc5061b1435b46b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16266
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07 23:06:31 +02:00
Arthur Heymans
e8cf4ffbee mb/intel/d945gclf: Disable combined mode to fix SATA
Similarly to 2b2f465fcb
"mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA"
SATA must function in "plain" mode because it does not work in
"combined" mode.

Tested on d945gclf

Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16319
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07 23:05:23 +02:00
Damien Zammit
93157f6c1c mb/gigabyte/ga-g41m-es2l: Add IRQs for PCI express graphics in ACPI
With this patch and the previous ones in this set,
PCI express graphics is now working.

01:00.0 VGA compatible controller [0300]: NVIDIA Corporation GT218
        [GeForce 210] [10de:0a65] (rev a2) (prog-if 00 [VGA controller])

Change-Id: Ife691fb381e90e7744fe2ac4e20977be53419a14
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16497
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07 23:05:03 +02:00
Venkateswarlu Vinjamuri
e52592078e mainboard/google/reef: Enable audio clock and power gate
Removes S0ix blocker. Sets audio clock gate and power gate
bits when audio not in use. Reduces power in S0.

Change-Id: Id5c0adc2605480583dc90ee62a706dbfa4027c1b
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16424
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07 18:37:50 +02:00
Duncan Laurie
c2875872c8 google/reef: Enable I2C TPM
Enable the I2C based TPM on the reef board at
bus 2 and address 0x50.

This makes vboot functional without needing MOCK_TPM and
results in the following in the SSDT:

Device (TPMI)
{
  Name (_HID, "GOOG0005")  // _HID: Hardware ID
  Name (_UID, Zero)  // _UID: Unique ID
  Name (_DDN, "I2C TPM")  // _DDN: DOS Device Name
  Method (_STA, 0, NotSerialized)  // _STA: Status
  {
    Return (0x0F)
  }

  Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
  {
    I2cSerialBus (0x0050, ControllerInitiated, 0x00061A80,
                  AddressingMode7Bit, "\\_SB.PCI0.I2C2",
                  0x00, ResourceConsumer)
    Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive)
    {
      0x00000039
    }
  })
}

Change-Id: Ia9775caabeac3e6a3bd72de38f9611b4cea7cea4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16398
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-06 22:58:56 +02:00
Shamile Khan
93c5470434 google/reef: Enable 20K pull ups for LPC CLKRUN and LAD0:3 lines
The pull up for CLKRUN is required to resolve keyboard slowness
and malfunctioning observed on some reef systems. The CLKRUN
signal was probed and found to be floating when the pull up
was not enabled. Also Added pull ups for the LPC Multiplexed
command, address and data lines LAD0:3 because the LPC
Interface specification requires them.

BUG=chrome-os-partner:55586
BRANCH=none
TEST=When a key is pressed, the character is immediately visible
     on the screen. Also the interrupt count for i8042 increments
     immediately in /proc/interrupts.

Change-Id: I16df1a0301a3994c926a609f61291761219f9e01
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/16426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-09-06 20:22:27 +02:00
Aaron Durbin
37ddb630dd mainboard/google/reef: drop remaining proto board references
The last vestige of the proto boards is the memory sku id
gpios. The internal pullups are still required because there's
only pulldown stuffing options available on the reef boards.

BUG=chrome-os-partner:56791

Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16432
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-06 20:17:37 +02:00
Aaron Durbin
8db1f8dabb mainboard/google/reef: add baseboard nhlt configuration
Move the current NHLT configuration implementation to the baseboard
area such that other variants can leverage it or provide their
own configuration.

BUG=chrome-os-partner:56677

Change-Id: If0d48cacdc793492e1618d0eda02a149e33f0650
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16431
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06 20:16:56 +02:00
Aaron Durbin
d94967dd22 mainboard/google/reef: add baseboard memory configuration
Move the current memory configuration implementation to the baseboard
area such that other variants can leverage it. The swizzle config
is exported as a global to allow duplicate swizzles to use the same
structure while still allowing different memory SKUs.

BUG=chrome-os-partner:56677

Change-Id: I57201118053051c01f0e3f164ab4bbaf650b892b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16430
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06 20:16:32 +02:00
Aaron Durbin
475d2cb19e mainboard/google/reef: provide cros_gpio variant API
Add support for Chrome OS gpio ACPI table information by
providing weak implementation from the baseboard.

BUG=chrome-os-partner:56677

Change-Id: I517764b78f47fb7b3637482ff9efc053cdd1ac69
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16422
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06 20:16:13 +02:00
Aaron Durbin
d1e365ac38 mainboard/google/reef: consolidate gpio related defines to one place
Since multiple boards will be living within one directory move all
the macros for defining anyting related to GPIOs to the gpio.h
header file. That way, when other boards land they can override
or use them as is.

BUG=chrome-os-partner:56677

Change-Id: I36967e57fc61ef354e0b51d1ff1396ce562fa805
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16421
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06 20:04:37 +02:00
Aaron Durbin
b64389d840 mainboard/google/reef: declare mainboard_ec_init() in each C file
There's no common EC header file in the code base, and I didn't
want to use a header file for single declaration. Therefore,
just move the declaration to each file that uses that symbol.

BUG=chrome-os-partner:56677

Change-Id: Ibaebb0ea6a07029aec02d5185cf05ffb8593b117
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16420
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06 20:04:27 +02:00
Aaron Durbin
10d67cbad5 mainboard/google/reef: add variant API for board_id and gpio
Provide APIs for the board_id() and gpio table functionality.
Default and weak implementations are provided from the baseboard.

BUG=chrome-os-partner:56677

Change-Id: I02d8deb7f60f8c4842916a9d35f51d8af74b1da4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16419
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-06 20:04:18 +02:00
Marshall Dawson
96a8b54edb intel/minnowmax: Clean up whitespace
Align the column of comments.

Change-Id: Iec3a173af26710f8ff56519a14784344ea71d489
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16427
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-05 01:25:21 +02:00
Marshall Dawson
4551bf6dbf intel/minnowmax: Enable all PCIe ports
A recently announced Turbot system populates two Ethernet
controllers.  Enable the remaining disabled PCIe port.

Also add a clarifying comment regarding the port associated
with Function 0.  Coreboot must not be allowed to disable the
function which breaks PCI compatibility.

Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16429
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04 20:17:55 +02:00
Marshall Dawson
297c559562 intel/minnowmax: Program GPIO for power LED
MinnowBoard Turbot systems have a GPIO-controlled LED that is
generally used to indicate the CPU is running.  Commit 2ae9cce8
changed the parameter for GPIO_NC, exposing an issue with the
assumed behavior of the signal.  Use a pull-down to turn on the
LED.

Change-Id: I153870904c007d89016c0d47bb3db9b824ebbcff
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16428
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04 20:17:42 +02:00
Duncan Laurie
0604106438 google/reef: Fix indent in devicetree.cb
Indent the I2C device for touchscreen with tabs so it
aligns properly.

Change-Id: Id9b2d26a4acdd6fe6c69055907258df3cc035b31
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16399
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-09-04 05:43:00 +02:00
Aaron Durbin
114d7c3ada mainboard/google/reef: provide baseboard and variant concepts
To further the ability of multiple variant boards to share code
provide a place to land the split up changes. This patch provides
the tooling using a new Kconfig value, VARIANT_DIR, as well as
the Make plumbing. The directory layout with a single variant,
reef (which is also the baseboard), looks like this:

variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/reef - code
variants/reef/include/variant - headers

New boards would then add themselves under their board name
within the 'variants' directory.

No split has been done with providing different logic yet.
This is purely a organizational change.

BUG=chrome-os-partner:56677

Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16418
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-04 05:36:43 +02:00
Aaron Durbin
4435a490cd mainboard/google/reef: prepare sharing directory for variants
Instead of completely duplicating the a reference board's directory
when doing a variant or follower device start providing a means to
share code within a single directory. This change just starts the
process from the Kconfig side, but subsequent patches will follow
which disentangles the board specific pieces from and common
logic.

BUG=chrome-os-partner:56677

Change-Id: I96628920d78012e488ec008e35daac9c1be0cf79
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16417
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-04 05:35:03 +02:00
Aaron Durbin
5a87de86ae mainboard/google/reef: correct EC ASL includes
The superio.asl wasn't being included within the right scope.
Fix that as well as clean up the per-mainboard header includes
to be in one place.

BUG=chrome-os-partner:56677

Change-Id: I5e6a82f9f2e3c7455132263d19b32b2f06220376
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16413
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-09-04 05:34:15 +02:00
Aaron Durbin
48b4cbdd94 mainboard/google/reef: remove unused gpio.h macros
Some of the macros in gpio.h are no longer used because
devicetree.cb is being used to autogeneric the ACPI AML.
Therefore remove the unused macros.

BUG=chrome-os-partner:56677

Change-Id: I433a929229a0318f6c1df652655d046a5152cc63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16412
Tested-by: build bot (Jenkins)
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-04 05:33:59 +02:00
Brandon Breitenstein
c31ba0ef52 drivers/intel/fsp2_0: Make FSP Headers Consumable out of Box
The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.

BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully

Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02 18:12:24 +02:00
Antonello Dettori
4bf48e8c33 lenovo/x60: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/lenovo/x60.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

Change-Id: Icaceeae2fc7276efa82d37582ecac93aaf37c41c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16372
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02 18:10:10 +02:00
Arthur Heymans
734b3d1be0 lenovo/x200,t400: use gpio.h instead of gpio_setup
Uses gpio.h instead of default_southbridge_gpio_setup to configure
southbridge GPIO's. This is more consistent with how GPIO's are
configured on newer targets.

Change-Id: I6ccd0564b929e958864739b7cde04f5592c58479
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16379
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02 18:08:01 +02:00
Martin Roth
26d484a237 Fix newlines at the end of files
All but ga-g41m-es2l/cmos.default had multiple final newlines.
ga-g41m-es2l/cmos.default had no final newline.

Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-09-02 18:04:48 +02:00
Aaron Durbin
e603a90045 mainboard/google/reef: drop proto gpio support
Many changes make proto boards very hard to work with since
proto boards were using A stepping processors. Everyone has
moved on. Therefore, drop non-proto support.

BUG=chrome-os-partner:56791

Change-Id: I2985e3965b1b69445e22506bd664b4cbca13c8ab
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16377
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2016-09-01 00:21:05 +02:00
Aaron Durbin
9a251c0280 mainboard/google/reef: add pen connections
A pen interface was added. Prepare for possibly testing it by
plumbing in the gpio configuration. It's very possible these
changes need to be tweaked, but no driver code has been seen
yet nor a datasheet detailing how some of these signals actually
function.

BUG=chrome-os-partner:56739

Change-Id: I208ff3e151ce55d62e5fcc33a1e39cc87e229970
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16376
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01 00:20:52 +02:00
Aaron Durbin
f0cd74dd84 mainboard/google/reef: fix polarity of FP_INT
The formerly name FP_INT_L net is actually active high and is push-pull.
Therefore adjust for the new net name, FP_INT, and polarity. The
pulldowns are there because the device is on another board that isn't
always available.

BUG=chrome-os-partner:56740

Change-Id: I6706fd2c2bd164cf3b5f1457aef69f5675f2112d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16375
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01 00:20:37 +02:00
Aaron Durbin
3681de8ab6 mainboard/google/reef: add new memory SKUs
Two new SKUs are being utilized for reef DVT. Add the following:
Hynix 8GiB using H9HCNNNBPUMLHR-NLE -- id: 4'b0100
Hynix 4GIB using H9HCNNN8KUMLHR-NLE -- id: 4'b0101

BUG=chrome-os-partner:56738

Change-Id: I39ed9e827501939b92cbcce6092302b5a23d1d78
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16374
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01 00:20:10 +02:00
Aaron Durbin
0577a1e9d3 mainboard/google/reef: support WLAN_PE_RST
The reef DVT build added another way to assert the wifi module's
reset line. Ensure it's deasserted by default. For previous boards
this GPIO doesn't matter because it wasn't routed anyway.

BUG=chrome-os-partner:56737

Change-Id: I63e97b091ca0a278682c883303b1d7e052d8e677
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16373
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01 00:19:57 +02:00
Eric Gao
61e6c4448c rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpu
Before, we calculate the pwm duties for cpu cores and centerlogic by
hand, adding pwm_regulator.c to handle this. The default pwm design
min/max voltage may be different between revs.

With the pwm regulator, this patch changes the little cpu frequency from
600M to 1512M, and raises CPU voltage to 1.2V correspondingly.

This also means we decide to drop the ES1 because it may fail to
bootup with 1.5G ~ 1.2v.

BRANCH=none
BUG=chrome-os-partner:54376,chrome-os-partner:54862
TEST=Bootup on kevin board

Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9
Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b
Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/364410
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16368
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31 20:32:43 +02:00
Arthur Heymans
874a8f961f i945: Enable changing VRAM size
On i945 the vram size is the default 8mb. It is also possible
to set it 1mb or 0mb hardcoding the GGC register in early_init.c

The intel documentation on i945, "Mobile Intel® 945 Express Chipset
Family datasheet june 2008" only documents those three options.
They are set using 3 bits. The documententation also makes mention
of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it.

The other non documented (straight forward) bit combinations allow
to change the VRAM size to those other states.

What this patch does is:
- add those undocumented registers with their respective vram size to
the i945 NB code;
- make this a cmos option on targets that have this northbridge.

TEST: build, flash to target, set cmos as desired and boot linux.
On Debian it can be found using "dmesg | grep stolen".
NOTE: dmesg message about reserved vram are quite different depending
on linux version

Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14819
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31 20:01:05 +02:00
Shunqian Zheng
868cd71282 rockchip/rk3399: Move romstage.c to mainboard/gru
The romstage.c is more board related than soc specific, like
setting the pwm regulators, so moving it to mainboard/gru.

BRANCH=none
BUG=chrome-os-partner:54819
TEST=Bootup on kevin board

Change-Id: I83c6cde9f451480e47e2b4b549cedf65b345134c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 35feeb07131a6a9de4adde035236987391833474
Original-Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/375398
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16367
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31 19:59:55 +02:00