Commit Graph

20203 Commits

Author SHA1 Message Date
Paul Menzel db94213640 ec/lenovo/h8: Use older syntax for bit shift
Currently, when using `iasl` 20140926-32 [Oct  1 2014] from Debian 8
(Jessie/stable), the build of the Lenovo X60 fails due to syntax errors.

ASL 2.0 supports `<<`. For consistency, right now, coreboot still uses
the old syntax. So use `ShiftLeft` instead, which also fixes the build
issue with older ASL compilers.

Change-Id: Id7e309c31612387da3920cf7d846b358ac2bdc71
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18520
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-06 11:51:34 +01:00
Martin Roth 561f368a2f util/docker: Update dockerfiles & build method
All files:
- Previously, various things were hardcoded into the docker containers
that made it necessary to update the Dockerfile files for each new
version of the sdk.  Turn those into 'Variables" that are updated during
the build step.  Because the makefile is piping the dockerfile through
the sed command and back into the docker build command, the normal
docker "COPY" keyword doesn't work.

coreboot-jenkins-node changes:
- Run ssh-keygen -A to explicitly generate the ssh keys.  This fixes an
error:  Could not load host key: /etc/ssh/ssh_host_dsa_key

coreboot-sdk changes:
- Remove apt-get upgrade command - The Dockerfile guide recommends
not to run this.
- Change libssl-dev to libssl1.0-dev. libssl-dev's header files won't
build the Chrome-EC codebase.
- Add libisl-dev, needed to build the riscv toolchain.
- Build the toolchain using the -b option
- Add environment variables containing the version and commit that the
coreboot-sdk was built from.

Makefile:
- Update targets to use the version and commit variables

Change-Id: I2c1376fe4b791da2a62fca11bc92c4774cbef1c8
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/18001
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-03-06 00:30:35 +01:00
Iru Cai 03353de80b buildgcc: Update GCC, Binutils, GMP, MPFR, GDB, IASL and LLVM
- GCC gets updated from 5.2.0 to 6.3.0:
gcc-6.3.0_riscv.patch is a diff between 5fcb8c4 and 173684b in
riscv-gcc, and it needs gcc-6.3.0_memmodel.patch.

- Binutils goes from 2.26.1 to 2.28:
There is a build error for MIPS gold so I add patch for it.

- GMP gets a bump from 6.1.0 to 6.1.2
- MPFR is updated from 3.1.4 to 3.1.5
- GDB is upgraded from 6.1.1 to 6.1.2
- IASL is changed from 20160831 to 20161222
- LLVM is changed from 3.8.0 to 3.9.1

Change-Id: I20fea838d798c430d8c4d2cc6b07614d967c60c5
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17189
Tested-by: build bot (Jenkins)
2017-03-05 18:35:18 +01:00
Rizwan Qureshi 0da186c3ff soc/intel/skylake: indicate voltage margining enabled/disabled
Support for voltage margining is dependent on the platform.
Enabling voltage margining puts additional constraints for
the SLP_S0# to be asserted and hence moving to S0ix state.
If the platform PMIC/VR supports PCH voltage reduction,
voltage marigining can be enabled.

Use the UPD provided by FSP to enable/disable voltage margining.

Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18469
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-04 17:35:13 +01:00
Arthur Heymans d55ea7b69e mb/getac/p470: Do not select EARLY_CBMEM_INIT
This is selected by default and not overwritten anywhere else for this
board.

Change-Id: I0f803e130366ee322163f7bb6fa16cac75f5416e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18541
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2017-03-03 19:41:49 +01:00
Furquan Shaikh 2eb0837b90 mainboard/google/poppy: Disable deep S3 on poppy
BUG=chrome-os-partner:62963
BRANCH=None
TEST=Compiles successfully

Change-Id: Icb929262fd67362b8e5c5cf31dce04ab1f496695
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18467
Tested-by: build bot (Jenkins)
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-02 22:15:53 +01:00
Elyes HAOUAS 44a3066015 nb/i945: Clean "Programming DLL Timings" function
As we drive both channels with the same speed,
chan0dll and chan1dll are the same.

Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/18472
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
2017-03-02 22:14:53 +01:00
Ricardo Ribalda Delgado b2bb6ad2a7 agesawrapper: Fix endless loop on bettong
AGESA AmdInitEarly() reconfigures the lapic timer in a way that
conflicts with lapic/apic_timer.

This results in an endless loop when printk() is called after
AmdInitEarly() and before the apic_timer is initialized.

This patch forces a reconfiguration of the timer after
AmdInitEarly() is called.

Codepath of the endless loop:

printk()->
  (...)->
    uart_tx_byte->
      uart8250_mem_tx_byte->
        udelay()->
          start = lapic_read(LAPIC_TMCCT);
	  	do {
			value = lapic_read(LAPIC_TMCCT);
		} while ((start - value) < ticks);
         [lapic_read returns the same value after AmdInitEarly()]

Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/17924
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-02 22:04:43 +01:00
Nicola Corna e38f85915f util/me_cleaner: Pull the latest changes from upstream
Relevant changes (commit 250b2ec):
 * Fix a bug for ME6 Ignition images.
 * Fix signature checking for ME11 and later.
 * Add command line arguments.
 * Add an option to relocate the FTPR partition to the top of the
    ME region, recovering most of the ME region space.
 * Print the image minimum size.
 * Add write boundary checks, to prevent writes on other regions
    in case of bugs.

The new changes have been tested on multiple platforms by the
me_cleaner users. They have been tested also on the author's
X220T with coreboot, where the ME region has been shrinked up to
84 kB without any issue.

Change-Id: I3bd6b4cba9f5eebc3cd4892dd9f188744a06c42b
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18473
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-03-02 22:04:08 +01:00
Nicola Corna 4f4fc1891b MAINTAINERS: Add myself as me_cleaner maintainer
Change-Id: Ia95f6beb1546efdb75a49bccfe293822f0785d7a
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18474
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins)
2017-03-02 22:03:47 +01:00
Arthur Heymans 0cf6748e47 .gitignore: Add autoport binary
Change-Id: I610797d5002b229211e320a814ce14131cc1dfe7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18517
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-03-02 22:03:28 +01:00
Iru Cai bc5112029b autoport: add "-d" option to ectool to dump registers
Change-Id: I7de37a026a0899c2d07ea17c9377c8d2283450ab
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18481
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-03-02 21:59:27 +01:00
Daniel Kulesz 610d1c67b2 Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h"
This reverts commit fec8872c9d.

The commit introduced a regression which is causing MC4 failures
when 8 RDIMMs are populated in a configuration with a single CPU
package. Using just 4 RDIMMs, the failure does not occur.

After reverting the commit, I tested configurations with
1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an
Opteron 6276. The MC4 failures did not occur anymore.

Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65
Signed-off-by: Daniel Kulesz <daniel.ina1@googlemail.com>
Reviewed-on: https://review.coreboot.org/18369
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2017-03-02 20:40:30 +01:00
Duncan Laurie 59eddac6ad acpi: Update the ACPI ID for coreboot
The newly assigned ACPI ID for coreboot is 'BOOT'
http://www.uefi.org/acpi_id_list

Use this new range of ACPI IDs of "BOOTxxxx" for coreboot specific
ACPI objects instead of the placeholder range of "GOOGCBxx".

Change-Id: I10b30b5a35be055c220c85b14a06b88939739a31
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18521
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-02 18:53:04 +01:00
Youness Alaoui 601aa313a6 intel/broadwell: Use the correct SATA port config for setting IOBP register
Fix a typo that was introduce in commit 696ebc2d (Broadwell/Sata:
Add support for setting IOBP registers for Ports 2 and 3.) [1].

Setting one of the SATA port 3 IOBP setting was using the value from
the port 2 register.

On the purism/librem13 (on which SATA port 3 is tested), this change
doesn't seem to affect anything, as that typo wasn't exhibiting any
visible problems anyways.

[1] https://review.coreboot.org/18408

Change-Id: I3948def5c0588791009c4b24cbc061552d9d1d48
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/18514
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-02 09:21:55 +01:00
Mono a154a910cb mb/apple/macbook21: Remove PCI reset code from romstage
Follow commit 7676730 (mb/lenovo/x60: Remove PCI reset code from
romstage). The PCI reset was copied from code specific for Roda
RK886EX and Kontron 986LCD-M. It is not needed on the MacBook.

Change-Id: I22dac962e8079732591f9bc134c1433f5c29ff4e
Signed-off-by: Axel Holewa <mono-for-coreboot@donderklumpen.de>
Reviewed-on: https://review.coreboot.org/18502
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-01 17:04:35 +01:00
Elyes HAOUAS 308aefffc6 nb/intel/i945: Fix sdram_enhanced_addressing_mode for channel1
Change-Id: I304467353bb9989f0d7e0ad7d1b632081f66b1af
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/18482
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2017-03-01 17:03:07 +01:00
Barnali Sarkar c16d389363 src/include: Include stdint.h since struct dimm_info uses it
struct dimm_info has all the parameter types defined in stdint.h
file. So including it.

BUG=none
BRANCH=none
TEST=Build and boot KBLRVP

Change-Id: I707523749ecf415e993b460f9613eae7be859c34
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18471
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-01 16:57:34 +01:00
Barnali Sarkar e13b77564f soc/intel/common: Save Memory DIMM Information in SMBIOS table
Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.
Add function dimm_info_fill() which populates SMBIOS memory
information from FSP MEM_INFO_DATA_HOB data.

BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS table from Kernel command "dmidecode".

Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18418
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-01 16:32:21 +01:00
Barnali Sarkar 9e54978f6e src/vendorcode: Add Memory Info Data HOB Header
Add the MemInfoHob.h provided by FSP v1.6.0 for aid in parsing the
MEM_INFO_DATA_HOB.

BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP

Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18326
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-01 16:31:41 +01:00
Nicola Corna 068edc1c52 ec/lenovo/h8: Fix mute LEDs
thinkpad_acpi expects a SSMS method to turn on/off the mute LED
and a MMTS method to turn on/off the microphone mute LED. With
these methods implemented the driver can correctly sync the LEDs
with the corresponding statuses.

There seems to be two different bits to mute the audio in the
Lenovo H8 EC:
 * AMUT, used internally (for example to disable the audio before
    entering S3).
 * ALMT, controllable by the OS, which also toggles the mute LED
    (if present).

Tested on a X220T and on a X201.

Change-Id: I578f95f9619a53fd35f8a8bfe5564aeb6c789212
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18329
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins)
2017-02-28 16:30:06 +01:00
Nicola Corna 435d307415 mainboard/lenovo: Power off USB and mute audio before entering S3
Currently, the USB ports are still powered during S3, so turning
them off may reduce the power consumption.
Note that, when the USB Always on feature is enabled, the USB
ports are always powered, regardless of the USBP state.

This patch also disables the audio, as it might consume some
power or generate some noise.

Both the USB power and the audio are reenabled by coreboot during
the poweron.

Change-Id: If0431b1315fffef2e372e7023f830a66bb7fddae
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18464
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-02-28 15:56:06 +01:00
Nicola Corna b1ffff7dab ec/lenovo/h8: Pulse the power LED during S3, if supported
On the models that support it (like the X220) the LED pulses, on
the others (like the X201) the LED powers off.

Change-Id: I2ac7dbc30609179e4ca5fc0a7b06763431fe3344
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18325
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-02-28 15:10:42 +01:00
Nicola Corna 47f87bd93f ec/lenovo/h8: Add tablet mode switch method
thinkpad_acpi expects a MHKG method which returns the current
state of the tablet mode switch shifted left by 3. If such
method is not found, subsequent laptop/tablet mode events are
ignored.

Tested on a X220T.

Change-Id: Ic9ffea2ffe507b3692d1dd7411c52b813ec32146
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18328
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-02-28 14:54:59 +01:00
Arthur Heymans f77d6ba911 Select a default SeaBIOS PS2 timeout in H8 Kconfig
This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.

Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18274
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-02-28 14:49:15 +01:00
Ricardo Ribalda Delgado 77ced402fb payloads/seabios: Add support for Hudson UART
Since version 9332965 "serialio: Support for mmap serial ports", SeaBIOS
supports memory mapped serial ports. This patch automatically configures
SeaBIOS when the Hudson UART is enabled.

Change-Id: I072f6a957df7e143d790783546b0725bcd597d9c
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/18025
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-28 14:12:22 +01:00
Aaron Durbin 6295b8a57a mainboard/google/reef: keep LPSS_UART2_TXD high in suspend state
The cr50 part on reef is connected to the SoC's UART lines. However,
when the tx signal is low it causes an interrupt to fire on cr50.
Therefore, keep the tx signal high in suspend state so that it doesn't
cause an interrupt storm on cr50 which prevents cr50 from sleeping.

BUG=chrome-os-partner:63283
BRANCH=reef
TEST=s0ix no longer causes interrupt storm on cr50. Power consumption
     normal.

Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18491
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-25 18:19:56 +01:00
Duncan Laurie d4d6ba180d google/eve: Add rise/fall times for I2C buses
Apply tuning for the PCH I2C buses on Eve based on rise/fall time
measurements that were done with a scope.

BUG=chrome-os-partner:59686
BRANCH=none
TEST=Manual testing on Eve P1 to verify that all devices on I2C
buses are still functional.  Post-tuning measurement will be done
once a new firmware is released.

Change-Id: I3d70ff455a20ecda374d7e7fa6cd3ab15e7f2621
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18487
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-25 18:19:50 +01:00
Andrey Petrov 6a489237d5 mainboard/intel/leafhill: Clean up
This patch tries to clean the code by:
o removing duplication of LPC GPIO pads
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file

Also adds vital defaults in Kconfig so it is possible to build an image.

Change-Id: Id9913f3b053189166392271152ce5300d82a7de8
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18479
Tested-by: build bot (Jenkins)
2017-02-25 09:00:50 +01:00
Jonathan Neuschäfer 37e30aa624 nb/amd/amdmct: Remove another currently unused table
This fixes a warning that the new toolchain generates.

Change-Id: Idf46026729a474323e74a5cf7a156bf5bc8cf026
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18485
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-25 03:03:15 +01:00
Furquan Shaikh 613350897d mainboard/google/poppy: Change touchscreen IRQ to level-triggered
BUG=chrome-os-partner:62967
BRANCH=None
TEST=Verified that touchscreen works on power-on and after
suspend-resume as well.

Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-24 15:59:42 +01:00
Martin Roth cb69fbaa87 src/arch/x86: Remove non-ascii characters
Change-Id: Ie0d35c693ed5cc3e890279eda289bd6d4416d9e6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18376
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-24 06:56:03 +01:00
Denis 'GNUtoo' Carikli 08cf195f4c payloads/external/GRUB2: Add "git revision" to the GRUB2 version menu
This change is based on the following commit:
3aa91dc payloads/seabios: Add "git revision" to the SeaBIOS version menu

Change-Id: I9987e3673e70b5cb20173d1ddff6060f42a5374a
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/18352
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-24 03:50:02 +01:00
Tobias Diedrich 9b798d7904 ec/lenovo/h8: Guard against EC bugs in the battery status logic.
On my Thinkpad with an H8-compatible ENE KB9012 EC (GDHT92WW 1.52), when
the battery is nearly full and we switch from battery to AC by plugging
in the cable, the current rate will not drop to 0 immediately, but the
discharging state is cleared immediately.

This leads to the code trying to process an invalid rate value >0x8000,
leading to a displayed rate of >1000W.

This patch changes the logic to deal with these corner cases.

Change-Id: Ideb588d00757f259792e5ae97729e371b63a096c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/18349
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-24 03:32:11 +01:00
Martin Roth 80c314d64a arm-trusted-firmware: Disable a couple of warnings for GCC 6.2
- Remove warnings about code using deprecated declarations such as:
plat/mediatek/mt8173/bl31_plat_setup.c: In function 'bl31_platform_setup':
plat/mediatek/mt8173/bl31_plat_setup.c:175:2: warning:
'arm_gic_setup' is deprecated [-Wdeprecated-declarations]
include/drivers/arm/arm_gic.h:44:6: note: declared here:
void arm_gic_setup(void) __deprecated;

- Disable pedantic warnings to get rid of these warnings:
In file included from plat/mediatek/mt8173/bl31_plat_setup.c:36:0:
plat/mediatek/mt8173/include/mcucfg.h:134:21: error:
enumerator value for 'MP1_CPUCFG_64BIT' is not an integer constant
expression [-Werror=pedantic]
MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT

Change-Id: Ibf2c4972232b2ad743ba689825cfe8440d63e828
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17995
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-24 03:27:41 +01:00
Jonathan Neuschäfer a6b1b258d2 nb/amd/amdmct: Remove two currently unused tables
This fixes warnings that the new toolchain generates.

Change-Id: I83d2c4c4651a89b443121312a5f36adfc1e4bc48
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18308
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-24 03:26:51 +01:00
Jonathan Neuschäfer c706eaf068 mb/emulation/*-riscv: Don't select ARCH_BOOTBLOCK_RISCV
It's already selected by SOC_UCB_RISCV.

Change-Id: Ic8a14300cdea2a4ab763b2746434891b72843604
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18390
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23 21:41:19 +01:00
Patrick Georgi 96af0afcd7 google/gru: whitespace fix
Follow up to https://review.coreboot.org/#/c/18460/

Change-Id: Ic3aada2acf3051622698e10d2e764050e16480d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18475
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23 18:51:34 +01:00
William wu ebbdd2882e google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold
According to USB 2.0 Spec Table 7-7, the High-speed squelch
detection threshold Min 100mV and Max 150mV, and we set USB
2.0 PHY0 and PHY1 squelch detection threshold to 150mV by
default, so if the amplitude of differential voltage envelope
is < 150 mV, the USB 2.0 PHYs envelope detector will indicate
it as squelch.

On Kevin board, if we connect usb device with Samsung U2 cable,
we can see that the impedance of U2 cable is too big according
to the eye-diagram test report, and this cause serious signal
attenuation at the end of receiver, the amplitude of differential
voltage falls below 150mV.

This patch aims to reduce the PHY0 and PHY1 otg-ports squelch
detection threshold to 125mV (host-ports still use 150mV by
default), this is helpful to increase USB 2.0 PHY compatibility.

BRANCH=gru
BUG=chrome-os-partner:62320
TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into
Type-C port, check if the USB device can be detected.

Change-Id: Ia0a2d354781c2ac757938409490f7c4eecdffe61
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d74311c25762668386061234df0562f84b7203e
Original-Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8
Original-Signed-off-by: William wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/431015
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Inno Park <ih.yoo.park@samsung.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18462
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2017-02-23 18:51:21 +01:00
Caesar Wang 8c454aaafa google/gru: update the pwm regulator
As David commented the "Bob and other follow-ons match Gru, Kevin should
be the special case here", and update the calculations value for gru/bob
board.

From the actual tests, some regulator voltage than the actual set of less
than 20mv on bob board. (e.g: little-cpus and Center-logic) Update the
{min, max} regulator voltage for Bob board. Make sure we get the accurate
voltage.

BUG=chrome-os-partner:61497
BRANCH=none
TEST=boot up Bob, measure the voltage for little cpu and C-logic.

Change-Id: Iad881b41d67708776bfb681487cf8cec8518064e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 25e133815f49018e7496c75077b8559c207350a4
Original-Change-Id: I3098c742c7ec355c88f45bd1d93f878a7976a6b4
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/424523
Original-Reviewed-by: David Schneider <dnschneid@chromium.org>
Original-Reviewed-by: Brian Norris <briannorris@chromium.org>
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/430403
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18460
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23 18:51:09 +01:00
Sumeet Pawnikar d56fae18dc mb/google/poppy: Enable support for DPTF
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for poppy.
It enables the DPTF flag in the device tree for poppy. It also includes
the DPTF specific ASL file in the main DSDT definition.

BUG=None
BRANCH=None
TEST=Built for poppy.

Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17926
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-23 18:42:58 +01:00
Kyösti Mälkki 57d4c30e22 lynxpoint bd82x6x: Enable PCI-to-PCI bridge
Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.

It was previously argumented this is copy-paste and never known
to be required for these more recent platforms:
   https://review.coreboot.org/#/c/2706/

Change-Id: Ic8911500a30bc83587af8d4b393b66783fa52e18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18330
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-23 18:36:24 +01:00
Patrick Georgi a5c029f235 intel/minnow3: follow up with recent changes in master
minnow3 doesn't build right now due to API divergence on master branch.
Follow up with recent changes.

Change-Id: Iee84750292f22aa040127bcbfe523a0b9eaa8176
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18476
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2017-02-23 18:21:12 +01:00
Yidi Lin 57debca234 google/oak: Add initial support for Rowan
Update GPIO controls and mainboard configurations for Rowan.

[pg: use the opportunity to clean-up the gerrit-rebase task list with
the entirely unrelated Ignore-CL-Reviewed-on lines]

BUG=chrome-os-partner:62672
BRANCH=none
TEST=emerge-rowan coreboot

Change-Id: I110fb368b3d9fa9dfb2bf091342dfb511ff7c09c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4252cbe94a7456108aaa522e170bca5dcb1fdd1
Original-Change-Id: I18ebc3ccf4c7d051839d7c50e9b0682ef8f09830
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/430557
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/341513
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/327003
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/355221
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/354670
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361360
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361361
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361362
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361363
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/382320
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/405110
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/405130
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/419795
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/424139
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430293
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430294
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430295
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427820
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427821
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427822
Reviewed-on: https://review.coreboot.org/18463
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23 17:41:22 +01:00
Caesar Wang 9e588004f6 google/gru: improve eye diagram for passing the test
The children of Gru should share the benefits. In the real world, Bob can't
pass the eye diagram tests.

BUG=chrome-os-partner:62714
BRANCH=firmware-gru-8785.B
TEST=build coreboot

Change-Id: I2470bbc81acdaf2458d660dca5dc307cc3038f83
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0cb3e718a7571f602a00c08a42019851634e7fd
Original-Change-Id: I0ccb48bb52eb770ccc9c8c265b07df46b0308dd3
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/440745
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/441468
Reviewed-on: https://review.coreboot.org/18461
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23 17:41:17 +01:00
Rizwan Qureshi c2c8a743d1 soc/intel/skylake: Enable Systemagent IMGU
Camera and Imaging device should be enabled for camera usecase,
FSP provides a UPD to enable/disable the SA IMGU (Imaging Unit)
expose the same as a config option in devicetree.cb

Also remove a redundant assignment for PchCio2Enable.

BUG=None
BRANCH=None
TEST=lspci should list 00:05:00

Change-Id: I4cf7daf41bfaf4dcba414921cac2e7e12bf89f37
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18365
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23 17:05:58 +01:00
Paul Kocialkowski 30d4604e5a mt8173: Enable Kconfig options for ChromeOS
This enables some required Kconfig options when CONFIG_CHROMEOS is set.

Change-Id: I290902746c1ea19c8bcb69540e34fde09abb9adf
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/18448
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-02-23 17:04:51 +01:00
Paul Kocialkowski 7a543d2ab9 libpayload: Add oak config
This adds an oak libpayload config, that should fit all oak-based
devices such as elm.

Change-Id: Iabb71404ff84029a5976371a353e8c92e781ca1f
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/18447
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-02-23 17:03:45 +01:00
Arthur Heymans 00954f0815 mb/apple/macbook21: Remove unused cmos parameters
These parameters are probably the result of copying from the Thinkpad
X60 code.

Change-Id: I29763b38618d4b306c37424c5c4b57dfcf69424b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18290
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-23 17:02:53 +01:00
Brenton Dong 6530b6d30d intel/minnow3: Implement and configure GPIO tables
Copy GPIO table implementation from the google/reef board except
with board variant features removed. Also exlcude CrOS GPIO functions.
Remove previous romstage GPIO implementation in brd_gpio.h and romstage.c.

Configure GPIO settings for MinnowBoard 3.

Change-Id: Id2817dcf2f8f196ecd13c810f7f0010a115db566
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18375
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-22 23:22:13 +01:00