Use post_code() instead of 'outb(value, CONFIG_POST_IO_PORT)'.
Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69901
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
All parameters of DPTC_INPUT() need to be configured on devicetree
when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enabled. The parameters without
configurations on devicetree would be 0 when
SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document
#57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA
and vrm_soc_current_limit_mA on devicetree with thermal table config E
as default table for SMT. Since the dynamic thermal table switching
mechanism is still under cooking, after discussing with thermal team,
suggest adopting config E(limit Soc not reach to max power) as default
thermal config to avoidany thermal-related issue during phase build.
Once the dynamic thermal table switching mechanism is finished, will
change the default value to config A.
BUG=b:258572474, b:248976976, b:259167917, b:257394883
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This patch helps to save 10.200ms of booting time without any issue
seen during MP Init. All cores are out from reset and alive.
Port the Alder Lake 'commit 6526e78967 ("soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL")' also to Meteor Lake.
Additionally, no performance degradation is observed while running
benchmarks.
BUG=b:211770003
TEST=Able to boot Google, Rex to ChromeOS with all cores enabled.
Without this patch:
30:device enumeration 1,480,217 (28,232)
With this patch:
30:device enumeration 1,472,466 (18,334)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iec21470b9b34514169789c39bdc3be4e4ff6c7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69851
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the most part, this just moves the existing post codes into macros
so that they're not just bare numbers.
cache_as_ram.S:
Post code 0x28 was previously pointless with just a single jump between
it and post code 0x29, car_init_done. This code was removed, and the
0x28 value was used to differentiate the car_nem_enhanced subroutine
from the other 0x26 post codes used before calling the clear_car
subroutine.
All other post codes remain identical.
POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas
the POST_SOC codes are expected to be Intel only.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No real functional changes, just cleaning up shellcheck issues, putting
braces around variables, add comments and the like.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6e79afc8d725e86ddbf7f4eb4685bed190c20738
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67319
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves a lot of post code values, but unifies them between
platforms, so that the same value means the same thing as much as
possible.
The P4-netburst code was the most extensive and most different, so that
dictated the majority of the values. Three were two values there that
didn't match the other files, so those two values, 0x22 & 0x29 have
duplicate entries in the table.
The rest of the entries are similar between platforms, though the values
for many of them were moved to match the P4-netburst values.
POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become
global, while POST_SOC would be specific to the Intel platforms.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69866
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
"../cmake" introduced on Change-Id: I3144a83
Remove "../cmake" when the build is done.
Change-Id: I289bfaca1fd8d3f004455babd99849ca8aa2d6db
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
It shouldn't be assumed that all variants of skyrim will use the same
gpio for TPM interrupts.
Use the PSP's new mailbox command to tell it what gpio the tpm interrupt
comes in on.
BUG=b:248193764
TEST=tast run <ip> hwsec.TPMContest
Verify log entry:[DEBUG] PSP: Setting TPM GPIO to 18...OK
Use incorrect GPIO in mailbox cmd and verify TPMContest test
failed.
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69874
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot only supports a small subset of the targets that LLVM supports.
It's not needed to enable all possible targets. Thus limit the targets
to the following ones:
* X86
* RISC-V
* AArch32
* AArch64
* PowerPC
Change-Id: I9938bf176b5fe2b0a631c3b1ae858f988898a196
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69841
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur.heymans@9elements.com>
For nissa, the ISH main firmware will be included in the CSE region in
flash instead of loading it from rootfs. So remove the ISH
firmware-name.
BUG=b:234776154
TEST=Boot to OS on nirwen and yaviks UFS SKUs. Check ISH firmware is not
loaded by kernel, and device still goes to S0i3.
Cq-Depend: chrome-internal:5102230
Change-Id: I68f963e17bc0dbf9db9adaaa3f96f06b8737523b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69868
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
BUG=b:253387689
Test:Boot to OS on craask and check SAR Proximity Sensor GPIO pin
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I2b2a2516890b68036e96d1a542e6a10a098cb6a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69790
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Move smbios_ec_revision to ocp folder so that all ocp boards
share the same function without implementing again.
TESTED=Execute "dmidecode -t 0" to check corresponding field.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Jonzhang Zhang <jonzhang@meta.com>
Change-Id: I898662b78d3dbab1861cee6f1b6e148297a5d11b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68785
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Following warnings occur when compiling with
`i386-elf-gcc (coreboot toolchain v2022-09-18_c8870b1334) 11.2.0`
drivers/serial/8250.c:75: [-Werror=unused-variable]
Move variable declaration inside the
`#if !CONFIG(LP_PL011_SERIAL_CONSOLE)` block
drivers/udc/dwc2.c:505: [-Werror=format=]
use `%zd` to match type `size_t`
Change-Id: Id285c24cba790f181fa203f3117e5df35bed27c4
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69764
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
With the addition of the clang tests, the jenkins builds are taking a
really long time to run the tests. This change allows the
"what-jenkins-does" build to be split into separate builds on jenkins.
Additionally, some jenkins builds like coverity don't need (or want)
to build clang or even the linters.
Update help with the variables.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0f8ac68c1bc8f8ff9be62d80db850355e742ee74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This tests building a single target with scanbuild so to make sure that
option hasn't been broken. Since it's a different type of build, it
hasn't previously been tested with what-jenkins-does.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8a74dac203f4d38c0cb30a0b64724e6f9095b9dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This gets rid of the duplicated directory and xml filename and uses the
--name argument to abuild instead, which also updates the test name in
the junit xml file.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ibe538da42280696190b0a7a0c63fd86a63e40214
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Previously, the testclass variable was only updated with the chromeos
or Kconfig option values, and the output directory and xml file names
were updated independently.
With the --name option, all of these can be set simultaneously. This
also prevents jenkins from seeing clang and gcc tests as the same
because the testclass variable wasn't updated.
If --name is not set, all behavior is as it was previously.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8f52779b92d213386a3eb371d1f30ee32ed48b85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69859
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of having duplicate lines in the what-jenkins-does target and
the test-tools target, make test-tools from what-jenkins-does.
Now there's only one place to update when changing the call.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id62d6bb1e729892ec123ea970ca8a31e03a812d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It's hard to tell what is what with the short option names, so use the
long options here.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1371e098bba1077dedfaffa56287a28656197b40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69837
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of having duplicate lines in the what-jenkins-does target and
the test-abuild target, make test-abuild from what-jenkins-does.
The test-abuild target had not been updated to use the ABUILD_OPTIONS
variable, so update it with the commands from what-jenkins-does.
Now there's only one place to update when changing the call.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4552193894c16301defb851eb3db4bdfbfa49803
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of having duplicate lines in the what-jenkins-does target and
the test-lint target, make test-lint with the --junit argument from
what-jenkins-does.
Now there's only one place to update when changing the call.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f90df76126f453fbcd91f4c4af5d784ac2dbe88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of having the what-jenkins-does target clean up before building,
have it call the test_cleanup target.
Clean the tegra targets.
Remove distclean from test_cleanup target - I don't think that's
expected, and people might be upset by having their .config deleted.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia9d585df05343365c89e49b1c01dba9ba865003f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
CBFS_MCACHE is currently experiencing overflow with CBFS verification
enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB.
This reduction along with the available free space in PSP shared buffer
(32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required
14 KiB.
BUG=b:259342909
TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS
mcache overflows.
FMAP: area COREBOOT found @ 80a000 (8347648 bytes)
VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported
CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes
CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640
VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled
Ensure that firmware_CbfsMcache FAFT test is successful.
Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If no boards are tested by abuild, an error is currently shown because
no boards failed, but no boards passed either. Account for this
possibility.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I097d3c728ca1acc652d5a1b7b49e57d01b0e513b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE is nowadays defined in
vboot/firmware/2lib/include/2constants.h, so update the comment.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7c9a5476ae06d4bac762da1729aff878b7d0965
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The patch parses CPU and PCH Trace Hub modes from the debug area in the
Descriptor Region. The modes can be updated in the debug area in order
to configure the CPU and PCH Trace Hub modes. The debug area's offset
starts from the SPI Flash offset:0xf00.
For runtime debugging, the OEM Section in the Descriptor Region is being
used as debug area. The OEM Section details are documented in the SPI
Programmer Guide of CSE Lite kit.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
One register configuring multi-pin functions was outside of the Global
Configuration Registers space and skipped in the initial port patches.
Replicate the vendor configuration and set the Super I/O pin for PECI
functionality.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add pcie_find_dsn() to detect and match PCIe device serial
number. In addition, vendor ID is matched when provided.
Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Elyes Haouas