This change drops the inclusion of codec.asl in DSDT for `GOOG0013`
device and instead uses the newly added Chrome EC audio codec driver
for filling in the device node in SSDT.
TEST=Verified that following node gets generated:
Scope (\_SB.PCI0.LPCB.EC0.CREC)
{
Device (ECA0)
{
Name (_HID, "GOOG0013") // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Name (_DDN, "Cros EC audio codec") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
}
Change-Id: I3e626ce01a3735ac2c966c0e95310be4c828b241
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43042
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change drops H1_PCH_INT macro for GPIO_9 since it is the same
across all variants. Also, the name differed from the schematics
version `H1_PCH_INT_ODL` creating confusion.
Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
For historical reasons, Windows has issues with certain names being
used for files and directories, 'con' or 'CON' being one of
them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in
order to work around this issue.
TEST=built volteer (only user of this driver as of now)
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
The eSPI polarity macros were reversed. Those are fixed so adjust
the corresponding values related to the correct expectations of
the IRQ path: eSPI virtual wire IRQs are active level high. The EC
sends active level high virtual wire IRQs. The default interrupt
encodings in ACPI for P2/S devices are active edge high. Therefore,
there is no need to override anything.
BUG=b:157984427
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
V.2: Spare USB routed internally to another peripheral and so
no plug event hook needed.
BUG=b:1603699358,b:157479891
BRANCH=none
TEST=none
Change-Id: Ideacac417a46b96f3e82b53bbb341ecce79ee420
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42994
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves the generation of I2SM ACPI device from static asl
file to runtime generation by ACP device driver. dmic_select_gpio is
set to match version 3+ of Trembyle and Dalboz schematics. In order to
maintain backward compatibility, dmic_select_gpio is updated at
runtime using variant_audio_update for board versions that are prior
to version 3 of reference schematics.
The only difference from static generation is that the device I2SM is
added under ACPD (i.e. ACP device) instead of CREC (Chrome EC
device). It does not make any functional difference from the kernel
perspective.
BUG=b:157603026
TEST=Verified that the following device gets generated in SSDT:
Scope (\_SB.PCI0.PBRA.ACPD)
{
Device (I2SM)
{
Name (_HID, "AMDI5682") // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Name (_DDN, "I2S machine driver") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
"\\_SB.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x000D
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"dmic-gpios",
Package (0x04)
{
\_SB.PCI0.PBRA.ACPD.I2SM,
Zero,
Zero,
Zero
}
}
}
})
}
}
Verified audio via speakers and mic input.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I5d1602c7f719eef9487ddea68e429d27408f9a76
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2253638
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Modify DPTF parameters for faffy from thermal team.
BUG=b:160292247
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
verify the parameters are correct
Change-Id: Ie8290f5460838f785a587c85b2ab7dd171dd0a54
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Currently, EC wake signal (GPIO_24) is configured early on in
romstage. However, there is no need for that since EC wake is not
really required to be configured until ramstage. This change moves
GPIO_24 configuration to happen in ramstage.
BUG=b:159832123
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6949dcd7c866df2fa028c7b2e7f347cec988e309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42952
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the pad configurations for wake lines as
follows:
1. Pen eject wake signal needs to be configured as PAD_WAKE i.e. wake
using GPIO controller block. This is because pen eject signal is not
dual routed and the trigger filtering is set by the kernel driver
differently for S0 and S3 wake. Hence, it cannot use SCI GEVENT and
instead has to fall back to using GPIO controller wake.
2. All other wake signals (EC, trackpad, fingerprint) need to be
configured as SCI. This allows OS to enable/disable wake from these
sources if required. Example: powerd disables wake from trackpad when
in tablet mode. Hence, all other wake sources use SCI.
BUG=b:159832123
TEST=Verified wake using pen eject and EC.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id8cd5926f223db51a689ed8948040b8070cf1680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42951
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature.
BUG=None
BRANCH=None
TEST=Built for dedede platform and verified the MSR value
Change-Id: I53d1bd413c64643cf8bdaef266bde25a2f3a97ee
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42906
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for pen insert/eject operations in S0 and
wake on pen eject from S3 for morphius.
BUG=b:158814699,b:158719244
Change-Id: I3530a0aa83ec69559436687205c64524b862799b
Signed-off-by: Kevin Chiu <kevin.chiu@quanta.corp-partner.google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change drops macros for GPIOs which are unused or don't really
require extra indirection (same across all variants).
BUG=b:159283649
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1a94327103a419f26b1d7feda4c995363ada7281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Board version 3 for Ezkinil follows Trembyle reference v3.51
schematics and hence GPIO_86 does not need a variant specific override.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7e04baad976f94d0d94e7196f0408c3c3237b2da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A late change went into v3+ of reference schematics which inverted
EN_PWR_WIFI to meet PCIe reset/power timings for WiFi device. This is
incorporated into v3.51+ for Trembyle reference and v3.2+ for Dalboz
reference. However, some variants are built with v3+ reference
schematics, but without the inversion of EN_PWR_WIFI polarity. Thus,
we need to add support for following combinations:
1. Pre-v3 Schematics
2. V3+ Schematics
3. V3+ Schematics + Active low wifi power
This change adds a new Kconfig
`VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW` that sets the minimum
board ID that has EN_PWR_WIFI active low in hardware. Variants that
missed this change in V3+ integration (berknip and vilboz) have board
IDs set to VARIANT_MIN_BOARD_ID_V3_SCHEMATICS + 1. For others, this
defaults to VARIANT_MIN_BOARD_ID_V3_SCHEMATICS.
BUG=b:159749536
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib8da7fba5f4a518a51b203d6a01a9551e261d8b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change moves variant_sleep_gpio_table() definition to dalboz and
trembyle references to allow each to make their own changes.
BUG=b:159749536, b:159453643
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I15b19cea05f1a540c56b6bc0507306d2348ac17f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change moves PCIE_RST1_L deassertion to happen as part of
variant_pcie_power_reset_configure() instead of
variant_romstage_entry() since romstage is guaranteed to run 100ms+
after PP3300_NVME is enabled. This is one of the first things that
coreboot on x86 does as part of early mainboard configuration.
Additionally, this change also drops deassertion of PCIE_RST0_L on bid
1 for dalboz since PCIE_RST0_L is already deasserted much earlier in
the boot flow.
BUG=b:152582706
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib734aa6ff664268e68388b1997ddce676504f8d2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261996
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Aaron Durbin <adurbin@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in
sleep path so that the PERST# to NVMe device keeps asserted until
coreboot reconfigures it as high on S3 resume path. This is similar to
the earlier change for PCIE_RST1_L but helps platforms that use
NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain,
hence it retains state across S3 entry/exit.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie79e946eee8f393863630226ae2183e653030415
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261117
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change configures PCIE_RST1_L as GPO driven low on the sleep
path. This is required to keep PERST# asserted to devices until
coreboot deasserts it on S3 resume path. Without this change, on S3
resume, PCIE_RST1_L gets deasserted sooner than required resulting in
violation of PCIe reset timings.
With this change, the behavior of PCIE_RST1_L is as follows:
1. GPIO27 is configured as NF (PCIE_RST1_L) in coreboot
bootblock/romstage and driven high.
2. On S3 entry, GPIO27 is configured as GPO driven low.
* Boot out of G3: Timing should be met since GPIO_27 is pulled down by
default until coreboot configures it.
* S3 resume: Timing should be met since GPIO_27 is configured as GPO
low and it retains state across S3 entry/exit. So, should be low
until coreboot configures it.
* Warm reset: Timing should be met since it is configured as NF. So,
hardware guarantees the reset timing as seen in "warm reset.jpg" in
#46.
BUG=b:152582706
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia0ad1522edc438fd054d927ef4a2ab5c27329c00
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261116
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change turns off power to camera and pen devices when entering
sleep since they do not act as wake sources in S3. Power to trackpad
and WiFi is left enabled since they are wake sources for S3.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I21bcdd53370372c7d43c3b685abb2a9171e42d22
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261115
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds support to configure GPIOs on the sleep path. This is
required to turn off power to devices that do not act as wake sources
and to assert reset to devices.
Currently, variant_sleep_gpio_table() returns an empty table by
default. In the following changes, entries will be added to
gpio_sleep_table.
BUG=b:152582706
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7286cbf165024bdd81f8748e525542dce8dd8702
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2253642
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Override VBT for nightfury SKU_ID = 2 to support different panel.
BUG=b:159051021
BRANCH=firmware-hatch-12672.B
TEST=Built and verified using different VBT by SKU_ID
Change-Id: I9450814aadc43cc7991457c3793f109b889186b9
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
in some m/b+BOE panel(G2 TS), G2 TS may still have chance to lost even
rst delay time already meets spec definition: 10us (minimum).
Restore G2 TS RST delay time to 50ms, we could have G2 TS working fine
on those specific m/b+BOE(G2 TS) panel.
BUG=b:159510906
BRANCH=master
TEST=emerge-zork coreboot
boot with G2 TS, make sure G2 TS is functional
Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
due to overridetree.cb set disable_xhci_lfps_pm = 0,
need correct condition expression to let function work.
BUG=b:155955302
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ia047c75611a35aafd15f2481bf64049e13d4a2ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42860
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, for Stoneyridge and Picasso mainboards, pads that are
configured for SCI/SMI/WAKE need to have multiple entries in the
configuration table - one for PAD_GPI and other for the special
configuration that is required. This requires a very specific ordering
of pads within the table and is prone to errors because of conflicting
params provided to the different entries for the same pad. This also
does not work very well with the concept of override GPIOs where the
entry in base table is overridden with the first matched entry from
the override table.
This change updates the way GPIO configuration is handled for special
routing like SCI/SMI/WAKE/DEBOUNCE by setting the control field of
soc_amd_gpio structure in the macros performing these
configurations. Also, program_gpios() is updated to perform a write to
GPIO control register instead of read-modify-write. This is because
mainboard is expected to provide only a single configuration entry for
each pad within a given table. Thus, there is no need to preserve
earlier configuration.
Mainboards that were providing multiple entries for a single pad are
updated accordingly.
BUG=b:159944426
Change-Id: I3364dc2982d66c4e33c2b4e6b0b97641ebea27f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
H1 is not a wake source and hence there is no need to configure SCI
GEVENT for it. This change drops PAD_SCI() configuration for GPIO_9
i.e. H1_PCH_INT_ODL.
BUG=b:159944426
Change-Id: Iec2285b76f9c5fa1b4b1be15128fea316fa04555
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature.
BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value
Change-Id: I6438547e09a3ff3a1c01addfcc01383e89f5b435
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use defines found in <cpu/x86/smm.h>.
Change-Id: Ib75df13021120fb2c056782c252e97d6b036c7da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Using proper symbols for base addresses, it is possible to
only define the symbols for base addresses implemented for
the specific platform and executing stage.
Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Due to faffy has PL-2303 connect to USB2 port6(count from port0),
needs to enable it.
BUG=b:159760559
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
boot on puff board
Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Both Dali and Pollock chips have less PCIe, USB3 and DisplayPort
connectivity. While Dali can either be fused-down PCO or RV2 silicon,
Pollock is always RV2 silicon.
Since we have all boards using this code in tree right now,
soc_is_dali() can be renamed and generalized to soc_is_reduced_io_sku().
Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows mainboard to configure different wakeup routes that
can be used by a GPIO key:
1. SCI: This is selected when SCI route is used to wake the system. It
results in _PRW property being exposed in ACPI tables.
2. GPIO IRQ: This is selected when GPIO controller wake is used to
wake the system. It is typically used when the input signal is not
dual routed and the GPIO controller block is not capable of applying
filters for IRQ and wake separately. In this case, _PRW is not exposed
in ACPI tables for the key device.
3. Disabled: No wakeup supported.
Based on these wakeup routes, gpio_keys_add_child_node() is updated to
expose _PRW and _DSD properties for wakeup appropriately.
Additionally, the change updates mainboards that were already using
gpio_keys to set wakeup_route attribute correctly and renames "wake"
to "wake_gpe" to make the usage clear.
BUG=b:159942427
Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 1408798637.
Reason for revert: Causing backlight issues in device. Will reland after more debugging to figure out the root cause.
BUG=b:159370566
BRANCH=None
TEST=boot up device and make sure when kernel is booted, backlight comes up.
Change-Id: I643854c6c805d262539bbb482808e8c322059a49
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
That option is only relevant if the boards selects HAVE_PIRQ_TABLE which
it doesn't.
Change-Id: Ib5839a42f5133f5f84e1e1e4e587801b916ca571
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Currently, Reset Power Cycle Duration is set with default value (4s).
This adds around ~5 seconds of delay during power cycle or global reset.
So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s
to minimize the delay.
Delay with Power Cycle or Global Reset:
Existing behaviour:
S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch:
S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert.
The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width
to 98ms not 2s.
Test=Verified on Hatch and Puff boards
BUG=b:158634281
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
