Commit Graph

35990 Commits

Author SHA1 Message Date
Angel Pons e2a2877adf nb/intel/ironlake/hostbridge_regs.h: Clean up registers
Remove duplicated definitios and sort them by ascending offsets.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Idcfa64a39c12a4ac06a342ef9b51a01b806d4c84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03 05:28:09 +00:00
Angel Pons e9d1d70c7f nb/intel/ironlake: Put host bridge registers into its own file
Looks like some registers are defined twice. Also, group some QPI
registers together. They were scattered around and mixed with the host
bridge registers, probably because other northbridges have such
registers in the host bridge's PCI config space. But not Ironlake.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I6e60f7fcb1467f302618eeab1b0d995920a98569
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03 05:27:45 +00:00
Angel Pons 0a760cd05b nb/intel/pineview/hostbridge_regs.h: Clean up registers
Sort them by ascending offsets.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03 05:27:28 +00:00
Angel Pons 0ddc2459bc nb/intel/pineview: Put host bridge registers into its own file
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: I12d6adb8f130599a33d71d7c9f71914ee7c9e8ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03 05:27:19 +00:00
Angel Pons 6b2be99eb1 nb/intel/x4x/hostbridge_regs.h: Clean up registers
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I8d68a1dd49769ac49009a8e628f7994bf461a05f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03 05:27:00 +00:00
Angel Pons 3896576a16 nb/intel/x4x: Put host bridge registers into its own file
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I2c59099f6ff0e9162c700c888fb8fbb3906b65e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03 05:26:46 +00:00
Sumeet R Pawnikar b278838fd2 mb/google/dedede: Update CPU critical temperature
Observed thermal shutdown initiated by DPTF due to CPU temperature
reaching critical temperature trip value. During stress testing with
heavy workload like WebGL Aquarium, sometime CPU temperature spikes
till 99 degree Celsius and DPTF initiates system shutdown. This
updates CPU critical temperature trip value to 105 degree Celsius
to avoid system shutdown.

BUG=b:161993459
BRANCH=None
TEST=Built and tested on dedede system

Change-Id: If15a873a997aa80f20940f27bbafd4498908c091
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44054
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:25:17 +00:00
Huayang Duan eef0152cc4 mb/google/kukui: Add Micron 8GB discrete LPDDR4X DDR support
Support 8GB MT53E2G32D4NQ-046 discrete DDR bootup.

BUG=b:159301679
BRANCH=kukui
TEST=Boots correctly on Kukui.

Change-Id: Ide01f029c5ebd6c3ae6350f73f3c60b818d51353
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-03 05:24:53 +00:00
Tim Chu 6b297c07c3 drivers/ipmi/ocp: Add ipmi set processor information
Implement setting processor information to BMC based on
document YosemiteV3_BMC_Feature_Spec_v1.7.

TEST=Use get command in OpenBMC to check.
Command and information are shown as below:

root@bmc-oob:~# ipmi-util 1 0xd8 0x11 0x4c 0x1c 0x00 0 1
DC 11 00 47 65 6E 75 69 6E 65 20 49 6E 74 65 6C 28 52 29
20 43 50 55 20 30 30 30 30 25 40 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00
root@bmc-oob:~# ipmi-util 1 0xd8 0x11 0x4c 0x1c 0x00 0 2
DC 11 00 1A 34 00 DC 05 41 30
root@bmc-oob:~#

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I3d53ac241a11ca962572816283a0c653fcde9f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:24:27 +00:00
Maxim Polyakov a9713c11c0 mb/intel/cedarisland: Remove duplicated code
Some UPD options are already set in `xeon_sp/cpx/romstage.c`. Remove
them from the board configuration to avoid duplicating this code.

Change-Id: Ic79245103c33427e06c7ea881be778e3d219c45f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43924
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:23:42 +00:00
Maxim Polyakov c8b7215639 mb/intel/cedarisland: Use FSP_M_CONFIG structure to set UPD
According to src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h,
use FSP_M_CONFIG structure fields to configure UPD options for FSP-M
in romstage instead of raw offsets.

Change-Id: Idb25d8954b09805b496ab97b341a8ef1ac38bb6a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:23:27 +00:00
Dtrain Hsu a64748c202 mb/google/dedede/var/madoo: Add discrete WiFi configuration
Add RTL8822CE support for Madoo.

BUG=b:162390420
BRANCH=None
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage, build successful

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I6e471be2b2856977e6f728d5a2ca78942725bea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-03 05:21:23 +00:00
Dtrain Hsu 092ef11a12 mb/google/dedede/var/madoo: Support Elan touchpad and configure I2C ports
1. Add Elan touchpad support.
2. Follow schematic to disable I2C1 and I2C3.

BUG=b:160869188,b:161407664
BRANCH=NONE
TEST=emerge-dedede coreboot chromeos-bootimage", build successful

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I154a1ff2597968d200d1d0693718f90cd2744616
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-03 05:21:10 +00:00
Ian Feng c6ee65f543 mb/google/dedede/var/madoo: Enable Goodix touchscreen
Add Goodix touchscreen support.

BUG=b:160868197
BRANCH=None
TEST=emerge-dedede coreboot chromeos-bootimage", build successful

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I9bf27d69d0895cb4ea8620a6da49e98d25e05c23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44012
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:21:01 +00:00
Aamir Bohra dde6b8a89c src/soc/intel/jasperlake: Update SD card ACPI device
1. Add _DSM method
2. Add support to turn on/off the power enable signal in _PS0/_PS3
   methods.

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I4f944caa535bdc946eef1e0f518fe3ee344187b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-03 05:20:52 +00:00
Maxim Polyakov 4ecc903222 mb/up/squared/gpio: 3/3 Convert bit field macros to PAD_CFG
Converts bit fields macro to target PAD_CFG_*() macros, which were
hidden in the comments. To do this, the following command was used:

./intelp2m -n -t 1 -p apl -file ./test/up-gpio.h

This is part of the patch set
"mb/up/squared: Rewrite pad config using intelp2m":

CB:42608 - 1/3 Decode raw register values
CB:42915 - 2/3 Exclude fields that are not in PAD_CFG*
CB:39765 - 3/3 Converts bit field macros to PAD_CFG

Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.

Change-Id: I266ec6fa10a9691a7b7d3cd6f2792624e8bd53d5
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:20:18 +00:00
Maxim Polyakov 5da541f9e7 mb/up/squared/gpio: 2/3 Exclude fields that are not in PAD_CFG*
This patch excludes bit fields that must be ignored in order to convert
current macros to target PAD_CFG_*() macros. The following commands
were used for this:

./intelp2m -ii -fld cb -ign -t 1 -p apl -file ./up-gpio.h

This is part of the patch set
"mb/up/squared: Rewrite pad config using intelp2m":

CB:42608 - 1/3 Decode raw register values
CB:42915 - 2/3 Exclude fields that are not in PAD_CFG*
CB:39765 - 3/3 Converts bit field macros to PAD_CFG

Change-Id: Ic9b6e63c1b84b97726886bef35c434dd9153eb78
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-03 05:20:07 +00:00
Maxim Polyakov 922c67bd35 mb/up/squared/gpio: 1/3 Decode raw register values
Use the intelp2m utility [1] with -fld=cb options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to
generate the target macro in the comments, so that it is easier to
understand what result we should get:

./intelp2m -ii -fld cb -t 1 -p apl -file ./up-gpio.h

This is part of the patch set
"mb/up/squared: Rewrite pad config using intelp2m":

CB:42608 - 1/3 Decode raw register values
CB:42915 - 2/3 Exclude fields that are not in PAD_CFG*
CB:39765 - 3/3 Converts bit field macros to PAD_CFG

[1] https://review.coreboot.org/c/coreboot/+/35643

Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.

Change-Id: I2523439af8842365c7de901bdfad85ad16d25dcf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:19:51 +00:00
Iru Cai 12a13e1f30 nb/intel/haswell: Add Crystal Well PCI IDs
From a log of a machine using Crystal Well CPU [1], Crystal Well CPUs
use some new PCI IDs. Without this patch, the Crystal Well northbridge
cannot be initialized in ramstage, thus the machine cannot boot. Some
PCI IDs of Crystal Well related devices can be found in the PCI ID
database [2].

Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS. The board
boots to SeaBIOS with boot screen displayed on HDMI output, and then
boots Arch Linux on a USB disk.

[1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/DNHLQTNTRQT43T67DG7L2HVI5CV74ZCM/
[2] https://pci-ids.ucw.cz/read/PC/8086

Change-Id: Icfe55323fd06187148c788ebfa7b679b6944e4f3
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41658
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:16:41 +00:00
Iru Cai 27126f135d cpu/intel/haswell: add Crystal Well CPU IDs
Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:16:29 +00:00
Iru Cai 9c20ad6da2 cpu/intel/common/fsb.c: add Crystal Well support
Without this change, there will be no console output when using a
Crystal Well CPU.

Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS.

Change-Id: Id18645c52d9c4a4ea7acb602bcb39b796d9e24b9
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:16:19 +00:00
Julius Werner 2aedc9776a assert.h: Try to evaluate assertions at compile time
Many places in coreboot seem to like to do things like

 assert(CONFIG(SOME_KCONFIG));

This is somewhat suboptimal since assert() is a runtime check, so you
don't see that this fails until someone actually tries to boot it even
though the compiler is totally aware of it already. We already have the
dead_code() macro to do this better:

 if (CONFIG(SOME_KCONFIG))
   dead_code();

Rather than fixing all these and trying to carefully educate people
about which type of check is more appropriate in what situation, we can
just employ the magic of __builtin_constant_p() to automatically make
the former statement behave like the latter.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I06691b732598eb2a847a17167a1cb92149710916
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-03 05:15:59 +00:00
Julius Werner 3e034b6e9a Change all assert(0) to BUG()
I would like to make assertions evaluate at compile time where possible,
but sometimes people used a literal assert(0) to force an assertion in a
certain code path. We already have BUG() for that so let's just replace
those instances with that.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I674e5f8ec7f5fe8b92b1c7c95d9f9202d422ce32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:15:15 +00:00
Julius Werner c435d3daa7 qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32
According to my SC7180 reference manual, these three GPIOs are in the
NORTH TLMM, but our pin table lists them as SOUTH. That means all
accesses our code has been doing to them have just been hitting empty
address space.

BUG=b:160115694

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If9c03ac890a7975855394c2e08b8433472df204d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-08-03 05:13:07 +00:00
Jes Klinke 683ac6f204 lib/string: Add standard strstr() function
Adding implementation of standard library strstr()

See https://review.coreboot.org/c/coreboot/+/43741 for context.

Change-Id: I63e26e98ed2dd15542f81c0a3a5e353bb93b7350
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-03 05:12:23 +00:00
Alex Levin e968e3762e mb/google/volteer: Change wake to be triggered on a raising edge
ACPI_GPIO_IRQ_EDGE_BOTH sets both edges as wake. The desired behavior is wake on rising edge, change to ACPI_GPIO_INPUT_ACTIVE_LOW.

Fixing for both Volteer and Volteer2 variants.

BUG=b:146083964
BRANCH=None
TEST=tested on a Volteer

Change-Id: I2d3339151bf4e2cbae60aaf97ba1bd7909a2b9a9
Signed-off-by: Alex Levin <levinale@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-03 05:11:50 +00:00
Patrick Rudolph 6588652ef5 mb/emulation/qemu-armv7: Fix board
Fix multiple issues allowing to boot until "Payload not loaded":

* The FMAP_CACHE was placed in memory mapped flash
  - Place the FMAP_CACHE in DRAM.
* The FMAP_CACHE was overlapping the BOOTBLOCK, which has a default size
  of 128KiB.
  - Increase the bootblock size in memlayout to 128KiB to match the FMAP.
* The heap in bootblock wasn't usable.
  - Add a linking check in armv7 common bootblock to relocate itself to
    the linked address.
* A FIT payload couldn't be compiled in as the POSTRAM_CBFS_CACHE was
  missing.
  - Add the POSTRAM_CBFS_CACHE to memlayout.
* The coreboot log is spammed with missing timestamp table error messages
  - Add TIMESTAMP table to memlayout.

Tested on QEMU armv7 vexpress.

Change-Id: Ib9357a5c059ca179826c5a7e7616a5c688ec2e95
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03 05:11:17 +00:00
Hung-Te Lin 935495f3e7 mb/google/kukui: indent config names for burnet and esche
The 'burnet' and 'esche' in Kconfig.name should have two spaces
after the arrow.

BUG=None
TEST=make menuconfig
BRANCH=kukui

Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43986
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:10:09 +00:00
Paul Menzel e1574e31f6 Doc/mb/facebook/monolith: Correct grammar by removing plural *s*
Change-Id: I2d14902f9d975e89cd2842f4c12eab8ca4018fbf
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44018
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:09:50 +00:00
Paul Menzel d3d316a28f Doc/mb/lenovo: Mark up file name as code/monospace
Change-Id: I397b1dc0c3faf65811889d4c5814d6dcca7fe6b4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43748
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:08:58 +00:00
Martin Roth 114cf22e8d drivers/amd/i2s_machine_dev: return if scope is NULL
Avoid dereferencing a null pointer.

Found-by: Coverity CID 1430549
BUG=None
TEST=Build

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I53f6a38aac6e7f94c3c370996b3b82ca0d88dac4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-03 05:08:39 +00:00
David Wu 6880aec670 mb/google/volteer/var/todor: Support ELAN i2c-hid touchpad
Update ELAN i2c-hid touchpad configuration

BUG=b:160741785
BRANCH=None
TEST=Verify touchpad is working fine.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2549048766d0707666910bd86c46ac9201bf3905
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43998
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:07:58 +00:00
Kevin Chiu a3bd96fe36 mb/google/zork: Add Samsung K4AAG165WA-BCTD SPD
For dirinboz
DRAMID 0x9: K4AAG165WA-BCTD

BUG=b:161579679
BRANCH=master
TEST=build

Change-Id: I28c0d23f96c5b9c975ffead3a1cac66cbda8c293
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-08-03 05:07:06 +00:00
Caveh Jalali 7eaac6cdc1 soc/intel/tigerlake: Invoke PCIe root port swapping
PCIe bus:function specifiers need to be coalesced the same way
functions are coalesced during bus enumeration. Invoke PCIe root port
devicetree update to swap the enabled root port devices with the
disabled devices.

At this point, the TGL pci_devs.h only describes the PCH-LP, so only
the PCH-LP root ports are listed in this patch. We'll need to add
additional PCIe root ports when PCH-H support is added.

BUG=b:162106164
TEST=Ensure that the PCIe device 1c.7 corresponding to Root port 8 is
swapped with the PCIe device 1c.0 corresponding to Root port 1.

Change-Id: I9230de8b1818f3f2115dab923841fd0e7778be62
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-03 05:06:34 +00:00
Sugnan Prabhu S 6d9f243835 drivers/intel/mipi_camera: Add reference counting for shared resources
This change updates the mipi_camera driver to handle shared power
resource between multiple cameras. This is achieved by adding a guard
variable and methods to manipulate the guard variable before calling
the actual platform method which enables or disables the resource.
PowerResource will call these guarded methods to enable or disable the
resource. This protects the shared resource from being enabled or
disabled multiple times while the other camera is using the resource.

Example:
Consider a platform where two cameras are sharing a GPIO resource 0xXX
and both the cameras calls enable and disable guarded methods for this
GPIO. Actual platform disable method for the GPIO is called only after
the last camera using the GPIO calls DSBx method and RESx becomes 0.

Scope (\_SB.PCI0)
{
	Name (RESx, Zero)
	Method (ENBx, 0, Serialized)
	{
		If ((RESx == Zero))
		{
			\_SB.PCI0.STXS (0xXX)
		}

		RESx++
	}

	Method (DSBx, 0, Serialized)
	{
		If ((RESx > Zero))
		{
			RESx--
		}

		If ((RESx == Zero))
		{
			\_SB.PCI0.CTXS (0xXX)
		}
	}
}

Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 03:44:50 +00:00
Felix Held e2f5fb2549 vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments
Also document the maximum nuber of lanes for the different platforms.

Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44069
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02 16:45:22 +00:00
Angel Pons 13cd145e02 configs: Add a weird config for Asrock B85M Pro4
This config is meant to build-test several options, such as SMMSTORE,
UBSAN, SIL3114 driver, EM100 support, code coverage and debug options.
Please do not try to use it on real hardware. Or maybe do try.

Change-Id: I8bc19a1987b405d5a654276050b00b956acbdf36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43977
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02 13:09:06 +00:00
Angel Pons bdd3d5f3de soc/intel/baytrail/northcluster.c: Clean up comments
Giant commit aee7ab2 (soc/intel/braswell: Clean up) reformatted comments
to follow the coding style, among many other things. This commit updates
some comments on Bay Trail with two objectives: follow the coding style,
and reduce the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: Ibe942a20c624e2c74801c8816616ec83851949af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-02 13:08:50 +00:00
Angel Pons c3be055fbe soc/intel/baytrail/sata.c: Fix SATA init sequence
SeaBIOS on Bay Trail would time out when trying to access a SATA drive.
Turns out that there's two mistakes in the SATA initialization sequence:

 - PCI register 0x94 is wrongly cleared with a bitwise-and operation.
 - PCI register 0x9c is instead written to 0x98, clobbering the latter.

After correcting them, SeaBIOS can boot from SATA on Asrock Q1900M.

Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44088
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02 12:18:40 +00:00
Mate Kukri e231949b78 soc/intel/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on
	Bay Trail
- Tested on GBYT4, should work everywhere as it's meant to behave
	exactly the same as the binary refcode

Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I91977c509022b0078804dc151d27296260e24bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43133
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02 12:07:08 +00:00
Angel Pons 32b93c94e0 soc/intel/baytrail/northcluster.c: Rename variable
Tested with BUILD_TIMELESS=1, Google Ninja does not change.

Change-Id: I7e74f342c0545f8d2a2128de4162581e5dc01e17
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02 12:03:40 +00:00
Angel Pons 7bef2eeb8e soc/intel/baytrail/northcluster.c: Tidy up long lines
These now fit in 96 characters.

Tested with BUILD_TIMELESS=1, Google Ninja does not change.

Change-Id: I7e1dc0126fa4d64f75e686d68c4f70f7109c6da0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02 12:03:21 +00:00
Angel Pons 31d6cd7495 soc/intel/braswell/northcluster.c: Tidy up long lines
These now fit in 96 characters.

Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical.

Change-Id: I4275c81d22c03c461c184f26367db80b828033a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02 12:03:04 +00:00
Angel Pons 3a713c0060 soc/intel/braswell/northcluster.c: Rename macro
Spell `KiB` with lowercase `i`.

Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical.

Change-Id: Ief606686ee3866a7ede75d097feb510418621fe8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02 12:02:46 +00:00
Subrata Banik 6362de3829 soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated
FSP default UPD for SkipMpInit is set to 0 which refers to run CPU
feature programming on all cores (BSP + APs).

Setting SkipMpInit=1 is not recommended as it will only limit CPU
feature programming on BSP.

TEST=Able to perform CPU feature programming by FSP on all cores
using external MP PPI services.

Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-08-01 06:55:36 +00:00
Subrata Banik 46f8073249 util/ifdtool: Add Alderlake platform support under IFDv2
Change-Id: Ief8ab6ad280d8a2625404c19d57cd2a24f23cf13
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39533
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01 06:55:25 +00:00
Subrata Banik a717e2f896 util/ifdtool: Make JSL platform entry for lock_descriptor
Change-Id: Ia2ddb4eceab29810b22766a0f241ba4b11e79538
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44057
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01 06:54:51 +00:00
Angel Pons f01884e48c sb/intel/lynxpoint/me_9.x.c: Constify string array
Jenkins complains about `const char *` and says it should instead be
changed to `const char *const`. So, change it so that Jenkins is happy.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: Iecd5fecdefdc2effd0114706648747460d0a4a72
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42630
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31 23:34:49 +00:00
Angel Pons 028b8e440b nb/intel/haswell: Configure VCs on Egress Port
System BIOS needs to program the Virtual Channel configuration.

Change-Id: Ic8ff17b3a1c4414633a658c60f2c4f7b195e5825
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43821
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31 23:33:43 +00:00
Felix Held 42d5294793 vc/amd/fsp/picasso: document DXIO lane number mapping
Haven't found the official documentation for the DXIO lane mapping on
Pollock, so I had to guess that from the working configurations used in
google/dalboz and amd/cereme.

Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44063
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31 21:05:34 +00:00