Currently, the LTE pins are enabled in gpio.c, then disabled in
fw_config.c if LTE is not present. However, since there's a short delay
between mainboard_init() and fw_config_handle(), this means that when
LTE is not present GPP_H19 (SOC_I2C_SUB_INT_ODL, used for the SAR
sensor) will be floating for a short period of time.
Rework the GPIO config so that the LTE pins are disabled in the
baseboard, then enabled in fw_config.c for variants using LTE. However,
this doesn't work for WWAN_EN and WWAN_RST_L since they need to be
enabled in bootblock. So these are instead enabled in the variant
gpio.c, then disabled in fw_config.c if LTE is not present.
BUG=None
TEST=LTE still works on nivviks
Change-Id: I9d8cbdff5a0dc9bdee87ee0971bc170409d925a2
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
To make sure Realtek RTL8822CE suspend stress test smoothly, we remove
1c.7 as wireless LAN (WLAN) connects the signal PCIE_4 and it will map
to 1c.7. refer to Intel Simon comment (https://partnerissuetracker.corp.google.com/issues/230386474#comment12),
as well as, remove redundant 17.0 and 1c.6 that both are described by
baseboard/devicetree.cb
BRANCH=dedede
BUG=b:230386474
TEST=on beadrix, verified by Realtek RTL8822CE can run suspend stress
test properly.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ib418eed57f07afaa6b397b42a057808eab142f7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This patch fixes a potential corner case scenario where the value of
CONFIG_DEFAULT_CONSOLE_LOGLEVEL is less than `BIOS_SPEW` hence, coreboot
is unable to redirect FSP serial messages over UART.
Rather than passing hard coded `BIOS_SPEW` for the FSP debug handler,
this patch now calls get_log_level() function to pass the supported log
level while printing FSP serial msg.
BUG=b:225544587
TEST=Able to build and boot taeko. Also, able to see FSP debug log with
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8a18101f5c3004252205387bde28590c72e05b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64460
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.
We checked power on sequence requires enable pin prior to reset pin
delay of 50ms and add delay of 20ms to meet the sequence on various
eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in
chapter 7.2.
BUG=b:231291431
TEST=USE="project_crota" emerge-brya coreboot chromeos-bootimage
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Id9bed46e801602f3f327753053ec6a1ceb0656e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Follow this commit 95986169f (soc/intel/alderlake: Skip FSP Notify APIs)
to skip FSP Notify APIs.
Elkhart Lake SoC deselects Kconfigs as below:
- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
to skip FSP notify APIs (Ready to boot and End of Firmware) and make
use of native coreboot driver to perform SoC recommended operations
prior booting to payload/OS.
When deselecting these Kconfigs, cse_final_ready_to_boot() and
cse_final_end_of_firmware() in the common cse driver will be used
instead as required operations to perform prior to booting to OS.
Check out this CL for further info:
commit 90e318bba (soc/intel/common/cse: Add `finalize` operation for
CSE)
Additionally, create a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again config.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I477c204233f83bc96fd5cd39346bff15ed942dc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove two redundant `void *` casts in `clrsetbits32()` calls. In
addition, preemptively retype the `io_mem_base` variable in order
to avoid having to add casts in future commits.
Change-Id: Iae9c8189a6f8cd29181c52c2241789c6d392d77b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch adds the support to enable the external V1P05/Vnn rails
in S0 state via devicetree.
BUG=b:223102016
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I555e5607af15a5f5d83ef74321b1b71f17cca289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This patch updates the VccIn Aux Imon IccMax for ADL-N to SOC SKU
specific value of 27A.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified that VccIn Aux Imon IccMax value is set to 27mA.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: If09cd1112fac9b30ff04c45aa5a6062c2513c715
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
EC wake event doesn't work. Nissa has a separate EC wake pin. SCI only
is not handled by EC, so we need to set dual route to wake the system.
BUG=b:229142661
TEST=EC wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ide1f4a2494bb0a64b11ab4c5135fc43d2a635f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
There are two APL specific config switches for RAPL and min. cpu clock
(APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches
could be used in future in other CPU platforms. Move them to common code
instead of having them just for one SOC.
Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings
(MSR0x610) do not change with this patch applied on mc_apl{1,4,5}
mainboard.
Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Now that the bootblock isn't added to cbfs anymore, on some targets it's
only conditionally build. One example would be Intel APL where it only
gets build when stitched into an IFWI. This is always done when
compiling for real targets but not by the CI builder. This adds a dummy
target to make sure the bootblock always gets buildtested.
Change-Id: I60601e01a2c370b5c21493b71d51f495bb42f41d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
AGESA.h has a '#pragma pack' nested somewhere. The pack pragma packs all
structs which is not what is expected in the structs inside the headers
included below AGESA.h.
Change-Id: Ia70f68ea0ece7c097a37517206d75b71d695561f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's
state in the devicetree. This avoids having to manually make sure the
SMBus PCI device and the `SmbusEnable` setting are in sync.
Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Builds are failing sporadically with:
src/lib/master_header_pointer.c:5:10: fatal error: fmap_config.h: No such file or directory
5 | #include <fmap_config.h>
| ^~~~~~~~~~~~~~~
Correct the filename in the Makefile from header_pointer.c to
master_header_pointer.c so that there's a dependency from
master_header_pointer.c to fmap_config.h.
Change-Id: I41bcb2a21fdbc48f09d5b6be3e211ca56607d849
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64431
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Update override devicetree based on schematics.
2. Update Kconfig based on schematics.
BUG=b:229191897
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ia28ae16f609fda6d90558e69b2d41139dbe533fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Add the support RAM parts for mithrax.
Here is the ram part number list:
DRAM Part Name ID to assign
K4U6E3S4AA-MGCR 0 (0000)
K4UBE3D4AA-MGCR 1 (0001)
H9HCNNNBKMMLXR-NEE 0 (0000)
MT53E1G32D2NP-046 WT:A 2 (0010)
MT53E1G32D2NP-046 WT:B 1 (0001)
BUG=b:229191897
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I2d19721a44f0176365a81da30d2f49b68a14df7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Configure GPIOs according to schematics
BUG=b:229191897
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I31a1e02b2fa3d2075efbf488cd611b6c5a88500f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
The psp_notify_boot_done call is done at the entry of BS_PAYLOAD_BOOT,
so it's not guaranteed that the psp_set_spl_fuse call is done before the
psp_notify_boot_done call. Moving the psp_set_spl_fuse call makes sure
that it's done before the psp_notify_boot_done call. This also brings
the psp_set_spl_fuse call in line with the enable_secure_boot call that
sends the PSB fusing command to the PSP.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id76b462608c3d788cd90e73a64d18c8e8b89dbfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Hook up the hyper-threading setting from the FSP to the option API so
that related mainboards don't have to do that. Unless otherwise
configured (e.g. the CMOS setting or overriden by the mainboard code),
the value from the Kconfig setting `FSP_HYPERTHREADING` is used.
Also, remove related code from the mainboard kontron/bsl6, since it is
obsolete now.
Change-Id: I1023d1b94acb63f30455c56b394b68059deaaa16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On this mainboard there are legacy PCI devices connected behind a
PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This
patch disables the unused PCI clock outputs on the XIO2001 bridge.
Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
device.c should not hold arch specific code.
Change-Id: I9dfdb905a83916c0e9d298e1c38da89f6bc5e038
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Follow the Kinox_schematic_R01_20220418.pdf to set memory SMBus
addresses to 0x52, 0x50.
BUG=b:231398371
TEST=Build and boot to OS with either 1 or 2 DIMM slots populated.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I32bb4f62a6b8a485ac757a60f5d16adb69109e2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This area is used for storing AP RO verification information.
BRANCH=none
BUG=b:227801913
TEST=build and boot nivviks
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: If5c03aca56e659d61c31613b284a55d0eba0d843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Use 'ENV' consistently and drop the redundant 'STAGE' in the naming.
Change-Id: I51f2a7e70eefad12aa214e92f23e5fd2edf46698
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Two trailing whitesspaces have an actual meaning in Markdown files (a new line).
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
amdfwread was added to the testing makefile but ended up not becoming a
separate tool. This commit removes it from the makefile so that `make
distclean` works again.
Fixes: 29bc79fddb ("util/amdfwtool: Add
amdfwread utility")
TEST=Ran `make distclean`
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I2c8b920bc69d6c20558a28515c52a1e9cecebe27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mcfg->usb_phy is a pointer to a struct usb_phy_config. The config is
constant. Changing a constant is undefined behavior, so create a local
static instance of usb_phy_config that can be modified safely.
Change-Id: If9b76b869a5b0581f979432ce57cc40f1c253880
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add and use defines instead of magic values in fsp_m_params.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64126
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use sizeof instead of having a hard-coded struct length.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85dc2fce11d9a670b2037d8a6a694177cfaa2177
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This variant uses all three EHL Ethernet GbE-TSN Controller so enable
the TSN GbE driver in order to set the needed MAC addresses. The
required function to retrieve a valid MAC address was already implement
in the common mainboard.c for mc_ehl.
TEST:
- Boot mc_ehl2 into Linux and check MAC addr via 'ip a'
Change-Id: Ia052c44feb606f9e1d31d047f2acc67e3226a895
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch provides the functionality to change the TSN GbE MAC
addresses. Prerequisite for this is a mainboard specific function that
returns a matching MAC address.
A test was performed with the next patch in the series, which enables
the TSN GbE driver for mc_ehl2 mainboard.
Change-Id: I2303a64cfd09fa02734ca9452d26591af2a76221
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
TSN runs in SGMII mode on this mainboard. This requires setting the link
speed to 1 Gbps.
Change-Id: I9f1da971b4de5671d6d38be6dbc50edbbe20d157
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard uses all three internal Ethernet GbE-TSN controllers. Two
of them are initialized by the Programmable Services Engine (PSE).
This patch enables the Serial Gigabit Media Independent Interface
(SGMII) mode for GbE PSE0 and GbE PSE1. By setting PCH PSE DMA pins to
host owned, the IO is under control of the IA processor cores through
system software.
TEST:
- Boot mc_ehl2 into Linux and check inet addr via 'ip a'
Change-Id: I74e660548b2c44d5dbdb6023d5a36cfdd7e96f43
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
To be able to make EHL Ethernet GbE-TSN Controller configurable, a
driver is required. Functionality comes in following patches.
Change-Id: I7522914c56b74486bb088280d2686acf7027d1d3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Both option-HDMI and option-DP use the same setting of vbt,
and ABSENT is just physically remove option board from motherboard,
so it just need one vbt, and it don't need the fw_config to decide
which vbt will be return.
BUG=b:231769131
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I1f8cdcbc05ed3bc689d29261e4fd4d700326dce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Both option-HDMI and option-DP use the same setting of vbt,
and ABSENT is physically remove option board from motherboard,
so set default vbt has option-DP setting and only return it.
BUG=b:231769131
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I440143dabcf04c103f2a4420a7e4afb8ec12ec1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
New device id 0x51f1 is added.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I695309d529a117bad68fc89a7f136e69cecb95d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
CPUID_RAPTORLAKE_P_J0 is ES. Add it to generate is_es = 1 in ACPI
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib8d57f7fb0b3d15bc4bcdeae47bfbdde17e13118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Based on the public datasheet of NCT6686 which should be similar to
NCT6687D.
TEST=Enable serial for debugging on MSI PRO Z690-A WIFI DDR4 and see
coreboot console on the debug port
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I0e8744b5958af196de3de63de31852029d81436e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Starting with Meteor Lake SoC, the PCR/DMI interface to program GPMR
is replaced with IOC (I/O Cache), hence, this patch implements IOC
driver to support that migration.
Reference: 643504 MTL FAS section 7.5.2
TEST=Build and boot to OS for TGL RVP and MTL PSS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63198
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MP_IRQ flags can be used in the MP table and the ACPI MADT table.
Move them into acpi.h to avoid pulling in the full mpspec.h which is
only available on x86.
BUG=b:218874489, b:160595155
TEST=Build
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f1091b7629a6446fa399720b0270556a926401a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fast SPI controller (usually handling the boot NOR flash) is a
different controller type than the generic SPI controllers as it
provides access to the boot flash and usually is not used for generic
SPI slave connections.
Though there is common code for the fast SPI controller it currently do
not uses the PCI driver structure. This patch adds the PCI driver
envelope to the fast SPI driver and moves Apollo Lake as the first
platform to this driver.
Change-Id: I31bf39ec1c622db887dec9ca8623a7f282402849
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add Platform Secure Boot (PSB) enablement via the PSP if it is not
already enabled. Upon receiving psb command, PSP will program PSB fuses
as long as BIOS signing key token is valid.
Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is
only available with NDA customers.
Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use the existing definitions from FspUsb.h instead of magic values for
the ComboPhyStaticConfig settings in the mainboard's devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reka Norman