Commit Graph

39448 Commits

Author SHA1 Message Date
Tim Crawford e78e909180 src/drivers/smmstore: Fix SMMSTOREv1 clear command
The `clear` command for SMMSTORE version 1 does not require a parameter.

Change-Id: I992b7ce5962bf7ee62b7e1970ae7aa1b975ef42e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49724
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 11:04:04 +00:00
Kevin Chang 4ed4c2474b mb/google/volteer/variant/lindar: Enable SA GV setting
Allow MRC training in SA GV.

BUG=b:177779469
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Idc9f634135b489450f53f8cd28d80649309d0f70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-21 11:03:35 +00:00
Mathew King b35b823a59 mb/google/guybrush: Add default FMD file to the build
BUG=b:175143925
TEST=builds; binary has correct layout

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I4f3826c8ed0dfd7219eaa5f0cc285f1fe89a4e1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-21 11:03:26 +00:00
Kevin Chang 8583191e8a mb/google/volteer/variant/lindar: Configure USB2 port for type-c
Assigned USB2 port to type-c use.

BUG=b:177483060
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I9bd820406124927d56296508be05033217c0d472
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49638
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 11:03:18 +00:00
Frans Hendriks 6f468a58c1 ach/x86/postcar.c: Avoid double CBMEM initialization
On FSP1.1 platform cbmem_initiailze() is called in
chipset_teardown_car_main(). This causes double
call op cbmem_initialize().

Add call to cbmem_online() to avoid double CBMEM init.

BUG  = N/A
TEST = Build and boot on Facebook FBG1701

Change-Id: I449ddfc94f1099d7c0e9005e6a5cf509e1433bb1
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2021-01-21 11:03:04 +00:00
Frans Hendriks 162d704b57 drivers/intel/fsp1_1/temp_ram_exit.c: Initialize CBMEM
prog_locate() will load FSP, before CBMEM is initialized.
The vboot workbuffer is used for loading, but
CBMEM_ID_VBOOT_WORKBUF is not available.
A NULL pointer is returned as workbuffer resulting in error
'Ramstage was not loaded!' at second boot.

Initialize CBMEM before calling prog_locate().

BUG  = N/A
TEST = Build and boot on Facebook FBG1701

Change-Id: I2f04a326a95840937b71f6ad65a7c011268ec6d6
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-21 11:02:43 +00:00
Michal Suchanek be5cc7da5f msrtool: fix build with gcc 10.
[   84s] /usr/lib/gcc/i586-suse-linux/10/../../../../i586-suse-linux/bin/ld: msrutils.o:(.bss+0x0): multiple definition of `PresentTypes'; msrtool.o:(.bss+0x14): first defined here
[   84s] /usr/lib/gcc/i586-suse-linux/10/../../../../i586-suse-linux/bin/ld: msrutils.o:(.bss+0x4): multiple definition of `MsrTypes'; msrtool.o:(.bss+0x18): first defined here

There should be typedefs, not variable definitions.

Change-Id: I663a011e9f1fc169126570d5eac7abe82d204a90
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2021-01-21 11:02:01 +00:00
Kyösti Mälkki e05f81a3e0 soc/intel/quark: Add pwrs in <soc/nvs.h>
For the time being every soc/intel selects ACPI_SOC_NVS
and pwrs is a required field for the common initialisation
implementation of followup work.

Change-Id: I4a0c7eb35f0646898e49fad15c6448607c398731
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49493
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 11:01:23 +00:00
Jeremy Soller 98d580b8fb soc/intel/cannonlake: Allow RP#1 usage for ClkSrc
0 is converted to not used, so use a special value to allow using PCIe
root port #1.

Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-21 11:01:08 +00:00
Furquan Shaikh 3b6b9c7b78 soc/intel/common/pcie_rp.h: Fix comment style
This change updates pcie_rp.h to reflow the comment blocks to fit
within 80 columns to match the original style of the file. This
addresses comment received on
CB:49370 (https://review.coreboot.org/c/coreboot/+/49370/comment/0f3fe10d_4e218b5f/).

Change-Id: I565ad602e0e3a2ee09e8345479d82e2ce0a31fd0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-21 11:00:54 +00:00
Elyes HAOUAS 985821c4f2 cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE
Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE".
It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets
should have at least 256K L2 cache. That is plenty for XIP RO cache of
bootblock + romstage and a 32K CAR.

Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-01-21 09:08:14 +00:00
Stanley Wu 083702c32e mb/google/dedede/var/boten: Update gpio config for boten
Correct GPIO settings as below reason:
1. GPP_G7 not being used but set to NF.
2. GPP_C22 and GPP_C23 is set to NC but internal pull down to 20K

BUG=b:177283756
BRANCH=dedede
TEST=emerge-dedede coreboot chromeos-bootimage and boot into emmc

Change-Id: Idf25674efa2336bde98c5abaff278484fd71ea8b
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-21 05:09:38 +00:00
Stanley Wu 375d460f5f mb/google/dedede/var/boten: Replace generic driver with sx9324 driver
Replace i2c driver for the SX9324 proximity detector device.
This is first draft settings, will modify it after fine tuning.

BUG=b:175932166
BRANCH=dedede
TEST=run "i2cdump -y -f 15 0x28" to confirm  registers as except.
     un-approach:
       => register address: 0x01 value: 0x00
     approach:
       => register address: 0x01 value: 0x02

Change-Id: I0c8b5948266a07092799c6db556383fa08b924e6
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-21 05:09:07 +00:00
Stanley Wu 68d19f83c3 mb/google/dedede/var/boten: Update gpio setting
Correct GPIO settings as below reason:
1. GPP_D19/GPP_D20/GPP_D21 not being used but set to NF.
2. GPP_B7 should configure as WWAN SAR detect ODL, but set to NC

BUG=b:175932166
BRANCH=dedede
TEST=emerge-dedede coreboot chromeos-bootimage and boot into emmc

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Id7780d5332551ed3fd20ef14f8b5d31164f16385
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-21 05:08:54 +00:00
Subrata Banik 34e84b5858 mb/intel/adlrvp: Add PRESERVE to UNIFIED_MRC_CACHE
This patch preserves MRC training data across FW update.

Change-Id: I6b7273471e4fc9dc25eac80904e012f86a981836
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49681
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 03:29:30 +00:00
Subrata Banik 55bdaa98e2 mb/intel/adlrvp: Remove redundant HAS_RECOVERY_MRC_CACHE Kconfig
HAS_RECOVERY_MRC_CACHE is already part of CHROMEOS hence remove
redundant Kconfig.

Change-Id: Ia55b587d77ca5be2a8ae701a3ab95cfebe8627db
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-21 03:29:17 +00:00
Subrata Banik d74cd60b81 soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD
Make IGD disable when mainboard user selects SOC_INTEL_DISABLE_IGD.

TEST=Able to get depthcharge pre-OS splash screen with AMD Radeon RX
5700 PCI-E DGPU when mainboard user selects SOC_INTEL_DISABLE_IGD.

Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-21 03:28:56 +00:00
Subrata Banik 0591348833 soc/intel/common/graphics: Add new Kconfig SOC_INTEL_DISABLE_IGD
This SOC_INTEL_DISABLE_IGD Kconfig will allow to skip IGD
initialization using FSP GOP and eventually disable the IGD.

TEST=Able to get depthcharge pre-OS splash screen when mainboard
user selects SOC_INTEL_DISABLE_IGD with below HW/FW/SW
configuration:

HW: ADLRVP + AMD Radeon RX 5700 PCI-E DGPU
FW: coreboot with depthcharge as payload for ADLRVP and OpRom for
AMD PCI-E DGPU
SW: Chrome OS RC10 release

Change-Id: I465541cb45c9022d53a5beb3fff1f80660c357c9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-21 03:28:33 +00:00
Felix Held cb9773443d soc/amd/cezanne/Kconfig: select IDT_IN_EVERY_STAGE
This adds interrupt handlers that end up calling x86_exception().

Change-Id: I3dce539b6f1ef300cf16f20224744a75100f60b8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-20 22:01:31 +00:00
Felix Held 740d62c9fd soc/amd/picasso/Kconfig: drop EHCI_BAR
Picasso doesn't have any EHCI controllers, so it can't support EHCI
debug, so there is no need to specify a MMIO address for the early EHCI
BAR configuration.

Change-Id: I5e904c160c68805a8606a8b2d1ab4fb6172066e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-20 22:00:11 +00:00
Felix Held 7dc74b2f6e soc/amd/picasso/Kconfig: drop HAVE_USBDEBUG_OPTIONS
Picasso doesn't have any EHCI controllers, so it can't support EHCI
debug.

Change-Id: I2dae22c0db294f5334d9796d90f432d6c8d304df
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-20 22:00:01 +00:00
Michael Niewöhner 953a26875b soc/intel: fix indentation in intelblocks/lpc_lib.h
Change-Id: I28be6091097f713472d5ca3b8b0921ee71238cf0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-01-20 18:46:07 +00:00
Michael Niewöhner 0d18da8627 mb/prodrive/hermes: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Change-Id: I5b99a66fb64683f3647ebff3ab01ceb52058f79c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-20 18:31:20 +00:00
Michael Niewöhner 71624cd94f soc/intel/*: drop broken LPC mmio code
The code for setting the LPC generic memory range uses an array of fixed
address ranges not needing explicit decoding, to decide if the address
needs to be written to the LGMR register. Most platforms only mistakenly
add the PCH reserved mmio range, that is not decoded generally,
effectively breaking the mechanism. Only APL uses the array correctly.

That code, in it's current state, does not work (except for APL) and
currently, there is not a single user. Thus, drop it before people start
using it.

Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-20 18:29:06 +00:00
Michael Niewöhner 2cbe3df2cd mb/google/poppy: do early pad configuration in early bootstage
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).

Change-Id: I795b8da3c5e1efb51c8fe4673f025839a1c630bc
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-01-20 18:26:13 +00:00
Michael Niewöhner 5413a77f34 mb/google/fizz: do early pad configuration in early bootstage
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).

Change-Id: I2f484d232a46214ff98168f41f96d56b047892e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-01-20 18:25:59 +00:00
Michael Niewöhner c8085e029a mb/google/eve: do early pad configuration in early bootstage
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).

Change-Id: I67bdd9a96928b77a9a178afea7dab03dc370312c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-01-20 18:25:49 +00:00
Michael Niewöhner 35808fdb08 mb/google/sarien: do early pad configuration in early bootstage
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).

Change-Id: I342b9217af0288a3b525e629aac791eb0f880442
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-01-20 18:25:36 +00:00
Elyes HAOUAS e0469b6ded soc/amd/picasso/mrc_cache.c: Remove unused <bootstate.h>
Change-Id: Ied235972d24276d7c88a2f50f192d69d24ae6e05
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-20 15:25:15 +00:00
Hsin-Hsiung Wang 2fc5976740 soc/mediatek/mt8192: pmic: unlock key protection before initial setting
We need to write some special values to key protection registers before
applying init_setting table and lp_setting table to PMIC. Otherwise,
those settings won't take effect.
After applying init_setting table and lp_setting table, we lock the
settings by writing zero to key protection registers.

Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205.

BUG=b:172636735
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I593d4e02bf0b62ac297957caf4ae1c1837f1f38d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-20 14:00:27 +00:00
Hsin-Hsiung Wang 8572e33e5c soc/mediatek/mt8192: pmic: add scp voltage initialization
Add scp voltage initialization.

BUG=none
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I68302715ae804fed11bb54f4dfc4e90cde5224df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-20 14:00:09 +00:00
Mario Scheithauer 92e4ed1702 mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs
Until now some FSP-S parameters were configured for Siemens APL
mainboards via the Binary Configuration Tool (BCT). For simplification,
the original APL FSP binary should now be used. For this purpose, the
corresponding FSP-S parameters are set via devicetree, respectively via
mainboard_silicon_init_params accordingly.

The following parameters are affected:
- Disable CPU power states (C-states)
- Set lowest Max Pkg Cstate - PkgC0C1
- Disable PCIe Hot Plug for all enabled RPs
- Disable PCIe Transmitter Half Swing for all RPs
- Disable PCIe Active State Power Management (ASPM) for all RPs
- Disable PCIe L1 Substates for all RPs

TEST:
- Compare old with new coreboot log on mc_apl5, found no differences
- Boot Linux v4.4 and check output of 'lspci'

Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-01-20 12:26:42 +00:00
Kyösti Mälkki 1bc061ee90 mb/foxconn,gigabyte: Drop GNVS lptp and fdcp
Change-Id: Iaa05c1162b2533957091c719ea43ffb8d004c5eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49275
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20 09:25:54 +00:00
Kyösti Mälkki cee844c957 mainboards: Drop GNVS cmap and cmbp
Functionality depends of CMAP and CMBP references inside board
specific ASL implementation. Only roda/rk9 and roda/rk886ex has
that.

Change-Id: I4da8292375cb589d67dc68496b1e81971bc2a61f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49274
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20 09:25:08 +00:00
Kyösti Mälkki 780e02d1a5 ACPI GNVS: Drop APIC, factor out MPEN
APIC was not referenced anywhere in ASL.

MPEN has references under boards:
getac/p470, roda/rk9, roda/rk886ex.

MPEN has reference also in Intel SpeedStep ASL.

Replace static MPEN with detection of multiple CPUs
installed.

Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-20 09:24:35 +00:00
Kyösti Mälkki c196246f75 ACPI GNVS: Drop most dev_count_cpu()
Only amd/picasso and amd/stoneyridge have reference to
PCNT and that could be replaced with acpigen.

Remove the PCNT name from GNVS OperationRegion elsewhere.

Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-20 09:22:59 +00:00
Julius Werner e1383d39d7 trogdor: Initialize BACKLIGHT_ENABLE to 0, only turn it on in payload
The BACKLIGHT_ENABLE pin on this board unfortunately defaults to a
pull-up on power on, meaning the backlight is immediately enabled. Best
we can do about that is to turn it off again early and wait until it is
actually correct in the panel power sequence to turn it back on.

Some panels want an explicit 80ms delay after training the eDP
connection before the backlight is turned on (this is probably just to
avoid temporary display artifacts, but whatever). We don't want to
busy-wait that extra time, so instead just delegate turning on that GPIO
to the payload (which is also in charge of the backlight PWM already).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id8dafbdcb40175fbc9205276eee698583b971873
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-01-19 23:43:47 +00:00
Arthur Heymans 4338ae3194 nb/intel/pineview/northbridge.c: Fix overlapping resources
Fixed resources should not overlap.

Change-Id: I166e0095ac0cc0dd8271a693bb452f505a1a9413
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19 23:05:22 +00:00
Arthur Heymans 95a1142019 nb/intel/pineview/northbridge.c: Improve readability
This cosmetic change does 2 things:
- change bitwise shifting to division
- Make the division by / KiB explicit for fixed legacy ranges like
  0xa0000.

Change-Id: Ia6c2ee29e37040ea9b11505e9888c7f6f8da78bc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19 23:05:05 +00:00
Arthur Heymans 15ef9b6513 nb/intel/i945/northbridge.c: Reserve upper part of lower memory
This memory is used for option roms and BIOS. This matches the ACPI
code.

Change-Id: I53dd4b967569889108352ca70086a12ce252e8e0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19 23:04:34 +00:00
Arthur Heymans a6e4afc1cb nb/intel/i945/northbridge.c: Improve readability
This cosmetic change does 2 things:
- change bitwise shifting to division
- Make the division by / KiB explicit for fixed legacy ranges like
  0xa0000-0xbffff.

Change-Id: I626989fa6625e0b3613a11e709c614d40a788b0e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19 23:03:52 +00:00
Felix Held e8ac16e7e9 3rdparty/blobs: advance submodule pointer
This pulls in the following changes:
* Drop geode_lx
* cpu/amd/model_fxx: Drop unused microcode
* cpu/amd/model_10xx: Drop unused microcode
* soc/mediatek/mt8192: Add dram.elf for DRAM full calibration
* soc/mediatek/mt8192: Add dpm binary
* soc/mediatek/mt8192: Add 4266Mbps flag for dpm & dram blob
* soc/mediatek/mt8192: add SPM firmware
* soc/mediatek/mt8192: Support 26M clock off in SPM
* soc/mediatek/mt8192: Add SSPM firmware
* soc/mediatek/mt8192: Add MCUPM firmware
* soc/mediatek/mt8192: Update MCUPM firmware
* soc/mediatek/mt8192: Support discrete DRAM modules
* mb/amd/majolica: Add APCB configuration files

Change-Id: I5c18349307421707fac71f392b785f3e2bef3acb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-19 23:02:52 +00:00
Arthur Heymans 839c98aa8d nb/intel/ironlake/northbridge.c: Fix overlapping resources
Fixed resources should not overlap.

Change-Id: I7a70f5475c1d701db2cb8cbea659bacf6d0c52ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19 22:53:16 +00:00
Arthur Heymans 6473473417 nb/intel/ironlake/northbridge.c: Improve readability
This cosmetic change does 2 things:
- change bitwise shifting to division
- Make the division by / KiB explicit for fixed legacy ranges like
  0xa0000-0xbffff.

Change-Id: If4e05f496abc05e06a944b244824376f3937a57b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19 22:52:30 +00:00
Patrick Georgi b68dbc47c4 mb/intel/strago: Disable Chrome EC build
Chrome EC dropped strago support, so we need to disable it here
before updating our Chrome EC submodule.

Change-Id: Ied8905e995fd040b981ce18e95e225ade496d23c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48216
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19 22:38:46 +00:00
Kyösti Mälkki 070d7a6c4b soc/amd: Drop unnecessary <soc/nvs.h> include
Change-Id: Ia27bc256376c61a7330196a5b4a331dd79386fb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-19 21:08:14 +00:00
Kyösti Mälkki f1b0935ec4 soc/amd/picasso,stoneyridge: Unify set_nvs_sws()
Change-Id: I673f038b4ce3c4141db128a65be71e7a242dfd28
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-19 21:07:57 +00:00
Kyösti Mälkki b64cdebd2d soc/amd/stoneyridge: Add struct chipset_state
Struct will be synced with picasso with followups.

Change-Id: I5f460cc3849bf1fad1f6da61169893488ccb2b40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48855
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19 21:07:08 +00:00
Zhuohao Lee f1e25b1e35 mb/google/volteer: select GOOGLE_SMBIOS_MAINBOARD_VERSION
In order to use the function smbios_mainboard_version()
to query the board revision from the EC.
we need to select GOOGLE_SMBIOS_MAINBOARD_VERSION.

BUG=b:177818769
TEST=1. emerge-volteer coreboot chromeos-bootimage
     2. flash the image to the device and check board rev
        by using command `dmidecode -t 1 | grep Version`

Change-Id: I2474ee03845356d0775f6da25274f696ad33f935
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-19 18:45:34 +00:00
Felix Held e697fd9ecb soc/amd/picasso: move HAVE_ACPI_TABLES from mainboards to SoC
The SoC code has in implicit dependency on this option, so select it in
the SoC code instead of the mainboard code.

Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-19 15:05:58 +00:00