Commit Graph

53084 Commits

Author SHA1 Message Date
Kapil Porwal 1fe5fcf30d drivers/soundwire/max98363: Support MAX98363 SoundWire device
The MAX98363 smart speaker amp can be connected over SoundWire and be
configured for mainboards to use:

- Data Port 0 and Bulk Register Access is not supported
- Data Port 1 is the 32bit data input for the speaker path

The data port and audio mode properties are filled out as best as
possible with the datasheet as a reference.

The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.

For example this device is connected to master link ID 2 and has strap
settings configuring it for unique ID 0.

chip drivers/soundwire/max98363
  register "desc" = ""Left Speaker Amp""
  device generic 2.0 on end
end

This driver was tested with the rex0 reference design by booting
and disassembling the runtime SSDT to ensure that the devices have the
expected address and properties.

Device (SW20)
{
  Name (_ADR, 0x000230019F836300)  // _ADR: Address
  Name (_DDN, "Left Speaker Amp")  // _DDN: DOS Device Name
  Method (_STA, 0, NotSerialized)  // _STA: Status
  {
    Return (0x0F)
  }

  Name (_DSD, Package ()
  {
    ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
    Package ()
    {
      Package () { "mipi-sdw-sw-interface-revision", 0x00010000 },
      [...]
      Package () { "mipi-sdw-source-port-list", Zero },
      Package () { "mipi-sdw-sink-port-list", 0x02 }
    },

    ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
    Package ()
    {
      Package () { "mipi-sdw-port-audio-mode-0", "MOD0" },
      Package () { "mipi-sdw-dp-1-sink-subproperties", "SNK1" }
    }
  })
  Name (MOD0, Package ()
  {
    ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
    Package ()
    {
      Package () { "mipi-sdw-audio-mode-bus-frequency-configs",
        Package () { 0x00927C00, ... }
      },
      Package () { "mipi-sdw-audio-mode-sampling-frequency-configs",
        Package () { 0x3E80, ... }
      },
      [...]
    }
  })
  Name (SNK1, Package ()
  {
    ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
    Package ()
    {
      Package () { "mipi-sdw-data-port-type", Zero },
      [...]
    },

    ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
    Package ()
    {
      Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }
    }
  })
}

BUG=b:269497731
TEST=Verified SSDT for SNDW in the OS

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ie56109d615759e3e5e32782c8782cb2f47014ec4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73278
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-25 21:21:40 +00:00
Jeremy Compostella 246b943056 soc/intel/mtl/acpi/xhci: Add clock gating support
Implement PS0 and PS3 methods to support xHCI clock gating in S0ix
suspend and resume.

BUG=b:283989367
TEST=S0iX test passed

Change-Id: Ia5b72b81fd1c0d0b7b90f8d9cbf6ef4aa9da9743
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25 21:19:53 +00:00
Felix Held aec951eb3a arch/x86/include/arch/pci_io_cfg: add IO port count & last port defines
The PCI config space access via IO ports uses two 32 bit IO ports.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie99b4f5fc01fb0405243ff108d813ee1a3d35e5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75408
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-25 20:54:00 +00:00
Elyes Haouas 9c599c8b30 crossgcc: Upgrade IASL from 20221020 to 20230331
Changes: https://acpica.org/node/202

Change-Id: I43fc180bd51ff7cb06a67619c8350d28b086bc90
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-25 20:18:36 +00:00
Pratikkumar Prajapati 20ce90154e soc/intel/meteorlake: Enable Key Locker
BUG=b:276988831
Platform=Rex
Test= inteltool -k
============= Dumping INTEL Key Locker status =============
Key Locker supported : YES
AESKL instructions enabled : YES
===========================================================

Also,
No S0ix issue seen, no impact on power just with this coreboot patch, no stability issue seen.

Boot time delta (using cbmem -t):

Without this CL:
963:returning from FspMultiPhaseSiInit 1,299,043 (98,480)

With this CL:
963:returning from FspMultiPhaseSiInit 1,324,659 (121,995)

Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I9919f44623972d7bbae4a9b886e1da4ac7879c98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71120
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25 15:18:12 +00:00
Arthur Heymans 1a903f9878 cpu/Kconfig: Remove MMX config option
Now -mno-mmx is statically set in arch/x86 so remove this option.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I0da7f9f1afb0c8ecae728c45591897ca1d4dfb11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-25 13:11:30 +00:00
Arthur Heymans 67d9518586 arch/x86: Don't allow hw floating point operations
Even though coreboot does not allow floating point operations some
compilers like clang generate code using hw floating point registers,
e.g. SSE %XMMx registers on 64bit code by default. Floating point
operations need to be enabled in hardware for this to work (CR4). Also
in SMM we explicitly need to save and restore floating point registers
for this reason. If we instruct the compiler to not generate code with
FPU ops, this simplifies our code as we can skip that step.

With clang this reduces the binary size a bit. For instance ramstage for
qemu/Q35 drops from 216600 bytes decompressed to 212768.

TEST: See that with x86_64 bit and clang coreboot reaches the payload
without setting the CR4_OSFXSR bit in CR4. Without this change it would
bootloop very early in the bootblock on Qemu Q35.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib8590c55e7aed1ece2aa23b8ea99463396435e11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75316
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-25 13:08:43 +00:00
Matt DeVillier 7dab99856d mb/google/skyrim/var/winterhold: Fix USB port register scope
Commit f99d6700 ("mb/google/skyrim/var/winterhold: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.

BUG=b:283778468
BRANCH=skyrim
TEST=build/boot winterhold, dump ACPI, verify unchanged

Change-Id: Ia9982fed0fe2093d787ee9506ac5bbadd6cc03f9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75389
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-25 13:04:40 +00:00
Matt DeVillier dcabf1bd97 mb/google/skyrim/var/markarth: Fix USB port register scope
Commit d81ee3f1 ("mb/google/skyrim/var/markarth: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.

BUG=b:283778468
BRANCH=skyrim
TEST=build/boot markarth, dump ACPI, verify unchanged

Change-Id: I5c1cd23c49b512f55e9e13b2164d30dfb7fb682d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75388
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-25 13:04:31 +00:00
Matt DeVillier 432cb4035e mb/google/skyrim/var/frostflow: Fix USB port register scope
Commit a539893c ("mb/google/skyrim/var/frostflow: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.

BUG=b:283778468
BRANCH=skyrim
TEST=build/boot frostflow, dump ACPI, verify unchanged

Change-Id: I3912fe1b7d3f2a07cb379928cd4f5d87100d3284
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75387
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-25 13:04:24 +00:00
Subrata Banik a193308fab soc/intel/meteorlake: Set SaGv work points as enum macro
This patch adds an enum macro to define the different SaGv work points.
The enum macro is named `sagv_wp_bitmap` and it has three values:

The goal is to choose the optimal SaGv work point for the target
platform after considering the two inputs as power consumption and performance. The first group is for workloads that require high performance, even if it means consuming more power. The second group
is for workloads that can tolerate lower performance, in order to save
power.

SAGV_POINTS_0_1: The highest power consumption, but also the highest
                 performance.
SAGV_POINTS_0_1_2: A lower power consumption than work point
                   SAGV_POINTS_0_1, but also a lower performance.
SAGV_POINTS_0_1_2_3: The lowest power consumption, but also the lowest
                     performance.

Set SaGv work points after reviewing the power and performance impact
with SaGv set to 1 (Enabled) and various considering various work points
between 0-3 being enabled.

BUG=b:267879107
TEST=Able to build google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4af0038f2799a458d1b006270068341f65d36609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75362
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-25 05:04:06 +00:00
Subrata Banik 90a825a7bc mb/google/rex: Enable SaGv
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be
able to train memory (DIMM) at different frequencies.

On all latest Intel based platforms SaGv is expected to be enabled
to support dynamic switching of memory operating frequency.

BUG=b:267879107
TEST=Able to verify SaGv is enabled with 3 work point (0, 1 and 2)
and MRC retraining takes around ~20ms extra compared to SaGv being
disabled.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic680bfeab4dd285c0d3916ba5e917cc12bae3284
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73534
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-25 05:03:32 +00:00
Subrata Banik 04abc869ae vc/intel/fsp/fsp20/meteorlake: Add `SaGvWpMask`
This patch adds `SaGvWpMask` UPD into the FSP header.
This information is required to set the SaGv work endpoint.

BUG=b:283746904
TEST=Able to build google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If39da58c927cc7b28b46063576f8e246ef9596d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75361
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-05-25 05:02:32 +00:00
Felix Singer 38453784d7 util/crossgcc: Add empty directory for tarballs
A directory for tarballs is needed in any case but it's created at build
time. However, in reproducible build environments the sources are
downloaded before the buildgcc scripts runs and the directory needs to
be created.

Thus, to simplify that, add an empty tarballs directory.

Change-Id: Id3b4bf918c93f10c145f580684e916a4f8bae3b1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-24 21:11:21 +00:00
Simon Zhou 3b82131c28 mb/google/Screebo: Enable AUX DC biasing on C0
SKU1A C0 has no redriver, so enable SBU muxing in the SoC.

BUG=b:283044004
BRANCH=none
TEST=Voltages are correct on the C0 and C1 AUX bias pins

Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba
Signed-off-by: mike <mike5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-24 18:28:03 +00:00
qinwentao 3afa593103 mb/google/rex/var/screebo: Add BT devicetree config
Enabling BT for screebo project

BUG=b:278169273
TEST=Check whether BT can connect to Bluetooth device

Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com>
Change-Id: I0ecd62abfbe751e1036948b1490844e7e63d7f0d
Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75352
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-24 18:27:18 +00:00
Zheng Bao 948c0b7947 amdfwtool: Set the minimum size of entry PSPL2 A/B
This is a PSP FW requirement.
This is only for recovery A/B without ISH header. That means only
Cezanne.

Change-Id: I62616d5a866f66fc71e6c0b31a23c62dc11cf3c6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-24 12:24:28 +00:00
Eric Lai 4f154a2dd3 mb/google/hades: Enable smbus in device tree
Hades uses the SODIMM, enable the smbus to see the SPD address for the
memory.

BUG=b:283138024
TEST=i2cdetect -l can see the smubs adapter.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3912a025afaf8388d04a4b08852a84d4a2a6bf06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75399
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-24 12:18:49 +00:00
Arthur Heymans 1e45295236 vc/amd/pi/amdlib.c: Use native coreboot code over compiler builtins
Compiler builtins depend on certain CPU features flags to be passed to
the compiler. This may have unwanted side effects as generating code
with FPU registers. Instead use native coreboot code.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4e92d103fa3a6c7a56e813a583b3262676969669
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-24 12:16:37 +00:00
Maximilian Brune 9d475bf6de libpayload/arch/x86: Update API handling of CBTABLE handoff
The payload API of coreboot described in
https://www.coreboot.org/Payload_API does not reflect the current
handoff mechanism to hand the coreboot tables off. Therefore the
arguments supplied by coreboot (cbtable) will currently never be parsed
correctly and libpayload has to search for the coreboot tables by
iterating through memory.

This patch removes the old payload API implementation and just takes the
coreboot table pointer from the first argument on the stack.

Tested: started prodrive/atlas with coreinfo payload

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I51fb0cfc81043cbfe3fc9c8ea0776add2d6a42b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74965
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-24 11:49:51 +00:00
Marx Wang 00d9107e02 soc/intel/meteorlake: Add CPU PortID for GPIO Community
Add CPU PortID for GPIO communities in order to calculate
IOM Aux Bias data correctly.

BUG=b:283044004
TEST=able to detect external display

Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: I79f27fb0b6bde0a4ce2466eaf707166a952fad81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-24 11:41:56 +00:00
Jan Samek 124c57a5c5 mb/siemens/mc_ehl1: Enable pi608gp I2C driver
Add devicetree and Kconfig entries to enable additional configuration
of the Pericom PI7C9X2G608GP PCIe switch on this board variant.

The amplitude is being adjusted to 425 mV and de-emphasis level to
6.0 mV.

BUG=none
TEST=Read out the PCIe config space values of the switch and check if
they match with the ones configured over SMBus.

Change-Id: I11459f0794278ad614aa6e16c56df1ad578fe2f8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-24 11:26:27 +00:00
Mario Scheithauer 04705bfc26 mb/siemens/mc_ehl4: Double payload size to 256 bytes for PCIe RP #2, #3
To improve the rate of data transfer for PCIe root port #2 (00:1c.1) and
root port #3 (00:1c.2) set the max payload size to 256 bytes for both
root ports.

Change-Id: I553f6cf090d799fbbaafb925646c6566d6951a86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75127
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-24 11:25:50 +00:00
Mario Scheithauer f5a48989b4 soc/intel/elkhartlake: Make PCIe root port max payload size configurable
The data payload size of PCIe root ports can be set to either 128
(default) or 256 bytes. A bigger payload size can improve PCIe data
throughput on the given port. FSP-S provides a parameter to configure
this value.

This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.

Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-24 11:25:24 +00:00
Dtrain Hsu a6d337badf mb/google/nissa/var/uldren: Add fw_config probe for touchscreen
Use fw_config to probe touchscreen.

BUG=b:283199751
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I5d8129b3af3aa09e5bc31160de82d9ef7af0dd59
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-24 11:24:44 +00:00
Johnny Lin b7dc12dc6c mb/intel/archercity_crb: Add EWL Hob processing for MRC error
Override the weak function mainboard_ewl_check() and select OCP_EWL.

Select IPMI_KCS_ROMSTAGE and IPMI_OCP for OCP IPMI commands which are
needed for OCP EWL driver, but they are Meta-specific BMC commands
and don't really work for AC, this change is just for a demonstration
with AC.

Note that FSP UPD promoteWarnings needs to be disabled so that
FSP won't block and can return to coreboot for EWL processing
when memory EWL type 3 error occurs.

Tested=On Intel AC, connected with a faulty DIMM can see
EWL type 3 error being generated and halted with coreboot log:
[DEBUG]  Number of EWL entries 3
[ERROR]  EWL type: 3 size:32 severity level:1
[ERROR]  Major Warning Code = 0x29, Minor Warning Code = 0x04,
[ERROR]  Major Checkpoint: 0xb7
[ERROR]  Minor Checkpoint: 0x74
[ERROR]  Socket 0
[ERROR]  Channel 4
[ERROR]  Dimm 0
[ERROR]  Rank 0
[ERROR]  IPMI: ipmi_get_board_config command failed (ret=3 resp=0xc1)
[DEBUG]  ipmi send memory training error
[DEBUG]  EWL type: 1 size:19 severity level:1
[DEBUG]  0x6392e968: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04
[DEBUG]  0x6392e978: 00 00 00
[DEBUG]  EWL type: 1 size:19 severity level:1
[DEBUG]  0x6392e97b: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04
[DEBUG]  0x6392e98b: 00 00 01
[EMERG]  Memory Training Error!

Change-Id: I4602ae356aa6e55ed0611b8ac9a206db127c297c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23 20:26:13 +00:00
Johnny Lin f89cd1cf43 drivers/ocp/ewl: Enforce MRC when there's EWL type3 error
If Fastboot is enabled, the next boot will skip MRC and won't be able
to detect MRC error via EWL and still continues booting. Enforce FSP
MRC training in the next boot.

Change-Id: I9dee0472f8e2602cecf88c6d00dec0bf02b9f7bd
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23 20:25:34 +00:00
Johnny Lin 3435f81ab7 soc/intel/xeon_sp: move and rename set_cmos_mrc_cold_boot_flag
1. Rename set_cmos_mrc_cold_boot_flag() to soc_set_mrc_cold_boot_flag
   in case a certain platform may not support this via CMOS data, and
   the function could in turn calls mainboard defined method in the
   future. Move the code into soc_util.c.

2. Remove redundant static get_system_memory_map() from cpx/romstage.c
   and call the soc_util.c one.

Change-Id: Ib7d9bed9092814658f4a0b1d6dcf3c7d79178048
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23 20:22:33 +00:00
Jeremy Soller 14d69d03b7 soc/intel/common: Add RPP-S PCI IDs
Add PCI IDs to support Raptor Point PCH.

Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2)
Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-23 20:21:39 +00:00
Matt DeVillier f99d6700f1 mb/google/skyrim/var/winterhold: Fix USB port ACPI generation
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:

ACPI BIOS error (bug): Could not resolve symbol \
  [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND

BUG=b:283778468
BRANCH=skyrim
TEST=untested, but same error/fix as frostflow variant.

Change-Id: Ic498afcc8b8e0224f344f405e2f1ef6184df1d6b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75340
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23 19:42:28 +00:00
Arthur Heymans bf282c2630 cpu/x86/smm_stub.S: Fix comment
The comment got stale because a few elements from the struct got
dropped.

Change-Id: I83469e24dfab82b9182accb549960dd06d81e02f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-23 19:16:23 +00:00
Arthur Heymans c532b83437 cpu/x86/smm_stub.S: Update comment
%ebp is used for the stack frame on which the fxrstor address is pushed.
entry64.inc does not trash it so that's fine.

Change-Id: If027437dccac9ad507ceb534c6aae77ea43bdfda
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68896
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-23 19:14:52 +00:00
Matt DeVillier d81ee3f1eb mb/google/skyrim/var/markarth: Fix USB port ACPI generation
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:

ACPI BIOS error (bug): Could not resolve symbol \
  [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND

BUG=b:283778468
BRANCH=skyrim
TEST=untested, but same error/fix as frostflow variant.

Change-Id: Ie40541ada508acfa5771ea800249b8a57b168e3b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75339
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23 19:01:57 +00:00
Matt DeVillier a539893cee mb/google/skyrim/var/frostflow: Fix USB port ACPI generation
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:

ACPI BIOS error (bug): Could not resolve symbol \
  [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND

BUG=b:283778468
BRANCH=skyrim
TEST=build/boot frostflow, verify error no longer present in dmesg.

Change-Id: I0b87af6b2c04f9354e6f394a8f987fa660e49134
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75338
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23 19:01:31 +00:00
Elyes Haouas cf993bd343 crossgcc: Upgrade LLVM version 15.0.7 to 16.0.4
Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-23 13:34:51 +00:00
Shon Wang 2c0960221d mb/google/nissa/var/yavilla: Generate LP5 RAM ID for K3KL6L60GM-MGCT
Generate the RAM ID for Samsung K3KL6L60GM-MGCT.

DRAM Part Name                 ID to assign
K3KL6L60GM-MGCT                6 (0110)

BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I05a2cd5f2235702dea8fd706349ebda6a9ffa2ef
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-23 13:14:52 +00:00
Srinidhi N Kaushik 7e2106627d src/vc/intel/fsp/fsp2_0/sapphirerapids_sp: Update Spr header files
This change updates Intel Copyright License for all header files
under Sapphirerapids dir

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ib04988194e5fe9515bea8620318eadff36f92181
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-23 08:43:17 +00:00
Sean Rhodes 34a63f3df0 mb/starlabs/starbook: Add ramtop to CMOS layout
Add `ramtop` to CMOS layout so SOC_INTEL_COMMON_BASECODE_RAMTOP
can be used.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23 08:26:13 +00:00
Angel Pons 6c42d14d45 nb/intel/haswell: Allow using Broadwell MRC.bin
This is needed to support 9-series PCH-H (e.g. Z97) and Broadwell
non-ULT CPUs (for which more magic is required).

Tested on Asrock Z97 Extreme6: Boots, but ME has to be disabled so that
the system remains on after 30 seconds. Apparently, something Broadwell
MRC.bin does results in the ME being unhappy, as there is no such issue
when not using MRC.bin at all (native RAM init). S3 resume is working.

Change-Id: I7b33660099fa75c5ad46aeeda17b1215729f96c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23 08:25:00 +00:00
Eran Mitrani 8a2c36467c mb/google/rex: Add FW_CONFIG and device for VPU
BUG=b:282912666
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Iee6a9026a4d210407350bfb7ecc8a058e7ff5c24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-23 06:03:54 +00:00
Eran Mitrani 78881e1006 mb/google/rex: Add FW_CONFIG for TOUCH over SPI
TEST=set the corresponding cbi bit, and saw SPI0 under sysfs
BUG=b:278783755

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I7099cde14cff90ad63e9164769f9913a8284a805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-23 06:03:18 +00:00
John Su a398b31108 mb/google/skyrim/var/markarth: Update DPTC and STT settings
According to Thermal table 0518, adjust DPTC and STT settings.

BRANCH=none
BUG=b:273636128
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Id1c1884eabc1ea58148270f39eaca836ccc3fb54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-05-23 02:03:52 +00:00
Konrad Adamczyk d6b4db159b util: Use common ARRAY_SIZE define
Remove duplicated definitions of ARRAY_SIZE macro across util/ dir.
Instead of duplicates, use the one from commonlib/bsd/helpers.h file.

BUG=b:231765496
TEST=make -C util/cbfstool; make -C util/cbmem;
     make -C util/intelmetool; make -C util/superiotool

Change-Id: I29b776586b4f0548d4026b2ac77095791fc9f3a3
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74474
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Grzegorz Bernacki
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 19:24:27 +00:00
Zheng Bao 9203f5ee85 mb/amd/majolica: Add default setting PSP_INIT_ESPI
The board needs this setting to boot.

Change-Id: I7f507c2478b63daf891430e95b008747b9b95a51
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-22 12:50:01 +00:00
Karthikeyan Ramasubramanian aa86e5f006 soc/amd/mendocino: Unmap hash table after usage
Earlier the entire SPI ROM is mapped at the start of verstage and then
unmapped at the end of verstage. With CB:74606, this behavior has
changed. So unmap the hash table CBFS file after usage.

BUG=b:240664755
TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and
suspend/resume cycles for 50 iterations each. Ensured that there is no
impact to boot time.

Change-Id: I5c605f8ba8bbd571b589b3cdf91e9cc71d711c1c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75092
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 12:49:27 +00:00
Karthikeyan Ramasubramanian 6f1b03b8f6 soc/amd/common/psp_verstage: Map/unmap boot device on need basis
Currently the SPI ROM is mapped completely when the boot device is
initialized. That mapping remains active throughout the execution time
of PSP verstage. Every 1 MiB of mapped SPI ROM region consumes 1 TLB
Slot in PSP for use during memory mapped or DMA access. With 16 MiB of
mapped SPI ROM + FCH devices + 4 reserved TLB slots, 31 out of 32 total
TLB slots is consumed. This leaves almost no scope for future expansion.
With upcoming programs possibly using 32 MiB SPI ROM, PSP will run out
of TLB slots to support 32 MiB.

Hence instead of mapping the entire SPI ROM upfront, get the SPI ROM SMN
address during the boot device initialization. Update the boot device
region operations to map and unmap the SPI flash with the desired offset
and size using the SVC call. Then anytime a memory mapped SPI ROM access
is performed: map the required area, read the data and immediately unmap
the area. There is no update required when using CCP DMA, since the
concerned SVC call performs mapping and unmapping of the required SPI
flash area implicitly.

With these changes, maximum of 8 slots(size of RO section) might get
used at any point in time during the PSP verstage execution.

BUG=b:240664755
TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and
suspend/resume cycles for 50 iterations each. Ensured that there is no
impact to boot time.

Change-Id: Icd44ea7b2a366e9269debcab4186d1fc71651db2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74606
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 12:49:06 +00:00
Shelly Chang e17fc5dc0b drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error
Add sending Meta's BMC SEL for memory training error occurred in EWL
type 3 error.

The detail definition of EWL (Enhanced Warning Log) can be found in the
specification document -- BIOS Data ACPI Table (BDAT) Interface
Specification v4.0 Draft 5:
https://uefi.org/sites/default/files/resources/BDAT%20Specification%20v4.0%20Draft5_0.pdf

Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69147
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 12:47:33 +00:00
Tim Crawford 930dbc0d04 mb/system76/rpl: Add Gazelle 18
The Gazelle 18 (gaze18) is a Raptor Lake-H board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots
- M.2 NVMe SSD slot
- M.2 SATA SSD slot
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.6

Not working:

- Discrete/Hybrid graphics

Change-Id: I4599bf12c0f3048f9328f336cc8971400f5fd1a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-05-22 12:46:38 +00:00
Karthikeyan Ramasubramanian 2049bb9b2c soc/amd/common/psp_verstage: Always build unsigned PSP verstage
Currently unsigned PSP verstage binary is copied from ELF file only when
required in amdfw*.rom. If a signed PSP verstage binary is supplied
while building amdfw*.rom, then it is dropped. Copy the unsigned PSP
verstage binary always so that it can be used for signing directly from
the CI build infrastructure instead of a locally built binary.

BUG=None
TEST=Build Skyrim BIOS image and ensure that the unsigned PSP verstage
is part of the build artifacts.

Change-Id: If797dcfd20aa2991f3517904ef862406b9b9875c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75334
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 12:45:30 +00:00
Leo Chou 4d002f356e mb/google/nissa/var/pujjo: Add WWAN_5G power on sequence
Pujjoteen5 support WWAN 5G device, use variant.c to handle the
power on sequence.

BUG=b:279835626
TEST=Build and check WWAN 5G power on sequence.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I7dc72f2c705bcb41745f4bf08bef286773fe8b13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75327
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 12:44:58 +00:00