Commit Graph

39231 Commits

Author SHA1 Message Date
Nico Huber ec70383acc libpayload/lpgcc: Set proper include paths for in-tree builds
We only need `$_OBJ` in the include path for in-tree builds. Also,
curses only need special handling for those and PDCurses turned out
to need many more include paths.

Change-Id: Idd29ef33065033e26ba61b09d412d8ca3566d643
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-11 23:32:32 +00:00
Nico Huber 3e0b3f17af libpayload/lpgcc: Add more variables to support in-tree builds
Add $_DOTCONFIG and $_XCOMPILE pointing to the respective files and
use them.

Change-Id: I719b42d1c8abf055948daf5b000daa30cd249edd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-11 23:31:45 +00:00
Tony Huang 3b39cb98d4 mb/google/octopus: add audio codec into SSFC support for Meep
BUG=b:171757619
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.

Change-Id: I37390535e263b4b9547ad7307278e3360ba836bd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2021-01-11 22:50:14 +00:00
Renius Chen 43dec1ad4c drivers/genesyslogic/gl9763e: Fix boot on eMMC failed issue on Volteer
Booting on Kingston (EMMC64G-TA29/TX29-HP) and Hynix (H26M74002HMR) eMMC
currently fails due to R/W error. This is a workaround to finetune the
data latch timing by verdor-specific setting of GL9763E. For improving
the compatibility of GL9763E with these two eMMC.

Signed-off-by: Renius Chen <reniuschengl@gmail.com>
Change-Id: Iddb145ed6a9edb2d7a50248e64659cda78b88ae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-11 21:32:55 +00:00
Michael Niewöhner 8a6c34e8ba soc/intel/{icl,tgl,jsl,ehl}: add LPIT support
Add SLP_S0 residency register and enable LPIT support.

Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048
Reviewed-by: Lance Zhao
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 20:49:53 +00:00
Michael Niewöhner 11fae4ffe0 soc/intel/skl: add SLP_S0 residency register and enable LPIT support
Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1
      boots without crashing with an INTERNAL_POWER_ERROR.

Change-Id: Icccd9d15a9e9a22c9bfe7a9843e95d77013c9c8f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49047
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 20:49:43 +00:00
Michael Niewöhner 320a3ab7d2 soc/intel/cnl: add SLP_S0 residency register and enable LPIT support
Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1
      boots without crashing with an INTERNAL_POWER_ERROR.

- Windows and Linux tested on google/akemi
- Linux tested on clevo/cml-u

Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046
Tested-By: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49046
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 20:49:30 +00:00
Michael Niewöhner f0a44ae0eb acpi,soc/intel/common: add support for Intel Low Power Idle Table
Add support for the Intel LPIT table to support reading Low Power Idle
Residency counters by the OS. On platforms supporting S0ix sleep states
there can be two types of residencies:

  * CPU package PC10 residency counter (read from MSR via FFH interface)
  * PCH SLP_S0 assertion residency counter (read via memory mapped
    interface)

With presence of one or both of these counters in the LPIT table, Linux
dynamically adds the corresponding attributes to the cpuidle sysfs
interface, that can be used to read the residency timers:

  * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
  * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us

The code in src/acpi implements generic LPIT support. Each SoC or
platform has to implement `acpi_fill_lpit` to fill the table with
platform-specific LPI state entries. This is done in this change for
soc/intel/common, while being added as its own compilation unit, so SoCs
not yet using common acpi code (like Skylake) can use it, too.

Reference:
https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf

Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1
      boots without crashing with an INTERNAL_POWER_ERROR.

- Windows and Linux tested on google/akemi together with CB:49046
- Linux tested on clevo/cml-u, supermicro/x11ssmf together with CB:49046

Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-11 20:49:23 +00:00
Felix Singer d456f65056 {soc,vc,mb}/intel: Drop support for Cannon Lake SoC
Drop the support for the Intel Cannon Lake SoC for various reasons:

* Most people can't use coreboot on Cannon Lake, since the required FSP
binaries aren't publicly available. Given that FSP binaries for several
newer platforms have been released, it's very unlikely that Cannon Lake
FSP will ever be released.

* It seems there is no interest in this, since the reference mainboard
is the only available mainboard in tree.

Also, remove the related reference mainboard intel/cannonlake_rvp and
its FSP headers in intel/fsp2_0/cannonlake.

Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 17:23:53 +00:00
Wayne3_Wang 5569bddf66 mb/google/volteer: Add CSE Lite SKU support to Drobit
This will allow CSE RW FW updates and also fixes the problem where no sound is emitted from the speakers.

BUG=b:176536593
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: Wayne3_Wang <wayne3_wang@pegatron.corp-partner.google.com>
Change-Id: I69962a5b7c7c464280b35c834f7ee1c9b77db6fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49197
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 16:19:52 +00:00
Furquan Shaikh fceca9259b util/sconfig: Emit chip config pointers for PCI devices on root bus
This change emits chip config pointers for PCI devices on root bus in
static_devices.h so that the config structure can be accessed directly
without having to reference the device structure. This allows the
linker to optimize out unused parts of the device tree from early
stages like bootblock.

Change-Id: I1d42e926dbfae14b889ade6dda363d8607974cae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49214
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 07:42:28 +00:00
Furquan Shaikh 696f4ea0f5 soc/amd/cezzane: Add a minimal chipset tree
This change adds a minimal chipset tree with only two devices:
1. Domain
2. GNB root complex

This allows sconfig to generate the config structure for SoC root
device that is used by config_of_soc().

Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-01-11 07:42:12 +00:00
Furquan Shaikh 708f25e8fa util/sconfig: Change __pci*|__pnp* device pointers to const
This change updates the device pointers exposed in static_devices.h to
const instead of DEVTREE_CONST. The pointer itself doesn't really need
to be DEVTREE_CONST.

Change-Id: I061b05d994fc5c4156ee8bddabadf940f0aeeac3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-11 07:41:47 +00:00
Furquan Shaikh 582a0e2dbc soc/intel/common/uart: Use simple(_s_) variants of PCI functions
This change updates various uart_* functions to use simple(_s_)
variants of PCI functions. This is done for a few reasons:

* __SIMPLE_DEVICE__ check can be dropped since the same data type can
  be used in early stages and ramstage.
* Removes the requirement on early stage to walk the device tree to
  get access to the device structure. This allows linker-based device
  tree optimizations for early stages.

As part of this change, uart_get_device() is refactored and a new
function uart_console_get_devfn() is added which returns pci_devfn_t
in MMCONF format. It is then used directly by the _s_ variants of PCI
functions.

Change-Id: I344037828118572ae5eb27c82c496d5e7a508a53
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-11 07:41:35 +00:00
Furquan Shaikh 4fa183fe79 soc/intel/uart: Drop SoC callback `soc_uart_console_to_device`
This change renames `struct uart_gpio_pad_config` to `struct
uart_controller_config` and adds a new parameter devfn (which expects
devfn for the UART controller corresponding to the index in
PCI_DEVFN() format). This gets rid of the SoC callback to get `struct
device` pointer to the UART controller device.

Change-Id: Id0712a0038f2cc1a61b8b5a58fa155f14e7949a5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49212
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 07:41:22 +00:00
Jeremy Soller b1fa231d76 soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S
Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.

A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").

The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.

Tested by checking lspci output on System76 galp3-c (WHL), oryp5 (CFL),
and oryp6 (CML).

References:
- TigerLake FSP Integration Guide
- Intel Document Number 337868-002

Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49104
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 07:39:54 +00:00
John Zhao 3ba2c1a63e mb/google/volteer: Set FORCE_PWR low at boot time
While FORCE_PWR is set high, it prevents retimer from entering low power
state. S0ix failure occurs while USB4 Gatkex is connected on Port-0.
This change sets FORCE_PWR(GPP_H10) low. This FORCE_PWR GPIO will be
toggled by kernel through DSM method while updating retimer firmware.

BUG=b:174166586
Cq-Depend: chromium:2594438
TEST=Verifed s0ix cycles with USB4 Gatkex connected on Port-0.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-11 07:36:52 +00:00
Eric Lai c1befbe5d0 soc/amd/picasso: Separate GPIO define into gpio_defs.h
Separate GPIO define into gpio_defs.h, then we can use it in asl include.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If2a779eae228f621e77610889205853de2fb179a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-11 07:36:29 +00:00
Jonathan Zhang 5378219988 vc/intel/FSP2_0/CPX-SP: update to FSP ww01 release
With Intel CPX-SP FSP ww01 release, CidBitMap field is added to
DimmDevice struct in hob_memmap.h.

The copyright statements were updated to accomodate year 2021.

gpio_fsp.h is not needed any more as coreboot takes over GPIO
configuration.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3242c8b50401757a28de8a9e9c71fb95bc0515dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-11 07:36:10 +00:00
Srinidhi N Kaushik b3e5c2371d vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
Update v 3444 FSP headers for Tiger Lake platform to include the
below 2 UPDs to control TC cold support usb connect or not.
FSPS:
Usb3ComplModeEnable
DisableTccoldOnUsbConnected

BUG=b:173054070
TEST=Build and boot on delbin.

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I68b32730293fc83b5088074f71fa215220574748
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-11 07:35:27 +00:00
Patrick Rudolph 82e111cc2a mb/emulation/qemu: Copy page tables to DRAM in assembly
To work around various bugs running KVM enabled, copy page tables to
DRAM in assembly before jumping to x86_64 mode.

Tested on QEMU using KVM, no more stange bugs happen:
Tested on host
 - CPU Intel(R) Core(TM) i7-7700HQ
 - Linux 5.9
 - qemu 4.2.1
 Used to crash on emulating MMX instructions and failed to translate
 some addresses using the virtual MMU when running in long mode.

Tested on host
 - CPU AMD EPYC 7401P 24-Core Processor
 - Linux 5.4
 - qemu 4.2.1
 Used to crash on jumping to long mode.

Change-Id: Ic0bdd2bef7197edd2e7488a8efdeba7eb4ab0dd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-11 07:34:19 +00:00
Ren Kuo cbfe4ba76a mb/google/dedede/var/magolor: Remove the unused touch controller
Remove unused touch controller - Goodix

BUG=None
BRANCH=dedede
TEST=build firmware

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I2a01666bc1e353e21ddf961a0eb721a0cb4013db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49221
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 07:33:40 +00:00
Patrick Rudolph 7c8de869a2 soc/intel/cannonlake: Enable wake from USB in S4
The xHCI controller supports waking the system from S1-S4.
Thus specify that the deepest sleep state is S4 in _PRW.

Tested on Prodrive/hermes. The board now wakes from S4 as well by
pressing a key on the USB keyboard.

Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49224
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 07:33:13 +00:00
Angel Pons a93cb11ed6 nb/intel/gm45: Guard macro parameters
Add brackets around the parameters to avoid operation order problems.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I023bb116fa2bdcaa7cfdce2445513da3959e827d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45435
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 23:03:33 +00:00
Angel Pons 08ba81b6e4 nb/intel/gm45: Guard `CxDRBy_BOUND_SHIFT` macro parameters
Wrap `r` in parentheses to avoid unexpected behavior with compound
expressions. This prevents `CxDRBy_BOUND_MB(r+1, base)` from triggering
undefined behavior when `r = 2`, as the shift would be greater than 32.

Change-Id: I14235b2708ab502d842da677451c14203a469b45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49261
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 23:03:17 +00:00
Subrata Banik af03936679 device: Add new Kconfig VGA_ROM_RUN_DEFAULT for mainboard user
Platform can now select VGA_ROM_RUN_DEFAULT Kconfig to perform graphics
initialization for PCI-E based discrete card through VGA OpRom
(SoC or Mainboard user can't select VGA_ROM_RUN directly because
it's part of choice option).

(Note: Some payloads, like SeaBIOS, are also able to run Option ROMs,
so coreboot does not need to enable VGA_ROM_RUN Kconfig)

For payload like depthcharge, create VGA_ROM_RUN_DEFAULT Kconfig
for mainboard to select design with DGPU where OpROM is embedded
inside the DGPU card.

Allow auto selection of VGA_ROM_RUN_DEFAULT from VGA_BIOS Kconfig.

Also NO_GFX_INIT Kconfig to avoid running VGA_ROM_RUN
by default in case SeaBIOS is used.

TEST=Able to get Pre-OS splash screen with AMD Radeon RX 5700 PCI-E
DGPU when mainboard user selects VGA_ROM_RUN_DEFAULT.

Change-Id: Iecb2fcdb105af449bc20ad727759cdef17d5e376
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49016
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 17:50:29 +00:00
Subrata Banik 26e0f3f30b mb/intel/adlrvp: Update GPIOs as per latest schematics
1. GPP_D8, GPP_H23 =>  Remove unused GPIOs
2. GPP_E18 .. GPP_E22 => Program the correct Native Functions for GPIO

Change-Id: Iedb1f8fbf5f96a9617b72ba1a6419e3fd4e331b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49260
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 17:49:54 +00:00
Subrata Banik 8c4aa15e91 mb/intel/adlrvp: Fix FW download failed for PEG 060, 010
Enable PCIE RP1 to fix DEKEL FW download failed for x4
controller (PEG 0:6:0).

Enable PCIE RP3 to fix HSPHY FW download failed for x8
controller (PEG 0:1:0)

BUG=b:176940923
TEST=No FSP error seen while loading DEKEL, HSPHY FW.

Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-10 17:49:27 +00:00
Subrata Banik 85144d9002 soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb

RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2

Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 17:49:19 +00:00
Angel Pons 9a1b720b1f soc/intel/broadwell: Use `mp_cpu_bus_init`
This is needed to allow switching to Haswell CPU code in the future.

Change-Id: Ic642f32f9c4a269a66ac470b7a7217f20ff8bfba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46886
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 16:11:32 +00:00
Nico Huber 03d9298490 superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA
There were several default values given for GPIO data and status
registers. As all GPIO are configured as inputs by default, we
can't predict the values of these registers, hence set their
default values to NANA.

Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Clay Daniels <clay.daniels.jr@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-10 15:49:24 +00:00
Angel Pons 15e5e51461 cpu/intel/haswell/haswell.h: Align with Broadwell
Sort MSR definitions, move MCHBAR registers to northbridge and relocate
C-state latency macros into the header.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46914
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 15:43:10 +00:00
Angel Pons 4c95f10232 cpu/intel/haswell: Align cosmetics with Broadwell
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I3eb522a48edf9e8fc7664141253ae4e2072d71fa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46913
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 15:43:03 +00:00
Angel Pons 829fb2e985 cpu/intel/haswell: Do not determine CPU type at runtime
It is already known at compile-time.

Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46912
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 15:42:17 +00:00
Angel Pons 78c45bd3ef sb/intel/bd82x6x: Use `PCH_LPC_DEV` macro
Change-Id: I681bb126546b5a7bda3f1bac05c345d2cf60b178
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-01-10 15:42:05 +00:00
Kyösti Mälkki 732eaf20c3 util/autoport: Rename to mainboard_fill_gnvs()
Change-Id: Ia8d7083ca2f21abbb5f184c1b55dcf1bf047a7be
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-10 11:42:30 +00:00
Kyösti Mälkki 388c16a7e8 mb/google/cyan: Move board_id() to mainboard_fill_gnvs()
Only a google/cyan variant evalutes BDID in ASL.

Change-Id: I3d839333333b4762ae5350734c85471a3c12838a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49003
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:41:32 +00:00
Kyösti Mälkki 98323cd222 ACPI: Add missing include in nvs.h
Change-Id: Ic779a668ebaa4f0c9bdef95fd6de8f0179e8a534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49004
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:40:45 +00:00
Kyösti Mälkki c2b0a4fa32 soc/intel: Rename to soc_fill_gnvs()
Replace acpi_create_gnvs() under soc/ to reflect their
changed funcionality.

Change-Id: I7bdbe0d6f795252e713e9785ada2b6320e6604b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48717
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:40:22 +00:00
Kyösti Mälkki 999e441338 soc/intel: Replace acpi_init_gnvs()
Rename these to soc_fill_gnvs() and move the callsite away
from mb/.

Change-Id: I760c36f65c6122103f2be98fc11ee13832c2772e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48716
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:39:28 +00:00
Kyösti Mälkki a9766c7ada mb/x/acpi_tables: Rename to mainboard_fill_gnvs()
Rename acpi_create_gnvs() functions under mb/ to reflect
their changed functionality.

Remove now empty mb/acpi_tables.c files.

Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:29:10 +00:00
Kyösti Mälkki 8a5f157fdf sb/intel: Use acpi_inject_nvsa()
Change-Id: I5f1762c4a25631af9d29a2cb038620d9e9698f8b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48715
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:27:40 +00:00
Kyösti Mälkki 4b4e995988 sb/intel: Factor out soc_fill_gnvs()
Name the common part of GNVS initialisation as soc_fill_gnvs().
It is also moved before the call to acpi_create_gnvs(), which
followup will rename to mainbord_fill_gnvs() to reflect that
implementation is under mb/.

Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48706
Reviewed-by: Lance Zhao
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:27:06 +00:00
Kyösti Mälkki 9f441dfc70 ACPI: Replace uses of CBMEM_ID_ACPI_GNVS
Change-Id: I45a2d9cb7f07609a1ff03fd70f17c3f2d4f013b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48705
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:25:12 +00:00
Kyösti Mälkki 46e37c6343 soc/intel/braswell: Refactor acpi_init_gnvs()
Move GNVS details to different function, called
from acpi_create_gnvs().

Change-Id: Ief02c078fe37753c0d29418394a351105a1aacc8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48704
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:23:07 +00:00
Kyösti Mälkki 82f6b932e9 mb/x/acpi_tables: Move EC_RW detection
These boards without ChromeEC do not set ACTIVE_EC_RW
flag as part of the gnvs_assign_chromeos() function.
Create abstraction to avoid <vendorcode/chromeos/x> include.

Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:18:05 +00:00
Kyösti Mälkki d77b5e9f99 ACPI: Drop redundant ChromeOS setup for GNVS
Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.

Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:16:55 +00:00
Kyösti Mälkki 81b8472237 ACPI: Drop redundant CONSOLE_CBMEM setup in GNVS
Already done from common gnvs_get_or_create() implementation
after gnvs_cbmc_ptr() is defined.

Change-Id: I77c292cd9590d7fc54d8b21ea62717a2d77e5ba4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48702
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:16:26 +00:00
Kyösti Mälkki 3139c8dc05 ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocations
Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.

Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:15:10 +00:00
Felix Singer fb777b5da8 mb/google/parrot: Replace while-loop with do-while
Fixes linter error complaining about trailing semicolon.

Change-Id: I3f74f25cb2e3edcdd509abd86d80098241c05741
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09 16:31:29 +00:00