Commit Graph

19711 Commits

Author SHA1 Message Date
Kyösti Mälkki b84c833bfd intel/sandybridge: Use postcar_frame for MTRR setup
Adapt implementation from skylake.

Change-Id: Ica3134a2261d3e84c714264cf75557322f9ef5db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 23:54:14 +01:00
Aaron Durbin eb9c639a1b mainboard/google/reef: fill in NHLT ACPI OEM header fields
Fill in the NHLT ACPI OEM header fields to differentiate
different audio solutions on a per board basis. This handles
boards that share a firmware that are differentiated by
the SKU id and boards that have their own firmware. For the
latter, the Oem Table ID uses the VARIANT_DIR to differentiate.
"reef" is always used for Oem ID which is treated as more of
family in this case.

iasl -d shows the following on reef:
[00Ah 0010   6]                       Oem ID : "reef"
[010h 0016   8]                 Oem Table ID : "reef"
[018h 0024   4]                 Oem Revision : 00000008

BUG=chrome-os-partner:60494
BRANCH=reef

Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17772
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-09 17:26:54 +01:00
Aaron Durbin 2b3a6bee77 mainboard/google/reef: add board SKU'ing support
There are 2 gpios on reef-like boards that can be composed
into a SKU. Add support for identifying the SKU value using
the base 3 gpio logic. Also export the SKU information to the
SMBIOS type 1 table.

BUG=chrome-os-partner:59887,chrome-os-partner:60494
BRANCH=reef

Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17771
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-09 17:26:29 +01:00
Martin Roth 26174c97fe abuild: Build saved config files
Update abuild to allow for building saved miniconfig files.

If one or more config files exist for a platform under
coreboot/configs, they will be built instead of the automatically
generated default config.

The config filename needs to start with "config.$VENDOR_$BOARD" to be
picked up by the abuild script.

- Update to version 0.10.0
- Add -d parameter to specify the saved config file directory
- Break 2nd half of create_config function into update_config
to set the payload for saved config files.
- Unset new payload Kconfig options that could be set in a saved
config file.
- Update a bunch of MAINBOARD variable names to BUILD_NAME since
the build name isn't necessarily the same as the mainboard name.
- Split build_target into two functions - build_target and
build_config because one mainboard can now build multiple
configurations.
- Update remove target and call it directly from build_target()
instead of from build_targets()

Change-Id: I1a276d3e507b178f7dcd9dc125fa9c59f1ab47bd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17590
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-09 00:36:08 +01:00
Martin Roth c01ff74a6a util/kconfig/conf.c: Fix newline in error printf
For some reason the \n in the defconfig save error was not escaped.

Change-Id: I6a76b258f461a194fe17aae2b4fa04326b46d8d6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17742
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-12-09 00:35:51 +01:00
Martin Roth 21c99af0c8 util/lint: Add check to verify saved configs are miniconfigs
Change-Id: Ifc5ec645dd27663c1b1fde9ff16d48534606a554
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17600
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2016-12-09 00:35:16 +01:00
Martin Roth 7a128cb9c3 configs: Add some sample default configuration files
Test some config options that don't typically get tested.

Change-Id: Ie05c99411c8ce6462a6f5502b086ee2b72a4324b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17591
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-09 00:34:50 +01:00
Duncan Laurie 57dcf55538 google/eve: Add ASL code to describe SPI FPC1020 controller
There is ongoing work to link SPI bus and devices in to the devicetree
so this can be generated, but for now put in the raw ASL code to
describe this controller so it can be used by the factory.

BUG=chrome-os-partner:55538
TEST=successfully load fpc1020 kernel module on eve board

Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17776
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:23:38 +01:00
Andrey Petrov a697c19640 soc/intel/apollolake: Move privilege drop to later stage
Previously privilege drop was happening "too early" and that caused some
PMC IPC programming (performed in FSP) to fail because sideband was
already locked out. This change set moves privilege drop to later stage,
after last FSP notify call.

BRANCH=reef
BUG=chrome-os-partner:60657
TEST=iotools rdmsr X 0x121, make sure they can't be read.
Also dmesg|grep -i IPC to make sure there are no errors related

Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17769
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 21:40:31 +01:00
Aaron Durbin b21e362e93 cpu/x86: allow AP callbacks after MP init
There are circumstances where the APs need to run a piece of
code later in the boot flow. The current MP init just parks
the APs after MP init is completed so there's not an opportunity
to target running a piece of code on all the APs at a later time.
Therefore, provide an option, PARALLEL_MP_AP_WORK, that allows
the APs to perform callbacks.

BUG=chrome-os-partner:60657
BRANCH=reef

Change-Id: I849ecfdd6641dd9424943e246317cd1996ef1ba6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17745
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2016-12-08 21:39:43 +01:00
Aaron Durbin 16bd2676ce bootstate: add arch specific hook at coreboot exit
The bootstate machine allows one to schedule work at the
boundaries of each state. However, there are no priorities by
design. As such if there are things that need to be performed
that are interdependent between callbacks there's no way to
do that aside from explicitly putting the call in one of the
callbacks.

This situation arises around BS_OS_RESUME, BS_PAYLOAD_LOAD,
and BS_PAYLOAD_BOOT as those are the states where coreboot is
about to exit. As such, provide an architecture specific hook
at these key places so that one is guaranteed any work done
in arch_bootstate_coreboot_exit() is after all callbacks in
the state machine.

BUG=chrome-os-partner:60657
BRANCH=reef

Change-Id: Icb4afb341ab15af0670501b9d21799e564fb32c6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17767
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-08 21:38:48 +01:00
Kyösti Mälkki 530f677cdc buildsystem: Drop explicit (k)config.h includes
We have kconfig.h auto-included and it pulls config.h too.

Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17655
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-12-08 19:46:53 +01:00
Sumeet Pawnikar 3ec149dd7e mainboard/google/reef: Set PL2 override to 15000mW
This patch sets PL2 override value to 15W in RAPL registers.

BUG=chrome-os-partner:60535
TEST=Built, booted on reef and verified PL2 value.

Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17730
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 16:13:38 +01:00
Sumeet Pawnikar 428f90afe7 soc/intel/apollolake: Set PL2 in RAPL register
This patch sets the package power limit (PL2) value
in RAPL register.

BUG=chrome-os-partner:60535
TEST=Built, booted on reef and verified PL2 value.

Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17699
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 16:13:23 +01:00
Aaron Durbin 256db40b14 commonlib: provide incoherent region device
The MRC cache uses an incoherent mechanism for updating the
cache contents in that it assumes memory mapped boot device
access for checking against latest data for update. However,
it uses another driver for updating the underlying storage
area.

In order to aid in moving the MRC cache over to using
region_devices for updates provide an implementation of
a region_device which performs reads and writes to different
region_devices so that different drivers can be used
transparently.

BUG=chrome-os-partner:56151

Change-Id: I30e858245c30cbccd6313aff5ebecd3fd98d7302
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17716
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-08 16:11:41 +01:00
Aaron Durbin 305c0cafaa drivers/spi: provide a mechanism to obtain the SPI flash boot device
The MRC cache wants to be able to access the SPI flash boot device.
Allow an easy way to provide that so that there isn't duplicate
spi_flash objects representing the same device.

BUG=chrome-os-partner:56151

Change-Id: Iba92e8bb8a6060cdd327b10f5f8ec23ac61101e7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17715
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-08 16:11:01 +01:00
Aaron Durbin cd0bc987be lib: add region file support
The region file library is added to provide the underpinnings for
other libraries that support appending updates when the data changes.
The most recent written data is deemed the latest data associated
with that "file". A good example is the MRC cache which in a follow-up
patch utilizes this library.

BUG=chrome-os-partner:56151

Change-Id: Ic3caf1edbb6f11dbbe27181a87b7b19d1224fffa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17713
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-08 16:10:28 +01:00
Aaron Durbin 30c64be4ce lib/compute_ip_checksum: mark data buffer as const
compute_ip_checksum() doesn't manipulate the data it is passed.
Therefore, mark it as const.

BUG=chrome-os-partner:56151

Change-Id: I54cff9695a886bacd6314aa441d96aaa7a991101
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17714
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-08 16:09:59 +01:00
Matt DeVillier 7c6951b059 google/beltino, tidus: simplify led_power_on() function
Simplify set_power_led() by consolidating switch and setting values
as needed inline based on LED state.  Remove unnecesary function
param, includes for Tidus.

Change-Id: I28e6fac5f8d7e2ff419002db714ce88697895faf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17744
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-08 14:25:31 +01:00
Damien Zammit f5dd23f954 drivers/r8168: Read default MAC address from CBFS
This driver applies to 10ec:8168

Previously, this driver resetted the nic and set a hardcoded
MAC address.  Now the driver reads a default MAC address
from CBFS in the form of a string:
echo -n "xx:xx:xx:xx:xx:xx" > macaddress
and store the macaddress file in CBFS with the same name.

TESTED on GA-G41M-ES2L and GA-945GCM-S2L:
       MAC address was detected

Change-Id: If1af91120fa3efca3f1406334a83ed1e59fbdaf9
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17672
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-08 12:40:46 +01:00
Nico Huber d1e2edf708 libpayload: Add Cougar Point PCH's AHCI to whitelist
Change-Id: Ie8ca342a32323be4c26c236a5209052ec724317f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17353
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-08 01:36:01 +01:00
Dennis Wassenberg bd202bcdf3 nb/intel/sandybridge: Lock PAVPC
This makes CHIPSEC happy. We don't enable PAVP, but it shouldn't hurt
to lock it nevertheless.

Change-Id: I9428f0b6e8868832eb79f7aea24cbc7961c2aa8f
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: https://review.coreboot.org/17352
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-08 01:35:42 +01:00
Dennis Wassenberg 0c04720cb7 sb/intel/bd82x6x: Add TCO_Lock in finalize step
CHIPSEC found that the TCO_Lock was not set.
This is used to prevent changing the TCO_EN bit.

Change-Id: I42364dbef2511e656662566cf94591e76c6847ed
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: https://review.coreboot.org/17351
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-08 01:35:22 +01:00
Matt DeVillier f8960a6149 soc/broadwell: set EM4/EM5 registers based on cdclk
The EM4/EM5 registers in the mini-HD audio device must be set based
on the GPU cdclk value in order for HDMI audio to function properly.
Add variables to save the correct values when initializing the GPU,
and accessor functions to retrieve them in order to set the registers
when initializing the mini-HD audio device.

Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17718
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07 23:54:14 +01:00
Matt DeVillier 0b7c72c70c google/beltino: fix LED, simplify function for Tricky variant
Simplify set_power_led() by consolidating switch and setting values
as needed inline based on LED state.

Fix non-off LED polarity for Tricky using correct value from Chromium source

TEST: power on Tricky, observe LED lit / solid

Change-Id: I8bc7c4ae3f83d3f37b76fd5c90a4faed7057ebee
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17719
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-07 23:43:49 +01:00
Kyösti Mälkki 4015608ed7 autoport: Fix romstage generator
Prototype changed here:
   e258b9a intel sandy/ivy: Improve DIMM replacement detection

Change-Id: Id79238db2e497b9163f3bd1b1d5d4bc11fe4da9e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17711
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07 23:30:16 +01:00
Subrata Banik fe204fe902 src/device: Get device structure by path type
Add helper function to find a device by path type
in the device tree.

Change-Id: I8846f63bd2488788ea3c7ab5154e7cf431a252bc
Credits-to: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Dhaval V Sharma <dhaval.v.sharma@intel.com>
Reviewed-on: https://review.coreboot.org/17731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-12-07 22:55:20 +01:00
Furquan Shaikh d6c555971b soc/intel/apollolake: Use the new SPI driver interface
1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash controller
in different files.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully for reef.

Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17562
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-12-07 20:23:01 +01:00
Furquan Shaikh b5d41cb063 spi: Clean up SPI driver interface
1. Add new structure spi_ctrlr_buses that allows platform to define a
mapping from SPI controller to buses managed by the controller.
2. Provide weak implementations of spi_init and spi_setup_slave that
will be used by platforms using the new interface.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Change-Id: Ia6f47941b786299f4d823895898ffb1b36e02f73
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17561
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 20:19:07 +01:00
Furquan Shaikh 2dc8b77d0e soc/intel/skylake: Remove unwanted spi_release call
Skylake uses a special SPI Flash controller and does not require
spi_claim_bus and spi_release_bus functionality. This was a leftover
call from earlier cleanup, so remove it.

Change-Id: Iea260813cf72b94b7e7c661dbe494a74351dc357
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17729
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 20:16:06 +01:00
Subrata Banik 847da79383 soc/intel/skylake: Remove redundant BootLoaderTolumSize assignment
BootLoaderTolumSize FSP-M UPD is already initialized with cbmem_overhead_size()
inside driver/fsp2_0/memory_init.c, hence remove the duplicate assignment.

Change-Id: I0b1d9769cd2a863bf0547ce5f44928cacc5a63b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17721
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 20:15:22 +01:00
Paul Menzel 00563bf054 lib: Add time stamp when starting to finalize chips
Add the new time stamps *finalize chips* to track, when the method
`dev_finalize_chips()` is called, so that the real time of
`write_tables()` is known.

Change-Id: I65ca0ec4c07c2eaa14982989cb206d23d8a2293f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-12-07 20:14:25 +01:00
Nico Huber 5eef7b34c1 sio/ite/it8783ef: New super i/o chip
This will be used by new Roda boards. Four UARTs and PS/2 keyboard and
mouse are exposed to ACPI. Since our boards only use the environment
controller part, most of the usual pnp interfaces are untested.

Change-Id: Ifeb0327ad115759411716f82585ace5ce55b8464
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17287
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07 20:02:17 +01:00
Nico Huber 21707cc29d sio/acpi: Add more magic bytes to ENTER/EXIT_CONFIG_MODE
ITE super-i/o chips need a fourth byte and have a special register
to exit config mode.

Change-Id: Ic40873649d567b87d3a937f2bf068649e67715de
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07 20:01:50 +01:00
Nico Huber 6167365530 sio/ite/common: Export pnp_enter/exit_conf_state()
Change-Id: I8cbfe49516e685c1b3e150b23f9fcac513f1f3dc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17285
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07 20:00:57 +01:00
Furquan Shaikh 56c848cdc9 soc/mediatek/mt8173: Do not initialize static variables to 0
Change-Id: Ibf0bd772bfdb3bbf6482a0ec9ff90a5c0a8945d2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17765
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 17:15:56 +01:00
Kyösti Mälkki 48f82a9beb AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain
Device is of type CPU_CLUSTER, while pci_dev_set_resources()
expects PCI_DOMAIN.

Change-Id: Ib1add47d71071abb6e9c28e3a85dd0b671741b71
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17697
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 13:05:48 +01:00
Kyösti Mälkki 27198ac2e3 MMCONF_SUPPORT: Drop redundant logging
Resource is actually stored even before read_resources, but
that's where we currently log this resource.

For Intel, use PCI config register offset as the resource
index, while AMD side uses MSR address.

Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17696
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 13:04:58 +01:00
Kyösti Mälkki e25b5ef39f MMCONF_SUPPORT: Consolidate resource registration
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17695
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 13:00:56 +01:00
Kyösti Mälkki 3d15e10aef MMCONF_SUPPORT: Flip default to enabled
Also remove separate MMCONF_SUPPORT_DEFAULT flag.

Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17694
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 13:00:31 +01:00
Kyösti Mälkki 6f66f414a0 PCI ops: MMCONF_SUPPORT_DEFAULT is required
Doing PCI config operations via MMIO window by default is a
requirement, if supported by the platform. This means chipset
or CPU code must enable MMCONF operations early in bootblock
already, or before platform-specific romstage entry.

Platforms are allowed to have NO_MMCONF_SUPPORT only in the
case it is actually not implemented in the silicon.

Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17693
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 12:59:28 +01:00
Aaron Durbin 891b6c4d19 mainboard/google/reef: adjust chromeos.fmd regions
- Drastically reduced RW_MRC_CACHE size to hold one update. Now
  that this area isn't changing after every S5 entry there's no
  need make it so large.
- ELOG area reduced by 4KiB for subsequent area alignment. In practice
  this doesn't matter because the elog library only uses 4KiB bytes.
  16KiB->12KiB is a nop.
- Moved RW_NVRAM for subsequent alignment.
- Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries
  and sized to 64KiB multiples. This ensures updates don't need a
  read-modify-write that could force a system into recovery if
  an inopportune power event occurred.

BUG=chrome-os-partner:60492
BRANCH=reef

Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17727
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-07 07:19:37 +01:00
Nico Huber 26267a7a41 buildgcc: Be less restrictive when trying to build GNAT
It turned out that newer GNAT versions can build our current (5.3.0)
GNAT without bootstrapping. So adapt the version enforcement.

Change-Id: Ie7189e8bcadeee56cf5c2172e8c0ae7cd534685a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-06 23:56:38 +01:00
Nico Huber aa89fb4618 buildgcc: Fix function prototype in GCC
With some newer versions of GCC (experienced with GCC 6.2.1 on Arch-
Linux) the first stage of a boostrapping fails due to a mismatching
function prototype. Also add a missing `static` to the signature.

Change-Id: Ia927036ccd725550f1191890515578bc80c74f80
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-06 23:56:05 +01:00
Shasha Zhao c99526cce9 Bob: Update the memory ramid of bob
Update the memory ramid.
Move to one CA training pattern.

BUG=chrome-os-partner:59454
BRANCH=firmware-gru-8785.B
TEST=Build firmware passed

Change-Id: Ic05cbc1700a13e372f63d5202459add0e984f9d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1030a78af3d489d13508f17a79df1e65bd5afa3b
Original-Change-Id: Ibe8acb5b698cec1adcdddbb13d35a5e20a5b8c0d
Original-Reviewed-on: https://chromium-review.googlesource.com/414664
Original-Commit-Ready: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Change-Id: I0ae46e496cd18492a2b6c7167081798c2f2479b1
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411645
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17679
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06 22:15:45 +01:00
Shasha Zhao 6bd75ec942 Bob: add bob in coreboot
Add bob in coreboot and update as necessary.
1. Add bob HWID
2. Add supported memory source

BUG=chrome-os-partner:59454
BRANCH=firmware-gru-8785.B
TEST=Build firmware passed

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Change-Id: Iad03a293bdbbb89450f0fea0822e34a4be7064bf
Original-Commit-Id: bff788c71a43403bff2c23b38e69cc27fb869559
Original-Change-Id: I0dcf47eb911337b176f73759a2c70a9dbf4dc68b
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411083
Original-Reviewed-by: Philip Chen <philipchen@chromium.org>
Original-(cherry picked from commit c5925dfcf59ac755a26182744b2bde59e41a37cf)
Original-Reviewed-on: https://chromium-review.googlesource.com/413744
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17678
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06 21:56:34 +01:00
Lin Huang f00af5833a rockchip/rk3399: sdram: use register to calculate sdram sizes
We may support different sdram sizes on one board in future, so
we need to calculate sdram sizes from sdram drvier.

BRANCH=None
BUG=None
TEST=boot kevin

Change-Id: I43e8f164ecdb768c051464b4dbc7d890df8055d0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c4d8b3cb647b2f9cebc416c298817c16d49330e
Original-Change-Id: I95d5ef34de9d79ebca3600dc7a4b9e14449606ff
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411600
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17629
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06 21:56:20 +01:00
Julius Werner c49782cbe7 google/gru: Power-cycle USB ports in developer/recovery modes
Gru only uses USB 2.0 in firmware to avoid all the madness associated
with Type-C port orientation and USB 3.0 tuning. We do this by isolating
the SuperSpeed lines in the Type-C PHY so it looks like they aren't
connected to the device.

Unfortunately, some devices seem to already get "locked" into SuperSpeed
mode as soon as they detect Rx terminations once, and can never snap out
again on their own. Since the terminations are already connected during
power-on reset we cannot disable them fast enough to prevent this, and
the only solution we found to date is to power-cycle the whole USB port.

Now, Gru's USB port power is controlled by the EC, and unfortunately we
have no direct host command to control it. We do however have a command
to force a certain USB PD "role", and forcing our host into "sink" mode
makes it stop sourcing power to the port. So for lack of a saner
solution we'll use this to work around our problem.

BRANCH=gru
BUG=chrome-os-partner:59346
TEST=Booted Kevin in recovery mode, confirmed that my "problem stick"
gets detected immediately (whereas previously I had to unplug/replug
it). Booted Kevin to OS in both developer and normal mode and confirmed
that USB still seems to work.

Change-Id: Ib3cceba9baa170b13f01bd5c01bd413be5b441ba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cd695eda33299e50362f1096c46f2f5260c49036
Original-Change-Id: I2db3d6d3710d18a8b8030e94eb1ac2e931f22638
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/413031
Reviewed-on: https://review.coreboot.org/17628
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06 21:56:01 +01:00
Julius Werner ea79d2b3a3 google/chromeec: Add command to control USB PD role
Normally firmware should have no business messing with the USB PD role
(source/sink/whatever) in the EC. But, as so often happens, ugly issues
crop up that require weird work-arounds, and before you know it you need
to do this for some reason that only makes sense in context. I do now,
so add this function to send the necessary host command in the simplest
possible fashion.

BRANCH=gru
BUG=chrome-os-partner:59346
TEST=Used it in a follow-up patch.

Change-Id: I07d40feafd6a8387a633d6384efb205baf578d76
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8b71767caccff9b77d458182ce8066f7abf6321c
Original-Change-Id: Ie8d0be98f6b703f4db062fe2f728cd2588347202
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/413030
Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/17627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06 21:55:43 +01:00
Kyösti Mälkki 3a0cb458dc cpu/amd/mtrr.h: Drop excessive includes
Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17736
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06 20:55:11 +01:00