Ipq8064 SBLs initialize the hardware to prepare it to run an arbitrary
user provided bootloader. The only bootloader requirements imposed by
the SBLs are that it is concatenated with the SBL chunks in the
bootprm AND it uses MBN encapsulation (mostly to specify the size and
load address).
This patch adds configuration options to specify the location of the
SBL blobs and to require MBN encapsulation of the bootblock.
BRANCH=none
BUG=chrome-os-partner:27784
TEST=manual
- the below demonstrates added encapsulation, no code run attempts
have been made yet:
$ FEATURES=noclean emerge-storm coreboot
$ cd /build/storm/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999
$ \od -t x4 build/cbfs/fallback/bootblock.bin | head -3
0000000 00000005 00000003 00000000 2a010000
0000020 00000be0 00000be0 2a010be0 00000000
0000040 2a010be0 00000000 e32bf0df e59f0030
Original-Change-Id: Iae30ad08059e2b35c434ac25a410ac2017752957
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193511
(cherry picked from commit bf16ea915c723ab124d817e3b0d950282e3cf1c1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I53c71d382ec1d826f530d7afb545f64ec4eaf96b
Reviewed-on: http://review.coreboot.org/7261
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch switches every last part of Coreboot on ARM over to Thumb
mode: libpayload, the internal libgcc, and assorted assembly files. In
combination with the respective depthcharge patch, this will switch to
Thumb mode right after the entry point of the bootblock and not switch
back to ARM until the final assembly stub that jumps to the kernel.
The required changes to make this work include some new headers and
Makefile flags to handle assembly files (using the unified syntax and
the same helper macros as Linux), modifying our custom-written libgcc
code for 64-bit division to support Thumb (removing some stale old files
that were never really used for clarity), and flipping the general
CFLAGS to Thumb (some more cleanup there as well while I'm at it).
BUG=None
TEST=Snow and Nyan still boot.
Original-Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/182212
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a)
Conflicts:
payloads/libpayload/include/arm/arch/asm.h
src/arch/arm/Makefile.inc
src/arch/arm/armv7/Makefile.inc
*** There is an issue with what to do with ramstage-S-ccopts, and
*** will need to be covered in additional ARM cleanup patches.
Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/6930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The ccopts mechanism is needed for passing ARM assembler flags to GCC.
There are many gotchas in adding ASFLAGS. As things have moved
around, the revert doesn't remove cleanly, so this reverts and cleans
up the ccopts.
This reverts commit 25b56c3af5.
Change-Id: I44c025535258e6afb05a814123c10c24775a88e8
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7352
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
acpigen_patch_len doesn't really need its argument: length always includes
everything from length bytes to current pointer and never bytes before it.
Hence just infer all the info implicitly.
Argument is wrong in several places through the codebase but ACPI parsing
is lax enough to swallow incorrect SSDT. After this function is used throughout
the codebase, these issues will be fixed.
Change-Id: I9fa536a614c5595146a7a1cd71f2676d8a8d9c2f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7325
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Change-Id: I1cf87b3c73d8bf8846e5870b19b089f85c299567
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7241
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The sizeof on array function parameter will return size of 'u8 *'
instead of 'spd_raw_data' (aka 'u8 [256]' leading to an overflow.
Found-by: Clang
Change-Id: I78e113a640b2953c853eb43bd6874e4694260b1f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7353
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Just when you thought you found them all..
Reduces loc and makes NOP's explicit.
Change-Id: I416e0468b7f2f462c940daae695d67fb409aa4c6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7350
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reduces loc and makes NOP's explicit.
Change-Id: I8a117b150b8b421c7a18b48a2ac36d15679f20b0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7344
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
cpu/intel/romstage.h is needed so the the main() has a
prototype in freestanding.
Change-Id: I5e6afef82a4f63ab42927725adf3881084a1e25c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7235
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
The flags used to compile libgcc may make it incompatible with the code it's
linked against, and/or the hardware it's going to run on. Rather than try to
tease the right libgcc from the compiler, lets just leave it out and use our
own implementations of the necessary functions.
Most of these implementations were taken from the Linux kernel, except for
uldivmod.S which was taken from a CL originally written for U-Boot by
Che-Liang Chiou in December of 2010. It was modified to not use the CLZ
instruction on machines that don't have it, anything earlier than ARMv5. The
top block was taken from an earlier version of the same CL which didn't use
CLZ in that spot. The later block was written from scratch.
BUG=None
TEST=Built and booted into the bootblock on nyan. Ran a series of tests which
divided and modded a 64 bit value by various 32 bit values which were powers
of 2. Confirmed that this function was used and that the returned value was
correct. Printed decimal and hex versions of some values and verified that
they equaled each other. Built and booted on pit with serial enabled.
BRANCH=None
Original-Change-Id: I7527e28af411b7aa7f94579be95a6b352a91a224
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/172401
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit be8c7a8f3292a7d7651b7c6dafc9a2c53afbd402)
*** This second patch is cherry-picked and squashed again to
*** pick up the libgcc changes that were skipped previously.
arm: Move libgcc assembly macros to arch/asm.h
libgcc/macros.h contains some useful assembly macros that are common in
Linux kernel code and facilitate things such as unified ARM/THUMB
assembly. This patch moves it to a more general place where it can be
used by other code as well.
BUG=None
TEST=Snow still boots.
Original-Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/182178
Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit a780670def94a969829811fa8cf257f12b88f085)
*** Additional changes for stage specific builds
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie3e48f34ebf6fbe20c3dd76ecbcbea7844e9466e
Reviewed-on: http://review.coreboot.org/7322
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Do all the handling in SB code with few parameters from devicetree.cb
instead of having mobo callbacks.
Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7199
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Bring code inline to be consistent with the rest of coreboot.
See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase,
'expressions that refer to functions get converted to pointers to
those functions'
Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7290
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We already have these implemented under superio/common, use
those instead of this copy-paste syndrom.
Change-Id: I7c7737e0b3c284d8b14b36c70681ab2269bb1d4b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7310
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We don't want segment for .car.data section to be considered while elf_to_stage
transformation is being done. Thus, use -S option for add-stage.
Change-Id: I04868c892e3aa94113189b012d284d52bacea5f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/7305
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
That takes them out of .data
Change-Id: Idf88ddaacb2f78ba6a0260e3511b34edc269731d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7313
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Apply commit 283ba78415 to f12 (literally, plus one adaptation).
Change-Id: Ied7891806e269320caf968cae3de3dc792c5f8fd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7312
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Breaks abuild and is dependent on WIP, is WIP itself.
This reverts commit d7d0c81348.
Change-Id: I8b589b41632696aa4570abcceab5f3a3b0784649
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7319
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This is based on LENOVO X230 port. Board boots to linux via SATA.
Remaining Issues:
1. Native raminit sometimes fails with "timC write discovery failed"
even without changing the ram configuration.
I suggest altering the native raminit code so that it reboots
if that message appears to give a chance for the boot process to recover.
2. VGA does not work.
Native graphics initialization only supports LVDS and the
VGA Option ROM still hangs when run in SeaBIOS
3. USB does not work.
SeaBIOS/GRUB2 do not detect devices connected to USB ports
4. Sound needs corrected codec verb settings
Change-Id: Ib465a4824ef1a71ab6aa17bd40fc281215c6d44f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7020
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Super I/O manufactures have found new and innovative ways to enter
and exit out of LDN config in PNP config space.
Change-Id: Id3f5882664f1b2b18b49f32373430cf4b037ad22
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7308
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Rather than everyone writing their own adhoc device operation
NOP shim, we provide some formalism. We later make use of this
to reduce the loc count down trivially.
Change-Id: I2d04bfb50e76f367a0ee258dab97d7caa12ec99e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7283
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
On the ASRock E350M1 a Nuvoton NCT5572D is used as SuperIO-chip. The coreboot
port to this board however used the driver of the Winbond W83627HF SuperIO,
which is compatible enough to get most stuff working, but which clears bit 6 in
register 0x2B. This switches the function of pin 38 of the NCT5572D from
RSTOUT1# output to GP36. The PERST# pin of the ethernet chip and the
unpopulated miniPCIe slot are connected to this pin, so they didn't get reset
during a reboot.
Using the newly added driver for the Nuvoton NCT5572D fixes this problem.
There is also a trace from the pin 37 of the SuperIO, which can be configured
as RSTOUT2#, to pin 82 of the USB3-chip with unknown function.
As with the wrong driver, PS/2 keyboard and mouse do work in SeaBIOS and GRUB
but not in Linux.
Change-Id: I4bc78406afd3b0e10a1b04b561147e0ed94cc494
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/6266
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add support for both NCT6776D and NCT6776F devices.
Change-Id: If6686ea0a1cd6be537e286699b4ee8f88ba8ad7c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/5450
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
