Commit Graph

17350 Commits

Author SHA1 Message Date
Stefan Reinauer 66fbeaec98 intel/pineview: Don't try to store 34 bits in 32
Mask out the bit that doesn't fit in 32bits, so gcc 6.1 is happy

Change-Id: I13e2b41742206b8d86b90314b80cc324c00ae637
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14639
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Tested-by: build bot (Jenkins)
2016-05-08 21:36:32 +02:00
Patrick Georgi 2a6f251f4d parade/ps8640: Initialize edid_size
decode_edid either gets EDID_LENGTH bytes or (in the extended case),
2*EDID_LENGTH.
See that this is reflected in its size argument.

Change-Id: If6c76358db4e9ee01c2bd2dbdd5948c61b7aa5bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14698
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-08 08:11:26 +02:00
David Hendricks 292be87205 board_status: Allow for parsing longopts
This converts the argument parsing to allow us to add longopts
using GNU getopt(1).

Shortopts should be reserved for general parameters. Longopts can be
used to tweak specific behaviors. For example, we might wish to add
options to set SSH port, timeout, and authentication parameters
with "--ssh-port", "--ssh-timeout", "--ssh-identity", etc.

Change-Id: Idee5579079dbbb7296ad98f5d6025b01aab55452
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14523
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-05-07 03:15:12 +02:00
Stefan Reinauer fe0609dc3e google/foster: Configure audio codec pads
Otherwise, newer GCCs will insist that they get deleted.

Change-Id: Ida45b7d193366f5e611a32632ba610193451b082
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14619
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-07 00:40:46 +02:00
Stefan Reinauer 617536e580 amd/gx2 + amd/lx: Fix shift overflow issue
gcc 6.1 complains that SMM_OFFSET << 8 is larger than the register
it is assigned to (rightly so):

src/northbridge/amd/gx2/northbridgeinit.c:196:23: error: result of
    '1077936128 << 8' requires 40 bits to represent, but 'int' only
    has 32 bits [-Werror=shift-overflow=]
  msr.lo = (SMM_OFFSET << 8) & 0xfff00000;
                       ^~

Change-Id: Ib0d669268202d222574abee335a6a65c8a255cc7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14617
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06 19:04:51 +02:00
Stefan Reinauer 24850ccf9b rtc: Do checksum check for all bytes
Due to missing braces (that went undetected because of the
indentation), I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8
CMOS: add set_option() only takes the last changed byte into regard
when determining whether the checksum needs to be updated.

This bug went undetected for 5 years.

Change-Id: I47cedc801a60959386dfdcda3a13b8e3162a7ecb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14616
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06 19:03:41 +02:00
Andrey Petrov d5a6eb44ca drivers/intel/fsp2_0: Update to FSP draft 9
Recent FSP draft slightly changed FSP_INFO_HEADER structure. This
change keeps FSP driver code in sync with header changes.

Change-Id: I3536f766a312b9eb73ab8940d91dc9b9dfa347f1
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14614
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 19:00:23 +02:00
Alexandru Gagniuc 851ef96f4e ec/google/chromeec/ec_lpc: Declare used IO ports as a resource
Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC;
however, those ports were not declared as a resource. This had two
major downsides:
* It allowed the allocator to assign said ports to other devices
* It required manually open up an IO window in the LPC bridge.
The LPC bridge on many chromeec boards had to be painstakingly
adjusted to meet these constraints.

The advantage of declaring the resources upfront is that the lpc
bridge can now scan its child resources and automatically open up
IO windows, as requested by its LPC children devices.

Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14585
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-06 18:59:00 +02:00
Alexandru Gagniuc 3aa34a8167 soc/apollolake/lpc: Allow configuring SERIRQ via devicetree
Every other SOC uses a CONFIG_* flag to enable or disable SERIRQ
continuous mode. Why they do that is beyond me, but the way we
implement it on apollolake is via devicetree.

Change-Id: I6e05758e5e264c6b0015467dd25add3bffe2b040
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 18:58:31 +02:00
Alexandru Gagniuc 665fca156c intel/amenia: Declare ChromeEC in devicetree.cb
This allows the chomeec driver to declare its resources so that IO
windows to LPC are opened up during resource allocation.

Change-Id: Ife98ecb4cbf5393493e6c71742de8d37953df548
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14591
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 18:57:56 +02:00
Alexandru Gagniuc 532f319c9d intel/amenia: Check with EC if we should enter recovery mode
Change-Id: Id35a74e3968315659b323e0ba348ad38ca11981b
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14590
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 18:57:36 +02:00
Alexandru Gagniuc 0d3a5126db ec/google/chromeec/ec_commands.h: Include stdint.h
This file use stdint types, but does not include the appropriate
header. This creates a parasitic dependency on including stdint.h
before ec_commands.h. Fix that by including the necesarry header.

Change-Id: I52477028c4ba8f6ffad0356c09e5fad4972649ed
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14589
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 18:57:13 +02:00
Alexandru Gagniuc 5ff7031f72 intel/amenia: Configure the bridge to ChromeEC in the bootblock
Communication with ChromeEC, which is on the LPC bus, is needed early
on for vboot purposes. I'm not sure if Google wants to have the
interface available in bootblock or romstage, so we're confguring it
in the bootblock.

The bridge is automatically reconfigured during ramstage in a way in
which we don't get duplicate windows opened upt to LPC.

Change-Id: I77887e881d23f655495dec2687394409a5bb8cf5
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14588
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 18:56:44 +02:00
Alexandru Gagniuc bdd921c772 soc/apollolake/lpc_lib: Add utility to configure LPC pads
Change-Id: Iaf325863681ad9b8b5d7662a9d267488b8fdf008
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14587
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 18:56:22 +02:00
Alexandru Gagniuc e237f8b766 soc/apollolake/lpc: Open I/O to LPC based on resource allocation
Besides a number of fixed memory windows, Apollolake supports
opening a configureable 64 KiB MMIO window, as well as four PMIO
windows to the LPC bus. Open up these windows dynamically, based on
how resources were allocated to the child LPC devices.

Change-Id: I170e861693cb6fd1be38889adc951f197a13460f
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14584
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 18:55:32 +02:00
Alexandru Gagniuc c1526f0458 Revert "soc/intel/apollolake: Enable LPC bus interface"
This reverts commit e976bd4469.

The LPC resource allocation will be completely reworked in subsequent
patches. The most straightforward approach is to start by reverting
the existing code.

Change-Id: I2475542b79817020d4c956f22ed5856f05046b16
Reviewed-on: https://review.coreboot.org/14583
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 18:54:49 +02:00
Alexandru Gagniuc d5b7c55c46 intel/amenia: Do not manually open up IO windows
Do not use devicetree.cb to manually control hardware registers. This
interface will be removed in a subsequent commit and replaced with
runtime allocation that also does sanity checking.

Change-Id: I55561085ea467f19f52110b1a59f45fe290c7f09
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14582
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 18:54:27 +02:00
Aaron Durbin 7ec9b6c6ac soc/intel/apollolake: fix incorrect bdsm -> tolud memory resources
The wrong base address was being used for the region of memory
between BDSM and TOLUD. This resulted in a very large reserved
region starting at TOLUD instead of BDSM.

Change-Id: I41d06267ffa93ea47aa059f4ddb7b9c349e51583
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14628
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-06 16:50:27 +02:00
Aaron Durbin f5ff854c36 soc/intel: indicate to build system that XIP_ROM_SIZE isn't used
The XIP_ROM_SIZE Kconfig variable isn't used for these chipsets.
Therefore, indicate as such so that romstage can be placed in
cbfs less rigidly.

Change-Id: If5cae10b90e05029df56c282e8adf37fa0102955
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14626
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06 16:50:00 +02:00
Aaron Durbin ef10529187 cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZE
Previously, the XIP_ROM_SIZE Kconfig variable is used globally on
x86 platforms with the assumption that all chipsets utilize this
value.  For the chipsets which do not use the variable it can lead
to unnecessary alignment constraints in cbfs for romstage.  Therefore,
allow those chipsets a path to not be burdened by not passing
'-P $(XIP_ROM_SIZE)' to cbfstool when adding romstage.

Change-Id: Id8692df5ecec116a72b8e5886d86648ca959c78b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14625
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-06 16:49:37 +02:00
Aaron Durbin ab00d779ed util/cbfstool: fix x86 execute-in-place semantics for all fmd regions
A previous patch [1] to make top-aligned addresses work within per
fmap regions caused a significant regression in the semantics of
adding programs that need to be execute-in-place (XIP) on x86
systems. Correct the regression by providing new function,
convert_to_from_absolute_top_aligned(), which top aligns against
the entire boot media.

[1] 9731119b cbfstool: make top-aligned address work per-region

Change-Id: I3b685abadcfc76dab8846eec21e9114a23577578
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14608
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06 16:49:01 +02:00
Aaron Durbin 6366d92803 {cpu,soc}/intel: remove unused smm_init() function
There used to be a need for an empty smm_init() function
because initialize_cpus() called it even though nothing
called initialize_cpus(). However, garbage collection at
link time is implemented so there's no reason to provide an
empty function to satisfy a symbol that is completely culled
during link. Remove it.

Change-Id: Ic13c85f1d3d57e38e7132e4289a98a95829f765a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14605
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06 16:48:21 +02:00
Aaron Durbin 770d7c7395 cpu/x86/mp_init: reduce exposure of internal implementation
With all users converted to using the mp_ops callbacks there's
no need to expose that surface area. Therefore, keep it all
within the mp_init compilation unit.

Change-Id: Ia1cc5326c1fa5ffde86b90d805b8379f4e4f46cd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14598
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06 16:47:54 +02:00
Aaron Durbin 5822582981 soc/intel/skylake: convert to using common MP and SMM init
In order to reduce duplication of code use the common MP and SMM
initialization flow.

Change-Id: I5c4674ed258922b6616d75f070df976ef9fad209
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14597
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-06 16:47:02 +02:00
Aaron Durbin 463af337b0 cpu/intel/haswell: convert to using common MP and SMM init
In order to reduce duplication of code use the common MP and SMM
initialization flow.

Change-Id: I80b5b94b62bdd001581eb56513a0d532fffb64e8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14596
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-06 16:46:29 +02:00
Aaron Durbin 309b8571cf soc/intel/broadwell: convert to using common MP and SMM init
In order to reduce duplication of code use the common MP and SMM
initialization flow.

Change-Id: I74c81c5d18dff7a84bfedbe07f01e536c0f641fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14595
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-06 16:44:18 +02:00
Aaron Durbin e72b9d483f soc/intel/apollolake: convert to using common MP init
In order to reduce duplication of code use the common MP
initialization flow.

Change-Id: I8cfb5ba6f6a31fecde2ce3bf997f87c4486ab3ab
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14594
Tested-by: build bot (Jenkins)
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06 16:43:56 +02:00
Aaron Durbin bbe4a7e944 soc/intel/braswell: convert to using common MP and SMM init
In order to reduce duplication of code use the common MP and SMM
initialization flow.

Change-Id: I65beefec53a29b2861433bc42679f3fa571d5b6a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14593
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06 16:41:22 +02:00
Aaron Durbin 8346b04445 soc/intel/fsp_broadwell_de: convert to using common MP init
In order to reduce duplication of code use the common MP
initialization flow.

Change-Id: I2a7c628cfae7cf6af6e89fa8fc274f59127ff7c7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14592
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
2016-05-06 16:41:01 +02:00
Furquan Shaikh c681409a8a soc/intel/apollolake: Correct PCI write size in romstage
1. PCI command reg write should be 16-bit.
2. HPTC reg write should be 8-bit. Also, use macros instead of
hard-coded values. Currently, the macros are defined in romstage.c,
but if more P2SB macros are added, it would be good to move them to a
separate header file.

Change-Id: Iad1eb6a95467a41ecf454092808d357425c4c2fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14613
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-05-06 06:52:28 +02:00
Patrick Georgi d264b46c49 build system: create fmap for UPDATE_IMAGE configurations, too
This fixes UPDATE_IMAGE builds, assuming that the fmap configuration in
the tree didn't change, at least as far as the CBFS regions are
concerned.

Another option would be to synthesize the fmap related files from the
existing image, but that comes with other issues (eg. what about
updating images old enough that there is no fmap?) and is more complex,
so keep it simple, stupid for now.

Change-Id: I036dab9f81f524f7d70bc0029b1ef835e6180a53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14601
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-05-05 23:16:29 +02:00
Stefan Reinauer 3b0f20ba70 rdc/r8610: Move to src/soc
Change-Id: I99e5d7f3b46c90ca863ddf6c186b5447d0c8e6f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14607
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-05-05 20:08:58 +02:00
Stefan Reinauer 5caf89b9f8 dmp/vortex86ex: Merge northbridge and southbridge into soc
Change-Id: I16c04452d2d6c3205aea29fe8aa8fad8fc485a46
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14600
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-05-05 20:06:33 +02:00
Stefan Reinauer f7dd6d5da1 lib/reg_script: Fix braces
In If0d4d61ed8ef48ec20082b327f358fd1987e3fb9 the code
was changed from one to two lines in the body of an if()
statement, without adding braces.

Change-Id: Ibbbdf240157adae95151fb2ce0135948caa60108
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14621
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-05 19:41:29 +02:00
Lee Leahy 4c3f5dc03c soc/intel/quark: Add script time delay support
Add time delay support to the scripts.

TEST=Build and run on Galileo Gen2

Change-Id: I2c87977e2a2547e00769e59e1ee81fbbb5dff33f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14555
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-05 17:55:26 +02:00
Lee Leahy 63e3dff02f soc/intel/quark: Add temperature sensor support
Migrate the temperature sensor support from QuarkFspPkg into coreboot.

TEST=Build and run on Galileo Gen2

Change-Id: I6dc68c735375c9d1777693264674521f67397556
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14565
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-05 17:53:54 +02:00
Lee Leahy 4dd34eee09 soc/intel/quark: Add USB PHY initialization
Add register access support using register scripts.
Initialize the USB PHY using register scripts.

TEST=Build and run on Galileo Gen2

Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14496
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04 22:36:53 +02:00
Stefan Reinauer 5c4ddebb16 drivers/xpowers: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: Idae5ee5f1f48d904b704abe618165c0bec839979
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04 22:14:44 +02:00
Stefan Reinauer 3dc5d079fe buildgcc: Update Python to 3.5.1
Change-Id: I57f935b94ab0db2e9ff9434fb496d470bb4ec987
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14463
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-05-04 20:40:57 +02:00
Stefan Reinauer 498f3d0cd5 buildgcc: Update gdb and expat
Update gdb to 7.11 and expat to 2.1.1
riscv64-elf is still broken.

Change-Id: Id7605f4274fcb15f9c3e366f5c492328f70f7956
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14461
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2016-05-04 20:21:29 +02:00
Iru Cai ae8e3a0bbb crossgcc: Update toolchain
New tools:
* mpfr 3.1.4
* binutils 2.26
* gcc 5.3.0
* llvm/clang 3.8.0

Patch changes:
* binutils-2.25_fix-aarch64.patch: fixed in 2.26
* binutils-2.25_host-clang.patch: the positions of header file
  includes have been adjusted
* binutils-2.25_no-bfd-doc.patch: update to 2.26
* binutils-2.25_riscv.patch: update from riscv-gnu-toolchain
* gcc-5.2.0_elf_biarch.patch: update to 5.3.0
* gcc-5.2.0_gnat.patch: update to 5.3.0
* gcc-5.2.0_libgcc.patch: update to 5.3.0
* gcc-5.2.0_nds32.patch: update to 5.3.0
* gcc-5.2.0_riscv.patch: update from riscv-gnu-toolchain
* cfe-3.7.1.src_frontend.patch: update to 3.8.0

In the latest code of riscv-gnu-toolchain project, the patch for
{binutils,gcc}/config.sub has been removed, and the target is renamed
as riscv32 and riscv64. The `riscv' to `riscv64' change in xcompile is
in another commit.

Test results:
All GCC and LLVM/clang toolchain build successfully.

x86,arm: qemu boots
power8: firmware fails to boot
aarch64,mips: not tested
riscv: firmware fails to build with new binutils
clang: firmware fails to boot

Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: I42ce89c29263d768d161c28199994f17d0389633
Reviewed-on: https://review.coreboot.org/14227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-04 20:21:11 +02:00
Ravi Sarawadi 2da008afa6 soc/apollolake: Set BootMode based on previous sleep state
- fill_power_state makes a copy of the current snapshot of power
  management
  registers in CAR variable "power_state" for use in ramstage
- migrate_power_state adds CAR variable "power_state" to
  CBMEM (CBMEM_ID_POWER_STATE)
- s3_resume state is updated in romstage_handoff block

Change-Id: I842b85c5e562893b58cd3b3f6432695fbd4430bf
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/14550
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-04 20:09:08 +02:00
Alexandru Gagniuc 15f755bd01 soc/apollolake/romstage: Do not cast const to non-const pointers
That was a workaround for the MRC cache API, which has since been
reworked. The workaround is no longer needed.

Change-Id: I1c1883f3ea37245615248459cd993ed774bf92de
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14574
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-04 20:08:03 +02:00
Alexandru Gagniuc 1116fa86e3 soc/intel/common/mrc_cache: Honor MRC data as a constant pointer
The MRC cache API has absolutely no reason to modify the data it is
asked to stash. Reflect that by taking all "data" parameters as
const void *.

Change-Id: I7a14ffd7d5726aa9aa5db81df82c06e7f87b9d9f
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14250
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-04 20:07:26 +02:00
Patrick Rudolph 9c9bde3aa3 nb/intel/sandybridge/raminit: support calling dram_freq multiple times
The PLL will never lock if the requested frequency is already set.
As the fallback may request the same frequency again exit early
to prevent a hang.

Test system:
 * Gigabyte GA-B75M-D3H
 * Intel Pentium CPU G2130

Change-Id: I625b2956346d8c50cca84def6190c076bf99dbec
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14174
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04 19:59:02 +02:00
Patrick Rudolph 2ccb74b6e9 nb/intel/sandybridge/raminit: add additional fallbacks
Add the following fallbacks:
* Try decreasing clock frequency.
   In case of DDR1600 the next possible value of DDR1333 is being used.
* Try decreasing clock frequency.
   In case of DDR1333 the next possible value of DDR1066 is being used.
* Disable failing channel.
   The system may be able to boot with a single channel enabled.

The fallbacks are untested.

Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14173
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04 19:58:46 +02:00
Nick High 1e302cbd09 nb/intel/gm45: Fix native text mode initialization
The LVDS port is configured to accept data from pipe A, but the panel
fitter and VGA were attached to pipe B.

Changes to VGACNTRL:
- select pipe A instead of pipe B.
- disable VGA centering to fix jitter.

TEST=Build and run on Thinkpad X200 in both text and framebuffer modes.

Change-Id: I2356f264580d8b021952c217de3477291d866f98
Signed-off-by: Nick High <nhigh@openmailbox.org>
Reviewed-on: https://review.coreboot.org/14524
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-05-04 19:57:03 +02:00
Lee Leahy 564dc9c7c8 lib/reg_script: Add display support
Add the ability to enable the display of the script:
* Added REG_SCRIPT_COMMAND_DISPLAY to enable and disable display output
* Added context values to manage display support
  * display_state - Updated by the command to enable or disable display
  * display_features - May be updated by step routine to control what
    the step displays for register and value
  * display_prefix - Prefix to display before register data
* Added REG_SCRIPT_DISPLAY_ON and REG_SCRIPT_DISPLAY_OFF macros to
  control the display from the register script
* Added REG_SCRIPT_DISPLAY_REGISTER and REG_SCRIPT_DISPLAY_VALUE as
  two features of the common display.  With these features enabled
  the following is output:
  * Write: <optional prefix> register <-- value
  * Read:  <optional prefix> register --> value

TEST=Build and run on Galileo Gen2

Change-Id: If0d4d61ed8ef48ec20082b327f358fd1987e3fb9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14553
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-04 19:21:40 +02:00
Joseph Pillow d3fccfbc41 crosfirmware: Make script more silent
Remove debug output and parted messages.

Change-Id: I6416a88b5fdb4c92741439e9edb5f753f885cbe3
Signed-off-by: Joseph Pillow <joseph.a.pillow@gmail.com>
Reviewed-on: https://review.coreboot.org/14460
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04 18:54:59 +02:00
Aaron Durbin 2a07a4d62b soc/intel/fsp_baytrail: convert to using common MP and SMM init
In order to reduce duplication of code use the common MP and SMM
initialization flow.

Change-Id: I709ea938b720f26b351a1f950593efe077edb997
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14581
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2016-05-04 18:52:46 +02:00