Alexey Buyanov 12016969c5 soc/intel/tigerlake: Rename pch_init() code ... Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=successfully built and booted TGLRVP Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>		2020-08-26 07:36:21 +00:00
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apollolake	mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms	2020-08-24 23:30:50 +00:00
baytrail	mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms	2020-08-24 23:30:50 +00:00
braswell	SMM: Validate more user-provided pointers	2020-08-21 07:51:07 +00:00
broadwell	mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms	2020-08-24 23:30:50 +00:00
cannonlake	soc/intel/cnl: Configure FSP option PcieRpSlotImplemented	2020-08-23 09:57:02 +00:00
common	soc/intel/common: Add downgrade support for CSE Firmware	2020-08-24 09:12:34 +00:00
denverton_ns	cpu,soc/intel: Drop select SMP	2020-07-26 20:59:52 +00:00
icelake	elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE	2020-08-18 15:57:40 +00:00
jasperlake	soc/intel/jasperlake: Disable multiphase SI init	2020-08-25 12:59:57 +00:00
quark	src: Make HAVE_CF9_RESET set the FADT reset register	2020-07-20 13:23:13 +00:00
skylake	elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE	2020-08-18 15:57:40 +00:00
tigerlake	soc/intel/tigerlake: Rename pch_init() code	2020-08-26 07:36:21 +00:00
xeon_sp	soc/intel/xeon_sp/cpx/Kconfig: Relocate 'select CACHE_MRC_SETTINGS'	2020-08-20 07:46:04 +00:00
Kconfig