John Zhao 270e25594f soc/intel/alderlake: Avoid NULL pointer deference ... Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458077, 1458078 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-07-08 15:47:53 +00:00
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acpi	soc/intel/alderlake: Enable support for common IRQ block	2021-06-29 21:54:00 +00:00
bootblock	soc/intel/alderlake: Add GFx Device ID 0x46b3	2021-06-21 05:38:58 +00:00
include/soc	soc/intel/alderlake: Correct Bus and Device of Touch Host Controller	2021-07-05 05:27:26 +00:00
romstage	soc/intel/alderlake: Update mainboard_memory_init_params() argument	2021-06-24 07:55:12 +00:00
spd	soc/intel/alderlake: Add new memory parts for ADL boards	2021-06-03 15:51:17 +00:00
acpi.c	soc/intel: Drop casts around soc_read_pmc_base()	2021-06-28 04:16:48 +00:00
chip.c	soc/intel/alderlake: Enable support for common IRQ block	2021-06-29 21:54:00 +00:00
chip.h	soc/intel/alderlake: Add support to update the FIVR configs	2021-07-05 10:47:17 +00:00
chipset.cb	soc/intel/alderlake: Correct Bus and Device of Touch Host Controller	2021-07-05 05:27:26 +00:00
cpu.c	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
crashlog.c	soc/intel/alderlake: Avoid NULL pointer deference	2021-07-08 15:47:53 +00:00
dptf.c	soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoC	2021-04-23 14:46:33 +00:00
elog.c	soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros	2021-05-03 16:28:53 +00:00
espi.c	src: Match array format in function declarations and definitions	2021-05-13 18:34:38 +00:00
finalize.c
fsp_params.c	soc/intel/alderlake: Add support to update the FIVR configs	2021-07-05 10:47:17 +00:00
gpio.c	soc/intel/alderlake: Add known GPIO virtual wire information	2021-05-14 08:58:07 +00:00
gspi.c
i2c.c
Kconfig	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
lockdown.c
Makefile.inc	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
me.c
meminit.c	soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards	2021-05-16 22:17:52 +00:00
p2sb.c
pcie_rp.c
pmc.c	soc/intel/common: Move PMC EPOC related code to Intel common code	2021-06-30 07:34:44 +00:00
pmutil.c	soc/intel/*/pmutil.c: Align cosmetics across platforms	2021-02-24 11:34:42 +00:00
reset.c
smihandler.c	soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster	2021-05-07 06:05:18 +00:00
soundwire.c	soc/intel/common: Move PMC EPOC related code to Intel common code	2021-06-30 07:34:44 +00:00
spi.c
systemagent.c	soc/intel/adl: Add SKU specific power limits support	2021-06-07 19:02:02 +00:00
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
xhci.c	soc/intel/alderlake: Correct TCSS XHCI Port status offset	2021-06-08 15:25:29 +00:00