Meera Ravindranath 3b03798953 soc/intel/alderlake: Disable VT-d for early silicons ... VT-d needs to disabled for early silicons as it results in a CPU hard hang. BUG=b:197177091 Test=Boot brya to OS with no hang Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>		2021-11-15 10:34:44 +00:00
..
acpi	soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimization	2021-10-29 16:53:57 +00:00
bootblock	soc/intel/alderlake: Add CPU ID 0x906a4	2021-09-30 13:37:57 +00:00
include/soc	soc/intel/alderlake: set lock offset for gpio pad communities	2021-10-26 19:33:37 +00:00
romstage	soc/intel/alderlake: Disable VT-d for early silicons	2021-11-15 10:34:44 +00:00
acpi.c	soc/intel: Constify soc_get_cstate_map()	2021-10-19 14:57:59 +00:00
chip.c	soc/intel/alderlake: Add igd device	2021-09-16 00:05:21 +00:00
chip.h	soc/intel/alderlake: Enable Intel FIVR RFI settings	2021-11-09 20:21:39 +00:00
chipset.cb	soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU	2021-10-01 18:44:33 +00:00
cpu.c	cpu/x86/mp_init: move printing of failure message into mp_init_with_smm	2021-10-22 01:27:07 +00:00
crashlog.c	soc/intel/alderlake: Avoid NULL pointer deference	2021-07-08 15:47:53 +00:00
dptf.c	drivers/intel/dptf: Add support for PCH methods	2021-10-11 12:45:47 +00:00
elog.c	soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros	2021-05-03 16:28:53 +00:00
espi.c	src: Match array format in function declarations and definitions	2021-05-13 18:34:38 +00:00
finalize.c	soc/intel: move disabling of PM Timer to SoC PMC code	2021-10-17 13:57:30 +00:00
fsp_params.c	soc/intel/alderlake: Enable Intel FIVR RFI settings	2021-11-09 20:21:39 +00:00
gpio.c	soc/intel/alderlake: set lock offset for gpio pad communities	2021-10-26 19:33:37 +00:00
gspi.c
i2c.c	soc/intel/alderlake: Add support for I2C6 and I2C7	2021-07-20 13:35:10 +00:00
Kconfig	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
lockdown.c
Makefile.inc	cpu/x86: Introduce and use CPU_X86_LAPIC	2021-10-26 17:44:14 +00:00
me.c
meminit.c	soc/intel/alderlake: Implement WA for DDR5 DIMM modules	2021-07-13 14:30:07 +00:00
p2sb.c
pcie_rp.c
pmc.c	soc/intel: implement ACPI timer disabling per SoC and drop common code	2021-10-17 13:57:53 +00:00
pmutil.c
reset.c
smihandler.c	soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster	2021-05-07 06:05:18 +00:00
soundwire.c	soc/intel/common: Move PMC EPOC related code to Intel common code	2021-06-30 07:34:44 +00:00
spi.c	soc/intel: Update api name for getting spi destination id	2021-10-26 18:12:17 +00:00
systemagent.c	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
uart.c
vr_config.c	soc/intel/alderlake: Allow devicetree override to leave some VR settings as default	2021-11-03 09:33:12 +00:00
xhci.c	soc/intel/alderlake: Correct TCSS XHCI Port status offset	2021-06-08 15:25:29 +00:00