Michael Niewöhner 586b1beb9c soc/intel: drop Kconfig PM_ACPI_TIMER_OPTIONAL ... Technically, it's not depending on the hardware but on the software (OS/payload), if the PM Timer is optional. OSes with ACPI >= 5.0A support disabling of the PM Timer, when the respective FADT flag is unset. Thus, drop this guard. For platforms without hardware PM Timer (Apollo Lake, Gemini Lake) the Kconfig `USE_PM_ACPI_TIMER` depends on `!NO_PM_ACPI_TIMER`. As of this change, new platforms must either implement code for disabling the hardware PM timer or select `NO_PM_ACPI_TIMER` if no such is present. Change-Id: I973ad418ba43cbd80b023abf94d3548edc53a561 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao		2021-11-08 21:11:05 +00:00
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acpi	soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimization	2021-10-29 16:53:57 +00:00
bootblock	soc/intel/alderlake: Add CPU ID 0x906a4	2021-09-30 13:37:57 +00:00
include/soc	soc/intel/alderlake: set lock offset for gpio pad communities	2021-10-26 19:33:37 +00:00
romstage	soc/intel/adl: Skip sending MBP HOB to save boot time	2021-10-26 05:47:07 +00:00
acpi.c	soc/intel: Constify soc_get_cstate_map()	2021-10-19 14:57:59 +00:00
chip.c	soc/intel/alderlake: Add igd device	2021-09-16 00:05:21 +00:00
chip.h	soc/intel: replace dt option PmTimerDisabled by Kconfig	2021-10-12 18:25:35 +00:00
chipset.cb	soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU	2021-10-01 18:44:33 +00:00
cpu.c	cpu/x86/mp_init: move printing of failure message into mp_init_with_smm	2021-10-22 01:27:07 +00:00
crashlog.c	soc/intel/alderlake: Avoid NULL pointer deference	2021-07-08 15:47:53 +00:00
dptf.c	drivers/intel/dptf: Add support for PCH methods	2021-10-11 12:45:47 +00:00
elog.c	soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros	2021-05-03 16:28:53 +00:00
espi.c	src: Match array format in function declarations and definitions	2021-05-13 18:34:38 +00:00
finalize.c	soc/intel: move disabling of PM Timer to SoC PMC code	2021-10-17 13:57:30 +00:00
fsp_params.c	soc/intel/alderlake: Fix wrong FIVR configs assignment	2021-10-20 15:48:38 +00:00
gpio.c	soc/intel/alderlake: set lock offset for gpio pad communities	2021-10-26 19:33:37 +00:00
gspi.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
i2c.c	soc/intel/alderlake: Add support for I2C6 and I2C7	2021-07-20 13:35:10 +00:00
Kconfig	soc/intel: drop Kconfig PM_ACPI_TIMER_OPTIONAL	2021-11-08 21:11:05 +00:00
lockdown.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Makefile.inc	cpu/x86: Introduce and use CPU_X86_LAPIC	2021-10-26 17:44:14 +00:00
me.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
meminit.c	soc/intel/alderlake: Implement WA for DDR5 DIMM modules	2021-07-13 14:30:07 +00:00
p2sb.c	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	2020-09-15 15:13:50 +00:00
pcie_rp.c	soc/intel/alderlake: Update PCH and CPU PCIe RP table	2021-01-18 07:28:51 +00:00
pmc.c	soc/intel: implement ACPI timer disabling per SoC and drop common code	2021-10-17 13:57:53 +00:00
pmutil.c	soc/intel/*/pmutil.c: Align cosmetics across platforms	2021-02-24 11:34:42 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
smihandler.c	soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster	2021-05-07 06:05:18 +00:00
soundwire.c	soc/intel/common: Move PMC EPOC related code to Intel common code	2021-06-30 07:34:44 +00:00
spi.c	soc/intel: Update api name for getting spi destination id	2021-10-26 18:12:17 +00:00
systemagent.c	soc/intel/alderlake: set power limits dynamically for thermal	2021-09-03 16:14:28 +00:00
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
vr_config.c	soc/intel/alderlake: Allow devicetree override to leave some VR settings as default	2021-11-03 09:33:12 +00:00
xhci.c	soc/intel/alderlake: Correct TCSS XHCI Port status offset	2021-06-08 15:25:29 +00:00