Angel Pons 6f5a6581a6 src: Introduce ARCH_ALL_STAGES_X86 ... Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>		2021-07-02 08:19:10 +00:00
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acpi	soc/amd/picasso/acpi/sb_fch: use AOAC offset defines	2021-06-16 16:38:15 +00:00
include/soc	soc/amd/cezanne,picasso/include/soc/iomap: reflow I2C_DEVICE_COUNT	2021-06-16 16:38:55 +00:00
psp_verstage	psp_verstage: differentiate bios entry	2021-05-10 04:07:09 +00:00
acpi.c	soc/amd/picasso,stoneyridge/acpi: use defines for MADT parameters	2021-06-18 16:01:43 +00:00
agesa_acpi.c	soc/amd: factor out acpi_soc_get_bert_region to amd/common	2021-06-08 18:24:00 +00:00
aoac.c	soc/amd/picasso: factor out AOAC offset defines	2021-06-16 16:38:07 +00:00
bootblock.c	soc/amd/picasso: factor out write_resume_eip to common code	2020-12-11 00:44:31 +00:00
chip.c	soc/amd/common/block/i2c: Move SoC agnostic parts into common	2021-03-22 03:40:42 +00:00
chip.h	soc/amd/picasso: add devicetree setting for PSPP policy	2021-05-27 16:43:15 +00:00
chipset.cb	soc/amd/picasso: introduce and use devicetree aliases for UART0-3	2021-06-17 14:21:58 +00:00
config.c	soc/amd/picasso/config: add comment about cfg never being NULL	2020-12-06 19:04:51 +00:00
cpu.c	soc/amd/picasso: remove warm reset flag code	2021-06-02 15:27:26 +00:00
data_fabric.c	cpu/x86/lapic: Replace LOCAL_APIC_ADDR references	2021-06-11 07:11:43 +00:00
early_fch.c	soc/amd/piasso/fch: use common pm_set_power_failure_state functionality	2021-04-14 18:46:23 +00:00
fch.c	soc/amd/{picasso/common}: Move populate_pirq_data prototype to common	2021-05-06 23:14:12 +00:00
fsp_m_params.c	soc/amd/picasso: add devicetree setting for PSPP policy	2021-05-27 16:43:15 +00:00
fsp_s_params.c	soc/amd/cezanne,picasso: rename fsp_params.c to fsp_s_params.c	2021-03-29 19:52:01 +00:00
fw.cfg	soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION	2020-11-04 09:42:18 +00:00
gpio.c	soc/amd: remove special GPIO_2 override soc_gpio_hook	2021-04-08 16:47:27 +00:00
graphics.c	soc/amd/picasso/graphics: implement map_oprom_vendev_rev	2020-06-14 19:08:08 +00:00
i2c.c	trivial: Fix the tab and rearrange the lines	2021-03-22 03:41:25 +00:00
Kconfig	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
Makefile.inc	soc/amd/picasso: Move Type 17 DMI generation to common	2021-06-13 09:55:30 +00:00
mca.c	soc/amd/picasso: remove warm reset flag code	2021-06-02 15:27:26 +00:00
pcie_gpp.c	soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver	2021-05-12 00:46:27 +00:00
reset.c	soc/amd/picasso: remove warm reset flag code	2021-06-02 15:27:26 +00:00
romstage.c	soc/amd/{cezanne,picasso}: Add TS_START_ROMSTAGE	2021-06-14 18:54:55 +00:00
root_complex.c	soc/amd: factor out acpigen_write_alib_dptc to common code	2021-05-13 00:58:26 +00:00
sata.c
smihandler.c	soc/amd/picasso/smihandler: sort includes alphabetically	2021-03-10 00:31:38 +00:00
smu.c	soc/amd/common: factor out SMU code from Picasso	2020-11-15 16:48:38 +00:00
soc_util.c	soc/amd/picasso/soc_util.c: Fix typo in macro name	2021-03-19 11:22:32 +00:00
uart.c	soc/amd/picasso: factor out AOAC offset defines	2021-06-16 16:38:07 +00:00
xhci.c	soc/amd: factor out common SMI/SCI enums and function prototypes	2020-12-02 21:33:14 +00:00