Angel Pons c3be055fbe soc/intel/baytrail/sata.c: Fix SATA init sequence ... SeaBIOS on Bay Trail would time out when trying to access a SATA drive. Turns out that there's two mistakes in the SATA initialization sequence: - PCI register 0x94 is wrongly cleared with a bitwise-and operation. - PCI register 0x9c is instead written to 0x98, clobbering the latter. After correcting them, SeaBIOS can boot from SATA on Asrock Q1900M. Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44088 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-08-02 12:18:40 +00:00
..
acpi	soc/intel/baytrail: Align whitespace and comments	2020-07-09 12:47:47 +00:00
bootblock	soc/intel/baytrail/bootblock/bootblock.c: Move functions	2020-07-25 10:17:46 +00:00
include/soc	soc/intel/baytrail: Add native refcode replacement	2020-08-02 12:07:08 +00:00
romstage	{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits	2020-07-26 21:17:50 +00:00
acpi.c	soc/intel/baytrail/acpi.c: Align with Braswell	2020-07-25 10:17:56 +00:00
chip.c
chip.h
cpu.c	soc/intel/baytrail/cpu.c: Align with Braswell	2020-07-25 10:22:33 +00:00
dptf.c
ehci.c	soc/intel/baytrail: Rename "pmc.h" to "pm.h"	2020-07-09 12:46:35 +00:00
elog.c	soc/intel/baytrail/elog.c: Align with Braswell	2020-07-25 10:18:52 +00:00
emmc.c	soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controller	2020-07-12 19:44:02 +00:00
fadt.c	src: Use ACPI macros	2020-07-21 18:26:47 +00:00
gfx.c	{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits	2020-07-26 21:17:50 +00:00
gpio.c	soc/intel/baytrail: Rename "pmc.h" to "pm.h"	2020-07-09 12:46:35 +00:00
hda.c
iosf.c	soc/intel/baytrail: Add native refcode replacement	2020-08-02 12:07:08 +00:00
Kconfig	soc/intel/baytrail: Add native refcode replacement	2020-08-02 12:07:08 +00:00
lpe.c	soc/intel/baytrail/lpe.c: Align with Braswell	2020-07-25 10:21:59 +00:00
lpss.c	{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits	2020-07-26 21:17:50 +00:00
Makefile.inc	soc/intel/baytrail: Add native refcode replacement	2020-08-02 12:07:08 +00:00
memmap.c
modphy_table.c	soc/intel/baytrail: Add native refcode replacement	2020-08-02 12:07:08 +00:00
northcluster.c	soc/intel/baytrail/northcluster.c: Rename variable	2020-08-02 12:03:40 +00:00
pcie.c	src: Use pci_dev_ops_pci where applicable	2020-06-06 20:36:51 +00:00
perf_power.c
placeholders.c
pmutil.c	soc/intel/baytrail: Retype some pointers	2020-07-25 10:17:40 +00:00
ramstage.c	soc/intel/baytrail: Simplify pattrs definitions	2020-07-25 10:23:09 +00:00
refcode.c
refcode_native.c	soc/intel/baytrail: Add native refcode replacement	2020-08-02 12:07:08 +00:00
sata.c	soc/intel/baytrail/sata.c: Fix SATA init sequence	2020-08-02 12:18:40 +00:00
scc.c	{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits	2020-07-26 21:17:50 +00:00
sd.c	soc/intel/baytrail/sd.c: Align with Braswell	2020-07-25 10:22:18 +00:00
smihandler.c	soc/intel/baytrail/smihandler.c: Align with Braswell	2020-07-25 10:22:41 +00:00
smm.c	soc/intel/baytrail/smm.c: Align with Braswell	2020-07-25 10:22:52 +00:00
southcluster.c	src: Remove whitespace between 'sizeof' and '('	2020-07-26 21:18:16 +00:00
tsc_freq.c
xhci.c	soc/intel/baytrail: Rename "pmc.h" to "pm.h"	2020-07-09 12:46:35 +00:00