SeaBIOS on Bay Trail would time out when trying to access a SATA drive.
Turns out that there's two mistakes in the SATA initialization sequence:
- PCI register 0x94 is wrongly cleared with a bitwise-and operation.
- PCI register 0x9c is instead written to 0x98, clobbering the latter.
After correcting them, SeaBIOS can boot from SATA on Asrock Q1900M.
Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44088
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- This is a reverse engineered re-implementation of refcode.elf on
Bay Trail
- Tested on GBYT4, should work everywhere as it's meant to behave
exactly the same as the binary refcode
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I91977c509022b0078804dc151d27296260e24bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43133
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with BUILD_TIMELESS=1, Google Ninja does not change.
Change-Id: I7e74f342c0545f8d2a2128de4162581e5dc01e17
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These now fit in 96 characters.
Tested with BUILD_TIMELESS=1, Google Ninja does not change.
Change-Id: I7e1dc0126fa4d64f75e686d68c4f70f7109c6da0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We have definitions for the bits in the PCI COMMAND register. Use them.
Also add spaces around bitwise operators, to comply with the code style.
Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I49e9cef1dfaa62dcfbd1260cec459ff5910ad5da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell, and avoids
unlikely but potential bugs regarding missing braces in macros.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ic341fe70e7d6fb4751f2fefbdedbee5c90dd8d1f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43201
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I90632909cd7d632d80739b3762e4ccba51624b75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43200
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43199
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaa6d5d72cd0368342205a9b98552c1e0762abbce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43198
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I9d9edd774143b0a98773b6d5de630d116cb6f0b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43197
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I08ccbc70744a17d589450e321a3ed77d9a56492f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43196
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I98d17fc470149b181e8d92b8bcc5d99c68299212
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43195
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: If75b4299918f5bee3cc68bc662d03f1a819aef68
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no reason to return the result of a void function.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I677dec1622768874a51effd6d73f0b2329f27aed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43193
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell, and
prevents possible bugs when using these macros.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I18e9a750901f1bf8d3b61f4b64bbed907bc1fa15
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43192
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ifd71881e3924dca3add1e788852e7eb078405d00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I52d58c6b77cd870b5d3f5892521e4c82027c4cac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43190
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I0b07f8d52203c0a6d20b747f36d4d22cf53c791c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I34079985e165ce8d10c7a2b4f0dde15060132208
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43188
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This ID is reported by newer mfg date SOCs. Needed for newer GBYT4 boards.
Change-Id: I6af746d66a15f67553de1dc1c925e5cb0b181898
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to the ACPI specification, version 6.3:
Accesses to the PM1 status registers are done through byte or word
accesses.
The same is said about the PM1 Enable registers. Therefore, reporting
dword-sized access is wrong and means nothing anyway. Since some other
platforms use word-sized access, use word everywhere for consistency.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: I6f85c9a4126f37ab2a193c3ab50a6c8e62cf6515
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43432
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.
To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Instead, just flip the desired bits using bitwise operations. As this is
initially zero, the resulting value is the same. This allows flags to be
set from anywhere regardless of execution order.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event
register blocks. According to the ACPI specification, version 6.3,
sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers):
If the PM1b_EVT_BLK is not supported, its pointer contains a value of
zero in the FADT.
If the PM1b_CNT_BLK is not supported, its pointer contains a value of
zero in the FADT.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with PM1b for now. So, drop unneeded writes to PM1b fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the currently-supported chips has a GPE1 block. The ACPI spec,
version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says:
If a generic register block is not supported then its respective
block pointer and block length values in the FADT table contain zeros.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.
Change-Id: I702988493e3b29d807a75c70485baaa2ff6d1aa2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This reduces the differences between Bay Trail and Braswell.
The resulting binary changes, but it shouldn't matter.
Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
This can result in accesses outside array bounds. Copy what Braswell
does, which is slightly safer.
Change-Id: If3d6f4e1f8921f0be7f4e5e438b7e73c46b8ef95
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig.
Change-Id: I617f332b80c534997e06a91247d1be90a85573be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Except for whitespace and varying casts the codes were
the same when implemented.
Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.
Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For baytrail and braswell, explicitly initialise
it to ACTIVE_ECFW_RO without ChromeEC.
For broadwell and skylake, fix it to report actual
google_ec_running_ro() status.
Change-Id: I30236c41c9261fd9f8565e1c5fdbfe6f46114e28
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42389
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
