John Zhao 49111cd2ba soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ... Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table. BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries. Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>		2020-03-12 21:36:57 +00:00
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bootblock.h	soc/intel/{icl,tgl}: Rename pch_early_init() to pch_init()	2019-11-15 11:02:37 +00:00
cpu.h	soc/intel/tigerlake: Do initial SoC commit till ramstage	2019-11-09 03:26:34 +00:00
espi.h
gpe.h	soc/intel/tigerlake: Do initial SoC commit till ramstage	2019-11-09 03:26:34 +00:00
gpio.h	soc/intel/tigerlake: Add Jasper lake GPIO support	2020-03-03 10:09:26 +00:00
gpio_defs.h	soc/intel/tigerlake: Add Jasper lake GPIO support	2020-03-03 10:09:26 +00:00
gpio_defs_jsl.h	soc/intel/tigerlake: Add Jasper lake GPIO support	2020-03-03 10:09:26 +00:00
gpio_defs_tgl.h	soc/intel/tigerlake: Add Jasper lake GPIO support	2020-03-03 10:09:26 +00:00
gpio_soc_defs.h	soc/intel/tigerlake: Add Jasper lake GPIO support	2020-03-03 10:09:26 +00:00
gpio_soc_defs_jsl.h	soc/intel/tigerlake: Add Jasper lake GPIO support	2020-03-03 10:09:26 +00:00
gpio_soc_defs_tgl.h	soc/intel/tigerlake: Add Jasper lake GPIO support	2020-03-03 10:09:26 +00:00
iomap.h	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	2020-03-12 21:36:57 +00:00
irq.h	soc/tigerlake: Add IRQ header and ACPI support for JSP	2020-02-19 12:11:26 +00:00
irq_jsl.h	soc/tigerlake: Add IRQ header and ACPI support for JSP	2020-02-19 12:11:26 +00:00
irq_tgl.h	soc/tigerlake: Add IRQ header and ACPI support for JSP	2020-02-19 12:11:26 +00:00
itss.h	soc/intel/tigerlake: Do initial SoC commit till ramstage	2019-11-09 03:26:34 +00:00
me.h	src/intel: Define HFSTS3 register	2020-02-17 15:56:55 +00:00
meminit_jsl.h	src/soc/tigerlake: Add memory configuration support for Jasper Lake	2020-03-03 04:07:39 +00:00
meminit_tgl.h	soc/intel/tigerlake: add memory configuration support	2020-02-09 19:26:36 +00:00
msr.h	soc/intel/tigerlake: Do initial SoC commit till ramstage	2019-11-09 03:26:34 +00:00
nvs.h	soc/intel/tigerlake: Do initial SoC commit till ramstage	2019-11-09 03:26:34 +00:00
p2sb.h
pch.h	soc/intel/tigerlake: Pick correct pmc base reg from pch type	2019-12-16 09:36:49 +00:00
pci_devs.h	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	2020-03-12 21:36:57 +00:00
pcr_ids.h
pm.h	intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected	2020-03-07 20:32:36 +00:00
pmc.h	soc/intel/tigerlake: Add Jasper lake GPIO support	2020-03-03 10:09:26 +00:00
ramstage.h	soc/intel/tigerlake: Do initial SoC commit till ramstage	2019-11-09 03:26:34 +00:00
romstage.h	soc/intel/tigerlake: Update header files	2020-01-15 14:30:07 +00:00
serialio.h	soc/intel/tigerlake: Update header files	2020-01-15 14:30:07 +00:00
smbus.h	intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers	2020-03-07 20:32:46 +00:00
soc_chip.h
systemagent.h	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	2020-03-12 21:36:57 +00:00
usb.h	soc/intel/tigerlake: Do initial SoC commit till ramstage	2019-11-09 03:26:34 +00:00