2008-08-20 15:41:24 +02:00
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/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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2010-04-27 08:56:47 +02:00
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* Copyright (C) 2008-2010 by coresystems GmbH
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2010-10-24 15:50:13 +02:00
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* Copyright (C) 2009 Carl-Daniel Hailfinger
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2010-04-27 08:56:47 +02:00
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*
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2008-08-20 15:41:24 +02:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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Remove address from GPLv2 headers
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-03-26 15:17:45 +01:00
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* Foundation, Inc.
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2008-08-20 15:41:24 +02:00
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*/
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#include <stdint.h>
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2009-09-01 11:52:14 +02:00
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#if defined(__GLIBC__)
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2008-12-04 16:18:20 +01:00
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#include <sys/io.h>
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2009-09-01 11:52:14 +02:00
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#endif
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#if (defined(__MACH__) && defined(__APPLE__))
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2011-03-18 23:53:38 +01:00
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/* DirectHW is available here: http://www.coreboot.org/DirectHW */
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2009-09-01 11:52:14 +02:00
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#define __DARWIN__
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2011-03-18 23:08:39 +01:00
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#include <DirectHW/DirectHW.h>
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2008-12-04 16:18:20 +01:00
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#endif
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2008-08-20 15:41:24 +02:00
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#include <pci/pci.h>
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2010-10-24 15:50:13 +02:00
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/* This #include is needed for freebsd_{rd,wr}msr. */
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#if defined(__FreeBSD__)
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#include <machine/cpufunc.h>
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#endif
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2008-08-20 15:41:24 +02:00
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#define INTELTOOL_VERSION "1.0"
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/* Tested chipsets: */
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2009-09-30 19:05:46 +02:00
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_ICH 0x2410
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#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
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#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
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#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
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#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
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2010-12-17 23:34:58 +01:00
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#define PCI_DEVICE_ID_INTEL_ICH5 0x24d0
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2010-04-21 08:23:19 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH6 0x2640
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
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#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
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#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
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#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
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2010-08-17 10:33:44 +02:00
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#define PCI_DEVICE_ID_INTEL_NM10 0x27bc
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#define PCI_DEVICE_ID_INTEL_ICH8 0x2810
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
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2015-03-01 10:14:15 +01:00
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#define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811
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2010-05-30 14:33:12 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912
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#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914
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#define PCI_DEVICE_ID_INTEL_ICH9R 0x2916
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#define PCI_DEVICE_ID_INTEL_ICH9 0x2918
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#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919
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#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
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2013-05-28 11:30:25 +02:00
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#define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00
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#define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01
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#define PCI_DEVICE_ID_INTEL_P55 0x3b02
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#define PCI_DEVICE_ID_INTEL_PM55 0x3b03
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#define PCI_DEVICE_ID_INTEL_H55 0x3b06
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#define PCI_DEVICE_ID_INTEL_QM57 0x3b07
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#define PCI_DEVICE_ID_INTEL_H57 0x3b08
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#define PCI_DEVICE_ID_INTEL_HM55 0x3b09
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#define PCI_DEVICE_ID_INTEL_Q57 0x3b0a
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#define PCI_DEVICE_ID_INTEL_HM57 0x3b0b
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#define PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF 0x3b0d
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#define PCI_DEVICE_ID_INTEL_B55_A 0x3b0e
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#define PCI_DEVICE_ID_INTEL_QS57 0x3b0f
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#define PCI_DEVICE_ID_INTEL_3400 0x3b12
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#define PCI_DEVICE_ID_INTEL_3420 0x3b14
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#define PCI_DEVICE_ID_INTEL_3450 0x3b16
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#define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e
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2010-06-01 12:04:28 +02:00
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
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2013-03-29 17:57:15 +01:00
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#define PCI_DEVICE_ID_INTEL_Z68 0x1c44
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#define PCI_DEVICE_ID_INTEL_P67 0x1c46
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#define PCI_DEVICE_ID_INTEL_UM67 0x1c47
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#define PCI_DEVICE_ID_INTEL_HM65 0x1c49
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#define PCI_DEVICE_ID_INTEL_H67 0x1c4a
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#define PCI_DEVICE_ID_INTEL_HM67 0x1c4b
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#define PCI_DEVICE_ID_INTEL_Q65 0x1c4c
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#define PCI_DEVICE_ID_INTEL_QS67 0x1c4d
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#define PCI_DEVICE_ID_INTEL_Q67 0x1c4e
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#define PCI_DEVICE_ID_INTEL_QM67 0x1c4f
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#define PCI_DEVICE_ID_INTEL_B65 0x1c50
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#define PCI_DEVICE_ID_INTEL_C202 0x1c52
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#define PCI_DEVICE_ID_INTEL_C204 0x1c54
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#define PCI_DEVICE_ID_INTEL_C206 0x1c56
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#define PCI_DEVICE_ID_INTEL_H61 0x1c5c
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#define PCI_DEVICE_ID_INTEL_Z77 0x1e44
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#define PCI_DEVICE_ID_INTEL_Z75 0x1e46
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#define PCI_DEVICE_ID_INTEL_Q77 0x1e47
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#define PCI_DEVICE_ID_INTEL_Q75 0x1e48
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#define PCI_DEVICE_ID_INTEL_B75 0x1e49
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#define PCI_DEVICE_ID_INTEL_H77 0x1e4a
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#define PCI_DEVICE_ID_INTEL_C216 0x1e53
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#define PCI_DEVICE_ID_INTEL_QM77 0x1e55
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#define PCI_DEVICE_ID_INTEL_QS77 0x1e56
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#define PCI_DEVICE_ID_INTEL_HM77 0x1e57
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#define PCI_DEVICE_ID_INTEL_UM77 0x1e58
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#define PCI_DEVICE_ID_INTEL_HM76 0x1e59
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#define PCI_DEVICE_ID_INTEL_HM75 0x1e5d
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#define PCI_DEVICE_ID_INTEL_HM70 0x1e5e
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#define PCI_DEVICE_ID_INTEL_NM70 0x1e5f
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2014-10-30 10:30:40 +01:00
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
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2015-05-15 04:58:33 +02:00
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_82810 0x7120
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2012-10-13 02:19:30 +02:00
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#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
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#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
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2010-02-22 12:26:06 +01:00
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#define PCI_DEVICE_ID_INTEL_82830M 0x3575
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_82845 0x1a30
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2010-12-17 23:34:58 +01:00
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#define PCI_DEVICE_ID_INTEL_82865 0x2570
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2010-04-21 08:23:19 +02:00
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#define PCI_DEVICE_ID_INTEL_82915 0x2580
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_82945P 0x2770
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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2012-10-13 02:19:30 +02:00
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#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac
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2012-10-13 06:23:52 +02:00
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#define PCI_DEVICE_ID_INTEL_82946 0x2970
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2012-10-13 02:19:30 +02:00
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#define PCI_DEVICE_ID_INTEL_82965PM 0x2a00
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#define PCI_DEVICE_ID_INTEL_82Q965 0x2990
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_82975X 0x277c
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2009-11-02 16:01:49 +01:00
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#define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
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#define PCI_DEVICE_ID_INTEL_82G33 0x29c0
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#define PCI_DEVICE_ID_INTEL_82Q33 0x29d0
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2012-10-13 02:19:30 +02:00
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#define PCI_DEVICE_ID_INTEL_82X38 0x29e0
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2011-04-04 07:53:19 +02:00
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#define PCI_DEVICE_ID_INTEL_32X0 0x29f0
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2015-08-17 13:04:41 +02:00
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#define PCI_DEVICE_ID_INTEL_82XX4X 0x2a40
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#define PCI_DEVICE_ID_INTEL_82Q45 0x2e10
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#define PCI_DEVICE_ID_INTEL_82G45 0x2e20
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#define PCI_DEVICE_ID_INTEL_82G41 0x2e30
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#define PCI_DEVICE_ID_INTEL_82B43 0x2e40
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#define PCI_DEVICE_ID_INTEL_82B43_2 0x2e90
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2012-10-13 02:19:30 +02:00
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#define PCI_DEVICE_ID_INTEL_82X58 0x3405
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
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#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
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2011-10-30 13:30:36 +01:00
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#define PCI_DEVICE_ID_INTEL_I63XX 0x2670
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2012-01-08 15:27:18 +01:00
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2012-07-05 22:53:57 +02:00
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#define PCI_DEVICE_ID_INTEL_I5000X 0x25c0
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#define PCI_DEVICE_ID_INTEL_I5000Z 0x25d0
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#define PCI_DEVICE_ID_INTEL_I5000V 0x25d4
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2012-01-08 15:27:18 +01:00
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#define PCI_DEVICE_ID_INTEL_I5000P 0x25d8
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2010-07-29 21:25:31 +02:00
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/* untested, but almost identical to D-series */
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2012-10-13 02:19:30 +02:00
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#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
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/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
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#define PCI_DEVICE_ID_INTEL_82443BX 0x7190
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#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192
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/* 82371AB/EB/MB use the same device ID value. */
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#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
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2008-08-20 15:41:24 +02:00
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2014-12-08 06:11:54 +01:00
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/* Bay Trail */
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#define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0f00 /* SOC Transaction Router */
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#define PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC 0x0f1c
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#define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31
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#define CPUID_BAYTRAIL 0x30670
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2012-10-13 02:19:30 +02:00
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/* Intel starts counting these generations with the integration of the DRAM controller */
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2013-06-20 18:05:06 +02:00
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#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
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2012-10-13 02:19:30 +02:00
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#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
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2014-11-05 03:18:44 +01:00
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#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */
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#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */
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2014-11-09 00:11:28 +01:00
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#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x0150 /* Ivy Bridge (Desktop) */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M 0x0154 /* Ivy Bridge (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3 0x0158 /* Ivy Bridge (Xeon E3 v2) */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c 0x015c /* Ivy Bridge (?) */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D 0x0c00 /* Haswell (Desktop) */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */
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2014-10-30 10:30:40 +01:00
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
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2015-05-15 04:58:33 +02:00
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#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */
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2012-07-21 04:36:47 +02:00
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2008-08-20 15:41:24 +02:00
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#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
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2010-10-24 15:50:13 +02:00
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#if !defined(__DARWIN__) && !defined(__FreeBSD__)
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2008-08-20 15:41:24 +02:00
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typedef struct { uint32_t hi, lo; } msr_t;
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2008-12-04 16:18:20 +01:00
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#endif
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2010-10-24 15:50:13 +02:00
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#if defined (__FreeBSD__)
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/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */
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#undef rdmsr
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#undef wrmsr
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#define rdmsr freebsd_rdmsr
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#define wrmsr freebsd_wrmsr
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typedef struct { uint32_t hi, lo; } msr_t;
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msr_t freebsd_rdmsr(int addr);
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int freebsd_wrmsr(int addr, msr_t msr);
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#endif
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2008-08-20 15:41:24 +02:00
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typedef struct { uint16_t addr; int size; char *name; } io_register_t;
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2011-03-18 23:08:39 +01:00
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void *map_physical(uint64_t phys_addr, size_t len);
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2009-09-01 11:52:14 +02:00
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void unmap_physical(void *virt_addr, size_t len);
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2008-08-20 15:41:24 +02:00
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unsigned int cpuid(unsigned int op);
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int print_intel_core_msrs(void);
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2015-10-10 13:20:32 +02:00
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int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file);
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2010-11-27 15:44:19 +01:00
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int print_pmbase(struct pci_dev *sb, struct pci_access *pacc);
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2008-08-20 15:41:24 +02:00
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int print_rcba(struct pci_dev *sb);
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inteltool: Add option to show differences in GPIO setup
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.
Here's a preview:
$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
========== GPIO DIFFS ===========
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
============= GPIOS =============
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000 (GPI_NMI_EN)
gpiobase+0x002a: 0x0000 (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)
Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 15:08:04 +02:00
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int print_gpios(struct pci_dev *sb, int show_all, int show_diffs);
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2008-08-20 15:41:24 +02:00
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int print_epbar(struct pci_dev *nb);
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int print_dmibar(struct pci_dev *nb);
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int print_pciexbar(struct pci_dev *nb);
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2012-01-08 15:27:18 +01:00
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int print_ambs(struct pci_dev *nb, struct pci_access *pacc);
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2015-01-03 02:52:10 +01:00
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int print_spi(struct pci_dev *sb);
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2015-05-20 14:04:41 +02:00
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int print_gfx(struct pci_dev *gfx);
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2015-10-10 13:20:32 +02:00
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void ivybridge_dump_timings(const char *dump_spd_file);
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