Commit Graph

17637 Commits

Author SHA1 Message Date
Zhao, Lijian 0f7885722e soc/apollolake/lpc_lib: Make cros compile pass
The print of size_t can pass upstream jenkins, but fails with CROS_SDK
enviornment, "%z" fits for size_t anyway.

Change-Id: Ic8dbab240463f2e484b73d55e21985fae2b0d9b7
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14835
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-19 03:47:08 +02:00
Jonathan Neuschäfer d4d3ecb551 jenkins: Run the romcc test suite
Change-Id: I467c56ffc632f58338cb3dbafade15acab5ee016
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14540
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-19 00:14:15 +02:00
Shunqian Zheng 462e14139e rockchip: rk3399: enable sdhci clk for emmc
If booting from sdcard/usb, kernel can't recognize the
/dev/mmcblk0.
Before kernel find it's root cause, we add this workaround
patch to enable clk for emmc.

BRANCH=none
BUG=chrome-os-partner:52873
TEST=boot from sdcard and check the /dev/mmcblk0 exists

Change-Id: Ie36cc6fdbc24db8c30984c02ccfe2f8aaaf30cd2
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 39b87ec3c73d6f56efc8c3f52b7ed759e548ee85
Original-Change-Id: I88a9cc2e3ea5a56aadfdbd94ef910daaf92a7eb7
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/341632
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14856
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18 20:23:42 +02:00
Lin Huang 2f7ed8d775 rockchip: rk3399: configure emmc clk
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz,
that is GPLL(594MHz) divided by 3.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard
TEST=LoadKernel faster, more than twice as I measured manually.

Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2
Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/339152
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14855
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18 20:23:18 +02:00
Gwendal Grignou 95b7a6c6db ec/google/chromeec/acpi: Add MKBP support
Allow EC to send an interrupt using ACPI SMI when a MKBP event
is available. This will be used by the sensor stack.

Update all ACPI branch except those without sensors with:
for i in $(find . -name ec.h -exec grep -l MAINBOARD_EC_SCI_EVENTS {} \+
| cut -d '/' -f 2 | grep -v -e cyan -e lars); do
  echo $i
  cd $i
  git diff ../lars/ec.h | patch -p 5
  cd -
done

BUG=b:27849483
BRANCH=none
TEST=Compile on Samus. Tested in Cyan branch.

Change-Id: I4766d1d56c3b075bb2990b6d6f59b28c91415776
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: d3b9f76a26397ff619f630c5e3d043a7be1a5890
Original-Change-Id: I56c46ee17baee109b9b778982ab35542084cbd69
Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/342364
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14854
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-18 20:22:38 +02:00
Vadim Bendebury ad6ee02146 rk3399: set proper configuration of SDMMC interface
For proper interface operation the drive strength on all pins is set
to 8 mA and all pull ups/pull downs disabled, this matches the current
kernel configuration.

BRANCH=none
BUG=chrome-os-partner:53257
TEST=it is possible to boot Chrome OS on Gru from various micro SD
     cards which were failing to boot before.

Change-Id: Ie43e52a52cd0513d48d0ecc8ac02fbb100baf9a4
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 6bb0549ed728ac3c5faab6cbe16e2487400e67ed
Original-Change-Id: I5180537d3ceb74a9a2f7b3982ca94d3e2daf0369
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/344491
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14853
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18 20:21:32 +02:00
Vadim Bendebury a9cd4a2f11 rk3399: add GPIO register definitions for SDMMC0
The code needs to be able to set drive strength for the pins used for
SDMMC0 interface. This patch adds the definitions for the two
registers, as per page 378 of the RK3399 TRM Part 1.

Instead of calculation of the reserved range size just use known
offsets of the registers included in the structure.

BRANCH=none
BUG=chrome-os-partner:53257
TEST=with the upcoming driver change it is possible to boot chrome OS
     on Gru from various micro SD cards which were failing before.

Change-Id: I63bf37432ec7f3bdf7e9c6a79d51c31de122dae9
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: c6d6dc5e5e6cc81c173603d4eb21ae803a47815d
Original-Change-Id: Ibe7584e77b446435ab1264dcf8fc8bfe0c50438e
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/344490
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14852
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18 20:21:03 +02:00
Vadim Bendebury 2832c4125b gru: set correct gpio for SD card detect
The only outlier at this time is Kevin rev 0, treat it specially, the
rest of the targets use the same GPIO.

BRANCH=none
BUG=none
TEST=gru still boots off SD card just fine

Change-Id: Ic603093a990d27166b16175db3303f155b4775aa
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 5788c5add1d1f803e7b22fb53215b6003ac04d03
Original-Change-Id: Ic5183f08dd1119f9588f243bd9e9c080d84687f9
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/344151
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14851
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18 20:20:30 +02:00
Lin Huang 728fffd33c Gru: support 4GB sdram on gru
now we use 4GB sdram on gru board, enable it.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot from kevin board

Change-Id: Icc483a8ba91c5deea85e6e4009a8a132851b1853
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: efa94aee02bedf51d73c91059b06afcbb1320282
Original-Change-Id: I26f77ff4ad9b2aa35ab5ff50f23984796f4f06bc
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342585
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14850
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18 20:20:03 +02:00
Lin Huang 4b9cd535e4 rockchip: rk3399: improve sdram driver
improve rk3399 sdram drvier, so we can support DDR3,
and check the cs training result, so we make sdram
work more stable.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot from kevin, do memtester in kernel and pass

Change-Id: I508bf26fb8163bab2d725a91ead929df585e04a7
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 4d83a87c459167145b7260f9af5c0380caddc056
Original-Change-Id: Id385f1343804a829b6589f89f4cfbb6565d41417
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/342664
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14849
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18 20:19:44 +02:00
Shunqian Zheng f4181ce3b3 rockchip: rk3399: add tsadc driver
This patch configures clock for tsadc and then
makes it in automatic mode to generate TSHUT when
CPU temperature is higer than 120 degree Celsius.

BRANCH=none
BUG=chrome-os-partner:52382,chrome-os-partner:51537
TEST=Set a lower tshut threshold(45C), run coreboot and check
     that coreboot reboot again and again.

Change-Id: I0b070a059d2941f12d31fc3002e78ea083e70b13
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 05107bd6a3430e31db216c247ff0213e12373390
Original-Change-Id: Iffe54d3b09080d0f1ff31e8b3020d69510f07c95
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342797
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/14848
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18 20:19:29 +02:00
Shunqian Zheng 307ca379d1 rockchip: revert the common tsadc header
The tsadc of rk3288 and rk3399 are similar but not enough
to share the same common driver, and we also decide to add a
polarity setting for mainboards on rk3399 tsadc header.
So we'd better split the tsadc header for each SoC.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=build veyron_jerry

Change-Id: I41f08965e6d7ce16da1754d4d2512c826cf8aff5
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: b36ee54c4146623bcacd83fe7d55a4fc78bae792
Original-Change-Id: I629599f9e30d863cabf764e1372c38f0f39d5480
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342796
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14847
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18 20:14:39 +02:00
Shunqian Zheng c7f32a5bb4 rockchip: rk3399: add routines to set vop clocks
Let vop aclk sources from CPLL, and vop dclk from NPLL.

The dclk freq is decided by the edid mode pixel_clock which
may require high accuracy like 252750KHz. The pll_para_config()
can calculate the dividers for PLL to output desired clock.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=check display with the other patches

Change-Id: I12cf27d3d1177a8b1c4cfbd7c0be10204e3d3142
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 0f019b055fffebe9ea3928aae1e25b0ad4feef81
Original-Change-Id: Icef58f87041905961772b69c6b8170d5a866a531
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342335
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: https://review.coreboot.org/14846
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18 20:14:21 +02:00
Lee Leahy 2d96be6484 Documentation/Intel: Update the documentation
index.html:
* Separate the sections on the main page
* Move the documentation links to the main page
* Add links for FSP 1.0 and 2.0 specifications
* Add link for UEFI specifications
* Add link to MinnowBoard MAX coreboot

fsp1_1.html:
* Use Integration instead of Documentation

SoC/quark.html:
* Move documentation to main page
* Update build instructions for CorebootPayloadPkg
* Remove FatPkg since it is now part of edk2 tree
* Add source location for QuarkFspPkg
* Add build instructions for QuarkFspPkg

TEST=None

Change-Id: I48bd1bf98a6d8bc43bdd3b4c51dfd119a1e0f61b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14882
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18 19:47:16 +02:00
Kyösti Mälkki 08311f5033 AGESA vendorcode: Build a common amdlib
Having CFLAGS with -Os disables -falign-function, for
unlucky builds this may delay entry to ramstage by 600ms.
Build the low-level IO functions aligned with -O2 instead.

Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 10:44:43 +02:00
Kyösti Mälkki 82171ea0ff AGESA vendorcode: Move compiler class definition
Change-Id: Ia4cef7d584e43f1911db2f81d8b86ed406b75aad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14786
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-18 10:44:22 +02:00
Andrey Petrov f87275f821 soc/intel/apollolake: Enable ACPI PM1 timer emulation
Enable emulation for ACPI PM1 timer. This is needed by FSP-M
MemoryInit.

Change-Id: I7a441f5f1673e6430697615ae7251da948e77548
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14821
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 07:06:39 +02:00
Andrey Petrov 664d585882 soc/intel/apollolake: Remove hardcode for TCO watchdog timer
Change-Id: Ie528b0ee3d447dcb819ccb7c0f832885da0f4257
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14820
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18 07:05:32 +02:00
Andrey Petrov 0e46307574 soc/intel/apollolake: Work around FSP-M CAR layout
As of now FSP-M can not be relocated and it can not be instructed
to use a specific resource for temporary memory. As result coreboot
is forced to use CAR layout dictated by default FSP-M configuration.

Change CAR size to 1MiB, link romstage at such CAR address so it
doesn't overlap with FSP-M's default heap/stack.

Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14804
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18 07:05:00 +02:00
Andrey Petrov 5ede3d8cce soc/intel/apollolake: Do not use StackBase FSP-M parameter
Currently, StackBase field doesn't work and changing it from default
value leads to crash.

Change-Id: Id3f3ea9a834d0c04a8381938535109d6a729cca2
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14803
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 07:04:36 +02:00
Andrey Petrov 9be1a115f1 drivers/intel/fsp2_0: Add recipes for FSP blobs in CBFS
Add recipes that insert FSP blobs into CBFS and get rid of
CBFS names hardcoding.

Change-Id: I350abeffc4d23e45e339464d036716ecdb2ba83a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-18 07:04:10 +02:00
Andrey Petrov 868679fe96 soc/intel/apollolake: Take advantage of common opregion code
Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14807
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 07:03:44 +02:00
Andrey Petrov dc4ae11366 soc/intel/common: Add IGD OpRegion support
Add helper function that fills OpRegion structure based on
VBT file content and some reasonable defaults.

Change-Id: I9aa8862878cc016a9a684c844ceab390734f3e84
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 07:03:13 +02:00
Andrey Petrov 060b215fa7 soc/intel/common: Add utility to load VBT file
Change-Id: I8d3d47ca2fc1fc4c10e61c04b941b6378b9c0f80
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14815
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 07:02:43 +02:00
Aaron Durbin 493ec92eb3 util/cbfstool: allow option to honor FSP modules' linked address
If '-b' isn't passed when adding an FSP file type to CBFS allow
the currently linked address to be used. i.e. don't relocate the
FSP module and just add it to CBFS.

Change-Id: I61fefd962ca9cf8aff7a4ca2bea52341ab41d67b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14839
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-18 03:19:12 +02:00
Lee Leahy 15843bdad0 mainboard/intel/galileo: Add I2C chip initialization
Add I2C chip initialization for the Galileo boards.

TEST=Build and run on Galileo Gen2

Change-Id: Ib5284d5cd7a67de2f3f98940837ceb2aa69af468
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14829
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18 00:58:06 +02:00
Lee Leahy ac690b1e9b soc/intel/quark: Add I2C support
Add the I2C driver.

TEST=Build and run on Galileo Gen2

Change-Id: I53fdac93667a8ffb2c2c8f394334de2dece63d66
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14828
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18 00:57:48 +02:00
Jonathan Neuschäfer 0e962eeb93 board_status: Abort early if the coreboot image doesn't exist
Change-Id: I274c990e69634ebcb9dd77470cbf1515281de312
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14683
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18 00:17:18 +02:00
Lee Leahy 5d9f5ff910 soc/intel/quark: Fix spelling error
Change Memroy to Memory in comment.

TEST=None

Change-Id: Ic57fcf962be6a302dcd7b52b9256a182577e734b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14881
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 23:32:33 +02:00
Lee Leahy 3f0fe68c4b soc/intel/quark: Perform GPIO initialization
Set the base address and enable the GPIO and legacy GPIO controllers.
Call the mainboard routine to initialize the GPIO controllers.

TEST=Build and run on Galileo Gen2

Change-Id: I06aed5903d6655d2a0948fb544cf9e0db68faa26
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14827
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 23:30:52 +02:00
Lee Leahy 274d20a065 mainboard/intel/galileo: Add GPIO initialization
Add Kconfig to configure coreboot for a specific Galileo board.
Configure the GPIOs for the specific Galileo board.

TEST=Build and run on Galileo Gen2

Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14826
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 23:30:09 +02:00
Jonathan Neuschäfer 0ba307f0fe acpigen: Fix ?: operator confusion
strlen(string) was on the "negative" side of the selection operator, the
side where string is NULL.

Change-Id: Ic421a5406ef788c504e30089daeba61a195457ae
Reported-by: Coverity Scan (CID 1355263)
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-17 23:27:02 +02:00
Julius Werner 2296479dfd libpayload: cbfs: Add cbfs_handle API for more fine-grained accesses
The libpayload CBFS APIs are pretty old and clunky, primarily because of
the way the cbfs_media struct may or may not be passed in and may be
initialized inside the API calls in a way that cannot be passed back out
again. Due to this, the only real CBFS access function we have always
reads a whole file with all metadata, and everything else has to build
on top of that. This makes certain tasks like reading just a file
attribute very inefficient on non-memory-mapped platforms (because you
always have to map the whole file).

This patch isn't going to fix the world, but will allow a bit more
flexibility by bolting a new API on top which uses a struct cbfs_handle
to represent a found but not yet read file. A cbfs_handle contains a
copy of the cbfs_media needed to read the file, so it can be kept and
passed around to read individual parts of it after the initial lookup.
The existing (non-media) legacy API is retained for backwards
compatibility, as is cbfs_file_get_contents() (which is most likely what
more recent payloads would have used, and also a good convenience
wrapper for the most simple use case), but they are now implemented on
top of the new API.

TEST=Booted Oak, made sure that firmware screens and software sync
worked okay.

Change-Id: I269f3979e77ae691ee9d4e1ab564eff6d45b7cbe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14810
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-17 22:48:28 +02:00
Stefan Reinauer 4bab6e79b0 intel/sch: Merge northbridge and southbridge in src/soc
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-05-17 21:38:17 +02:00
Lee Leahy 083da160af soc/intel/quark: Add GPIO register access
Add register access routines for the GPIO and legacy GPIO controllers.

TEST=Build and run on Galileo Gen2

Change-Id: I0c023428f4784de9e025279480554b8ed134afca
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14825
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 20:26:28 +02:00
Lee Leahy 4c56a58f63 soc/intel/quark: Add LPC symbols
Add LPC_DEV and LPC_FUNC symbols

TEST=Build and run on Galileo Gen2

Change-Id: I8485e2671af439f766228d4eaf9677c2ff8ff3f6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14880
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 20:18:04 +02:00
Lee Leahy 76684bf75b soc/intel/quark: Reformat include/soc/pci_devs.h
Replace # define with #define
Align the right hand column to prepare for further expansion

TEST=Build and run on Galileo Gen2

Change-Id: Ie4d9fb56d52d7291be5523d31c1d3aa51f94dcd6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14879
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 20:16:59 +02:00
Lee Leahy d3989a26c1 drivers/intel/fsp1_1: Simplify union references
Simplify the union references to enable Coverity to properly process
the routine.

Found-by: Coverify CID 1349854

TEST=Build and run on Galileo Gen2

Change-Id: I667b9bc5fcde7f68cb9b4c8fa85601998e5c81ff
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14870
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 20:16:24 +02:00
Lee Leahy 00c35c1a98 drivers/intel/fsp1_1: Replace for/break with returns
Coverity does not like the use of for/break, switch to using returns
instead.

Found-by: Coverity CID 1349855

TEST=Build and run on Galileo Gen2

Change-Id: I4e5767b09faefa275dd32d3b76dda063f7c22f6f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14869
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 20:15:59 +02:00
Lee Leahy c1cbc605cd soc/intel/quark: Add Ioh.h from EDK-II
Add Ioh.h from EDK-II to enable easy comparisons between EDK-II and
coreboot implementations.

TEST=Build and run on Galileo Gen2

Change-Id: I9320101a4a2c16ed18f682f3d04623c54afb52fd
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14824
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-05-17 19:41:21 +02:00
Lee Leahy 016d8f75d8 drivers/intel/fsp2_0: Fix array indexing error
Don't allow an array index of 2 to be processed by the code referencing
the array.

Found-by: Coverity CID 1353337

TEST=None

Change-Id: I586ca14416a6e40971f8f6f4066fbdb4908ca688
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14868
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-17 18:49:27 +02:00
Aaron Durbin 451b1e0b9d mainboard/google/reef: add first pass of full pad configuration
This is an initial stab of configuring the reef pads.

Change-Id: I8d8060745af6fbada268c6c6f3492b985ddf9eb8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14831
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
2016-05-17 06:18:17 +02:00
Paul Kocialkowski 1811768c64 vboot: Call verification_should_run directly in the if statement
Using a dedicated variable is slightly less readable and makes the code
less consistent, given that other test functions are called directly in
the if statements.

Change-Id: If52b2a4268acb1e2187574d15cc73a0c1d5fe9bb
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14817
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-16 22:37:50 +02:00
Duncan Laurie abe2de8854 acpigen: Add functions to generate _STA() and _PRW()
Add helper functions for generating some common objects:

acpigen_write_STA(status) will generate a status method that will
indicate the device status as provided:
  Method (_STA) { Return (status) }

Full status byte configuration is possible and macros are provided for
the common status bytes used for generated code:
ACPI_STATUS_DEVICE_ALL_OFF = 0x0
ACPI_STATUS_DEVICE_ALL_ON  = 0xF

acpigen_write_PRW() will generate a Power Resoruce for Wake that describes
the GPE that will wake a particular device:
  Name (_PRW, Package (2) { wake, level }

Change-Id: I10277f0f3820d272d3975abf34b9a8de577782e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14795
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-16 19:55:59 +02:00
Duncan Laurie f7c3876c28 acpigen: Add an abstracted integer output method
In order to produce smaller AML and not rely on the caller to size the
output type appropriately add a helper function that will output an
appropriately sized integer.

To complete this also add helper functions for outputting the single
OpCode for Zero and One and Ones.

And finally add "name" variants of the helpers that will output a
complete sequence like "Name (_UID, Zero)".

Change-Id: I7ee4bc0a6347d15b8d49df357845a8bc2e517407
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14794
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-16 19:55:33 +02:00
Duncan Laurie 56b69aa9c7 acpigen: Add helper functions for strings
Add helper function to emit a string into the SSDT AML bytestream with a
NULL terminator.  Also add a helper function to emit the string OpCode
followed by the string itself.

acpigen_emit_string(string)  /* Raw string output */
acpigen_write_string(string) /* OpCode followed by raw string */

Change-Id: I4a3a8728066e0c41d7ad6429fad983e6ae6962fe
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14793
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-16 19:51:58 +02:00
Duncan Laurie 9ccae7558d acpigen: Add helpers for word/dword output
Add helpers for writing word and dword values in acpigen and use them
throughout the file to clean things up:

acpigen_emit_word - write raw word
acpigen_emit_dword - write raw dword
acpigen_write_word - write word opcode and value

Change-Id: Ia758d4dd25d0ae5b31be7d51b33866dddd96a473
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-16 19:51:36 +02:00
Duncan Laurie 4650f5baff sconfig: Add a new generic device type
Add support for a basic generic device in the devicetree to bind to a
device that does not have a specific bus, but may need to be described
in tables for the operating system.  For instance some chips may have
various GPIO connections that need described but do not fall under any
other device.

In order to support this export the basic 'scan_static_bus()' that can
be used in a device_operations->scan_bus() method to scan for the generic
devices.

It has been possible to get a semi-generic device by using a fake PNP
device, but that isn't really appropriate for many devices.

Also Re-generate the shipped files for sconfig.  Use flex 2.6.0 to avoid
everything being rewritten.  Clean up the local paths that leak into the
generated configs.

Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14789
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-16 19:49:59 +02:00
Duncan Laurie b7ce5fe311 sconfig: Add 10bit addressing mode to i2c device type
Use the second token for an i2c device entry in devicetree.cb to
indicate if it should use 10-bit addressing or 7-bit.  The default if
not provided is to use 7-bit addressing, but it can be changed to
10-bit addressing with the ".1" suffix.  For example:

chip drivers/i2c/generic
  device i2c 3a.1 on end
end

Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14788
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-16 19:49:46 +02:00
Duncan Laurie b1fb0152bf sconfig: Allow strings in devicetree.cb
Currently you cannot assign a string to a register in devicetree because
the quotes are removed when parsing and the literal is assigned directly.

Add a parse option for two double-quotation marks to indicate a string
and return a quoted literal that can be assigned to a register with a
'const char *' type.

Example:

chip drivers/i2c/generic
  register "hid" = ""INT343B""
  register "uid" = "1"
  device i2c 15 on end
end

Change-Id: I621cde1f7547494a8035fbbab771f29522da1687
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14787
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-16 19:49:37 +02:00