The mainboard was accidently added due to bad rebase.
Change-Id: Ie7215e551651dbbc8d92316c48e455405923a30b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36077
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This uses less lines, is the original Markdown syntax, and for short
blocks better readable.
Change-Id: Id96ad0f65980dfb943eef3cde5626d56f97622f9
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35729
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Run
- make -C util/docker doc.coreboot.org to build the docker image
- make -C util/docker docker-build-docs to build the documentation
- make -C docker-livehtml-docs to serve autoupdated documentation over
http://0.0.0.0:8000
Change-Id: Ic07f216f8d90d6e212383250b852dc91575304c3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36104
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This config is a slightly stripped configuration of the Chromium OS
configuration used in production. Apparently the bootblock fills up
faster than usual on this device, resulting in address overflows.
Add this config here so we'll notice early in the future.
Change-Id: I3145bba63d32ddb9d00fd98d3cb774bf9ddd69a6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36923
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By removing this code, we get approximately back to
where the board was before the fmap cache feature
was added, which is small enough for the Chromium OS
default configuration for the board to fit into the
32KB that the bootblock can use on the chipset again.
Change-Id: I52c0c30a14929913ded144bf086c12938e9c2699
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Correct what looks to be errant characters in the makefile variable for
the Gigabit Ethernet Controller. This should have no effect on any
mainboards as none select the HUDSON_GEC_FWM symbol.
Change-Id: Icb861d872973aaf2b653440cae00057d5ad89b20
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Due to the way CAR teardown is handled in FSP 1.0, the results of
car_get_var_ptr() aren't always reliable, which can break things when
running with FMAP cache. It might be possible to fix this but would make
the code rather complicated, so let's just disable the feature on these
platforms and hope they die out soon.
Also allow this option to be used by platforms that don't have space for
the cache and want to save a little more code.
Change-Id: I7ffb1b8b08a7ca3fe8d53dc827e2c8521da064c7
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With GCC 9.x has a new warning *address-of-packed-member*.
> -Waddress-of-packed-member
>
> Warn when the address of packed member of struct or union is
> taken, which usually results in an unaligned pointer value.
> This is enabled by default.
This results in the build errors below, for example, with GCC 9.2 from
Debian Sid/unstable.
src/southbridge/intel/common/spi.c: In function 'spi_init':
src/southbridge/intel/common/spi.c:298:19: error: taking address of packed member of 'struct ich7_spi_regs' may result in an unaligned pointer value [-Werror=address-of-packed-member]
298 | cntlr->optype = &ich7_spi->optype;
| ^~~~~~~~~~~~~~~~~
Therefore, explicitly disable the warning.
Change-Id: I01d0dcdd0f8252ab65b91f40bb5f5c5e8177a293
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36940
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
buffer_to_fifo32() is a simple wrapper to buffer_to_fifo32_prefix(), but
unfortunately its arguments are swapped. This patch fixes the issue.
Change-Id: I6414bf51dd9de681b3b87bbaf4ea4efc815f7ae1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36942
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves the traditional POSIX stdbool.h definitions out from
stdint.h into their own file. This helps for using these definitions in
commonlib code which may be compiled in different environments. For
coreboot everything should chain-include this stuff via types.h anyway
so nothing should change.
Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch changes the ipq40xx Makefile.inc to follow established
coreboot practice of calling Python scripts directly rather than
invoking the 'python' interpreter explicitly. This has the added effect
of honoring the scripts shebang (which in this case is set to
'python2').
Change-Id: If96e8313527c411ef1bb6386e03b6a209c750131
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some types of Undefined Behavior can be determined statically at compile
time and gcc now has a set of flags that make it emit warnings in that
case instead of doing the __builtin_trap() / optimize / UD2-opcode dance
that silently breaks the resulting binary.
BUG=chromium:958270
BRANCH=none
TEST=abuild passes (probably not)
Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
IASL reports unnecessary/redundant use of offset operator. These
messages are only masking usefull messages.
Add -vw 2158 so this message isn't reported.
BUG=N/A
TEST=build
Change-Id: Ie8507d3b3cb6f2e75cb87cd3e4bcc4280df27f77
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36857
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid
probing by the MRC. We can do that for all boards instead, based on the
devicetree setting.
Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The integrated GbE port is toggled via the Backed-Up Control (BUC)
register. We already disable it according to the devicetree setting
but never enabled it. This could lead to the confusing situation
that it was disabled before (different build, vendor BIOS, etc.)
but shouldn't be anymore.
As we need a full reset after enabling GbE, do it in early PCH init.
Change-Id: I9db3d1923684b938d2c9f5b369b0953570c7fc15
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The BUC register is actually only 8 bits wide and setting bit 5
(disabling GbE) is already done by generic code.
Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Don't overwrite the LPC decode config of the generic PCH code, move
UART init into bootblock_mainboard_early_init() and don't enable the
IOAPIC, which is already done by generic code.
Change-Id: I90d090f5bff29174e68981fea3c3f04c666b1d28
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The BUC register is actually only 8 bits wide and setting bit 5
(disabling GbE) is already done by generic code.
Change-Id: I4b8e14606c319e8bfc48d6757087f28af1bd5dfb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Only set LPC decode bits that the generic PCH code doesn't set yet. And
don't enable the IOAPIC, which is already done by generic code.
Change-Id: I9d2f6a9ad3f5d83573e07596f2763edc75f4ee64
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This bit is already cleared by a reset.
Change-Id: Ib71496011c9621476a7327ba309f367c7fa971e4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This bit is used to indicate xHCI routing across reboots. If anything,
coreboot should act on it, not set it during boot. ASL code would be
supposed to set it.
Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The generic PCH code already enables a superset of LPC decoding. Move
UART setup to bootblock_mainboard_early_init() where it is expected.
Last but not least, remove an odd write to BUCs (RCBA+0x3414) and
beyond, as it's an 8-bit register and shouldn't be bluntly zeroed.
Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
mainboard_pch_lpc_setup() and mainboard_late_rcba_config() did 4
things here on top of the generic PCH code:
1. Enabling LPC decoding for gameports. It seems unlikely
that anything is using these ports and there is no code
to support gameports.
2. Decoding of COM3 instead of COM2. What COM?
3. Premature locking of ETR3/global reset. Bad idea.
4. Disabling the GbE port in BUC. Already done by PCH code.
Change-Id: Ie92dbf5c6813435995c4d24ed807ffc8d125953a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There is some overlap between romstage and bootblock.
LPC setup and BAR initialization is now done twice.
The rationale is that the romstage should not depend too
much on the bootblock, since it can reside in a RO fmap
region.
Enabling the console will be done in a followup patch.
Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The romstage default is to set stack guards at 0x2000 below end
of stack. The code is now overwrites some of the stack guards
so increase the stack size to a comfortable 0x2800.
Change-Id: I91f559383a987241b343e743d11291f2c100f7f5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This also changes the name to mainboard_pch_lpc_setup to better
reflect that it is an optional mainboard hook.
This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.
Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This also changes the name to mainboard_late_rcba_config to better
reflect what it does.
This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.
Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This always builds the usb debug callback functions when implemented.
They get garbage collected if CONFIG_USBDEBUG is not set.
Change-Id: I33051df583645cd00d08e06774383763172d5822
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The declarations in usb_debug.c needs to be guarded in order to not
conflict with other chipsets.
Change-Id: I84c3401b9419f2878c2cfdf81147fa854018f9ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36878
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds an empty weakly linked default. The rationale behind this
change is that without the callback some features might not work
but that the result is likely still able to boot, so it can be made
optional.
Change-Id: I62c8010aa81fc45d208e9293feb2f45b45f34a82
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In order to always show the bootlogo very early in coreboot we need the
option to always enable the display when VBOOT is enabled.
To do this a config option is added to make sure this functionality can
be provided without interfering with systems that require the standard
VBOOT display handing.
BUG=N/A
TEST=tested on facebook fbg1701.
Change-Id: I3ffaac85d2082717bb9608d536f7cec66a583789
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some special keys emit a prefix scan code 0xE0. We will ignore all
these except for the power button, F12 and cursor keys on drallion.
Media key mapping is set in depthcharge and will be sent to libpayload
keyboard driver. Whichever board requires this change will update its own
media key mapping.
BUG🅱️139511038
TEST=boot in recovery mode, press F12 to go to diagnostic mode and power
button to confirm. Also in recovery mode left arrow, right arrow, up arrow,
down arrow changes the language on the firmware screen.
Change-Id: I1c11939d18391bebe53ca21cf33a096ba369cd56
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36654
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Leave more space for PreRAM memconsole especially for seeing complete
logs when doing DRAM full calibration (that outputs in 200+k to UART):
- Shrink Full-K mem space (the ELF blob today needs ~132K)
- Move PRERAM_CBFS_CACHE to L2C since it's no used after DRAM is up
- Shrink TIMESTAMP to 1k (all other non-MTK ARM SOCs use only 1k)
- Incease PRERAM_CBMEM_CONSOLE to 63k-4
- Reordered few sections to align at better locations
BUG=b:144542023
TEST=emerge-kukui coreboot chromeos-bootimage; boot and see logs
Change-Id: I8696fb01653c0a581cf62e687dc523cb6fed9a32
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Setting GPP_A10 to NC now that older boards are deprecated and this
GPIO is not in use anymore.
BUG=b:142056166
BRANCH=hatch
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: If8a249a3dcba90bb4ccb5e3f02595e680f789f93
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36869
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The eltan security items ended up in the chipset menu which is not
desired. Now the eltan security option (when enabled in mainboard) shows
up in the security menu.
BUG=N/A
TEST=build
Change-Id: I3b2aa3836e8d9a3242c6d1f3ba7b7821a5cfb9d3
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
These mainboard don't feature a SPI flash. The SPI init code
will timeout on probing for a SPI flash which takes a lot of time.
Not including all SPI drivers also lightens the uncompressed ramstage
of about 17K or 7K compressed.
Change-Id: Icc7bf62d56fc2ef38854402e658830b8d59c737f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36870
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On devices lacking SPI boot devices there is a hefty timeout
penalty on probing for flash chips and this code would not
be useful anyway.
Change-Id: I0bec11372ef54c1e1e611b81f7013932257f4ca6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36868
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Patrick Rudolph