Commit Graph

36623 Commits

Author SHA1 Message Date
Angel Pons dd7470cb7e mb/asrock/b85m_pro4: Factor out common MRC settings
These settings are the same on all boards. Since the other boards
currently overwrite the struct contents, it doesn't make a difference.
To ease review, the same settings will be dropped from other boards in
separate commits, one board at a time.

Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12 09:59:34 +00:00
Angel Pons 45f448f4a4 haswell: Relocate `mainboard_romstage_entry` to northbridge
This is what sandybridge does, and if done properly allows factoring out
common settings. Said refactoring will be handled in subsequent commits.

Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12 09:58:33 +00:00
Angel Pons c05c2b3fb2 haswell boards: Fix writes to 16-bit DxxIR registers
The DxxIR (Device xx Interrupt Route) registers in RCBA are 16-bit wide,
so do not use 32-bit operations to program them.

Note that the DxxIP (Device xx Interrupt Pin) registers are 32-bit, so
using 32-bit operations on them is correct.

Change-Id: I9699b98d5fcd26b2c710bf018f16acc65dcb634e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12 09:57:34 +00:00
Angel Pons 14c4f4f43c haswell: Drop `struct romstage_params` type
It only contains a pointer to another struct. Flatten it.

Change-Id: Iab427592c332646e032a768719fc380c5794086b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12 09:56:56 +00:00
Angel Pons 6eea191511 haswell: Make `copy_spd` a weak function
Instead of using function pointers, we can use weak functions. So, drop
the pointer from `romstage_params`, leaving `pei_data` as the only
remaining member. This will be cleaned up in a follow-up commit.

Change-Id: I3b17d21ea7a650734119a5cab4892fcb158b589d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-12 09:54:50 +00:00
Angel Pons 517bc99db1 sb/intel/i82801dx: Correct SMBUS_IO_BASE value
The current value of 0x1000 would overlap the first PCI bridge IO
window. As we commonly reserve IO range 0x0 .. 0x1000 for LPC and
integrated device use, change SMBUS_IO_BASE to 0x400. This is the
prevalent value among Intel southbridges, too.

Change-Id: I5c299f001f9012d6766b155a2f5def5cff6e88d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43023
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11 23:11:33 +00:00
Angel Pons a0a94d8c64 drivers/usb/ehci_debug.c: Drop preprocessor usage
There's no need to use ugly preprocessor here when regular C conditional
statements will work just fine.

Change-Id: I5abd445a335b43fb95e4df087d44e82c3f44349b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-07-11 22:26:42 +00:00
Angel Pons 54ff67c698 mb/asrock/b85m_pro4: Reduce Super I/O ACPI code
We only need ACPI for the PS/2 devices. Plus, the NCT6776 ACPI code
makes Windows BSOD with STOP 0xA5 (ACPI_BIOS_ERROR), which is bad.

Change-Id: I4cfad012684264b21284674e8e3713a5d8bb37be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42430
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11 22:24:35 +00:00
Angel Pons 73fa035b20 nb/intel/haswell: Add `mb_late_romstage_setup` function
This function is called at the end of `romstage_common`. Only one board
makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call
it after `romstage_common` has done nearly everything.

Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43094
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11 20:49:25 +00:00
Angel Pons c06648b8c1 mb/google/beltino: Move Super I/O init to bootblock
Also remove an unneeded `pch_enable_lpc` function call.

Change-Id: I83158a655670d4e6cd91f6bf3332d1b6f9f655d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-07-11 20:46:06 +00:00
Kyösti Mälkki 2446c1e9e9 arch/x86: Drop CBMEM_TOP_BACKUP
Code has evolved such that there seems to be little
use for global definition of cbmem_top_chipset().
Even for AMD we had three different implementations.

Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11 14:48:25 +00:00
Anna Karas bd5c721f6b src/lib: Remove redundant code in imd.c
Get rid of duplicated "if" statement in imdr_create_empty().

Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: I80c074d09f222086092478f8fd3ac665235ebb31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-11 14:10:19 +00:00
Angel Pons 81c9c275e6 nb/intel/i945: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I5e33526a02872c14e9fa37a485d2f93dea8b088f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-11 11:19:27 +00:00
Angel Pons fc5469c345 drivers/i2c/w83793: Drop dead code
Nothing selects this driver. Drop it before it grows moss.

Change-Id: I4d0e678a8725c1fdf9263b9fae4e4fb6bb5ab4de
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43268
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11 00:00:30 +00:00
Angel Pons 000784bc84 nb/amd/agesa/agesa_helper.h: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: Icb98f3535f6c5f51081fc82262f6413f4b1a5733
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43261
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 23:58:44 +00:00
Angel Pons 93fe3727e0 sb/amd/cimx/sb800: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I2a244436adb8f41e4246aad7e3bfaf0986f2d832
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43260
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 23:58:24 +00:00
Angel Pons 32f90d8c68 vc/amd/pi/00660F01: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I14c575ac20cd94af1cfbb1204e2923149ef2920d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43259
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 23:58:12 +00:00
Angel Pons 99bd1ab00d mb/hp/abm: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I2a97954a36e5af37dc3c379c39afa24030daceea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-10 23:57:46 +00:00
Raul E Rangel 0357ab7b8f soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCI
This provides the functionality to provide the GPE to the pci_xhci
driver.

BUG=b:154756391, b:160651028
TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and
verify GPE is set. Resume using a USB keyboard.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-10 23:35:41 +00:00
Raul E Rangel 62c583622d drivers/usb/pci_xhci: Add Picasso xHCI controllers
BUG=b:154756391
TEST=Dump ACPI table and see xHCI nodes being created.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1541dc8ebf314a204708a7767f30f4db72990907
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43331
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 23:34:30 +00:00
Raul E Rangel 4489cb5284 soc/amd/picasso: Delete partially implemented usb implementation
There is now a generic xhci driver we can use to generate the xHCI ACPI
nodes.

BUG=b:154756391
TEST=Boot trembyle and look at ACPI table

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41901
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 23:33:05 +00:00
Raul E Rangel 1a31b103c7 drivers/usb/pci_xhci: Add a driver to generate xHCI ACPI nodes
We can use xhci_for_each_ext_cap to inspect the xHC so we generate the
correct number of device nodes.

    Scope (\_SB.PCI0.PBRA)
    {
        Device (XHC1)
        {
            Name (_ADR, 0x0000000000000004)  // _ADR: Address
            Method (_STA, 0, NotSerialized)  // _STA: Status
            {
                Return (0x0F)
            }

            Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
            {
                0x1F,
                0x03
            })
            Device (RHUB)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Device (HS01)
                {
                    Name (_ADR, 0x01)  // _ADR: Address
                }

                Device (HS02)
                {
                    Name (_ADR, 0x02)  // _ADR: Address
                }

                Device (SS01)
                {
                    Name (_ADR, 0x03)  // _ADR: Address
                }
            }

            Name (_S0W, Zero)  // _S0W: S0 Device Wake State
            Name (_S3W, 0x04)  // _S3W: S3 Device Wake State
            Name (_S4W, 0x04)  // _S4W: S4 Device Wake State
        }
    }

BUG=b:154756391
TEST=Boot trembyle and look at ACPI table. See all xHCI nodes.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I44ebaef342e45923bc181ceebef882358d33f0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41900
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 23:32:16 +00:00
Raul E Rangel fc06af867e soc/amd/picasso: Add missing include to smi.h
BUG=b:154756391
TEST=Don't see build failure.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I36b81643c29ec1e7978d521206fbc366060ab286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43330
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 22:52:44 +00:00
Raul E Rangel f261e8183f mb/google/zork: Rename get_gpe_table to variant_gpe_table
This matches the other methods.

BUG=b:154756391
TEST=Build trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ba1fc5756c17da4dc1727425af17c4582c01a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-10 22:51:40 +00:00
Raul E Rangel 1c0b9f25a1 include/acpi/acpi.h: Add ACPI_NAME_BUFFER_SIZE
ACPI names can only be 4 characters long. Define a constant that defines
the size of the name + the NUL terminator.

BUG=b:154756391
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iad230c029f324005620ddad66c433ada26be78cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43329
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 22:50:19 +00:00
John Zhao f6f1f734ee soc/amd/picasso: Avoid NULL pointer dereference
Coverity detects dereferencing a pointer that might be "NULL" when
calling acpigen_write_scope. Add sanity check for scope to prevent
NULL pointer dereference.

Found-by: Coverity CID 1429980
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I6214fb83bccb19fe4edad65ce6b862815b8dcec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42837
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 17:33:39 +00:00
Nick Vaccaro 7b1cb0d603 mb/google/volteer: remove ripto variant
BUG=b:160711124
TEST="FW_NAME=ripto emerge-volteer coreboot chromeos-bootimage"
and verify that the build does not fail.

Change-Id: Ic132256a192b8cb77662963bea844f193eb912d9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-10 16:25:42 +00:00
Furquan Shaikh 0c707d4dbc soc/amd/picasso: Add PCI driver for data fabric devices
Data fabric devices are PCI devices which support PCI configuration
space but do not require any MMIO/IO resources. This change adds a PCI
driver for the data fabric devices which only provides device
operations for adding node to SSDT and returning the ACPI name for the
device.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-10 16:00:20 +00:00
Furquan Shaikh cff479e930 soc/amd/picasso: Add driver for handling PCIE GPP bridges
This change adds a driver pcie_gpp.c which provides device_operations
for external and internal PCIe GPP bridges. These device operations
include standard PCI bridge operations as well as operations for
generating ACPI node for the device and returning appropriate ACPI
name for it.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-10 15:59:03 +00:00
Raul E Rangel 5bb926e3c9 arch/x86/exception: Print stack on exception
It's useful to see the stack when an exception happens so you can see
the variables on the stack, and also manually recreate the back trace.

If you need to recreate the back trace, you will need to add
-fno-omit-frame-pointer to the CFLAGS.

BUG=b:159081993
TEST=Caused an exception and saw the stack dumped. Then I manually
recreated the back trace.

0xcc6fff6c:     0xcc6ce02e <- 0xcc6ce02e is in dev_initialize
0xcc6fff68:     0xcc6fff88 <-- frame 1
0xcc6fff64:     0x00000005
0xcc6fff60:     0x000000dc
0xcc6fff5c:     0x00000000
0xcc6fff58:     0x00000200
0xcc6fff54:     0x00000000
0xcc6fff50:     0x00000400
0xcc6fff4c:     0xcc6d72d4 <- 0xcc6d72d4 is in setup_default_ebdad
0xcc6fff48:     0xcc6fff68 <-ebp
0xcc6fff44:     0x00000005
0xcc6fff40:     0xcc6f571c <-esp

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3822ea7aa23202ecc98612850402eeb4b1f7b5ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-10 15:39:51 +00:00
Martin Roth 812efb1fc2 mb/google/zork: enable i2c devices in verstage
Zork devices shut down the i2c controllers in S3 to save power.  On
resume, they need to be enabled in verstage before being accessed or
the system hangs.

BUG=b:160834101
TEST=Resume works with psp_verstage.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7b8c7e12847876dab4ca74d67d3c41e63d7727cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43334
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 15:39:02 +00:00
Martin Roth 853c6237cb soc/amd/picasso: Map AOAC registers to enable i2c after S3
When entering S3, zork shuts down the i2c controllers to save power.
On resume, we need to re-enable i2c before accessing them, so we need
to map the AOAC registers in verstage.

BUG=b:160834101
TEST=psp_verstage works after resume.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43333
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 15:38:53 +00:00
Angel Pons 3b5e196e67 AMD mainboards: Drop commented-out include
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I6f71419ea23b973b0bedb426e20cb3dc460ef68d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43271
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 12:58:02 +00:00
Angel Pons 69c9aa9dc5 cpu/intel/haswell/finalize.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I3fc616eeb975aae7a5937f8b555ae554010d8dd3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-10 12:57:22 +00:00
Angel Pons a13007b49a mb/asrock/imb-a180: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I00b3af64b6f842d298e91c20ab5f54f0ca3197ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-10 12:56:29 +00:00
Angel Pons 89525b3b4f mb/*/Kconfig: Drop spurious warning about disabled boards
No boards are disabled anymore.

Change-Id: Ic8f7bdcc02faa73ce8e647756d40b20a920fc430
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-10 12:55:41 +00:00
Angel Pons 1b85f18a97 mb/gizmosphere/gizmo2: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: Icc3f9a4f71001547ef3d1efe6fc7551b5c690f92
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-10 12:54:21 +00:00
Angel Pons afd0e9e88a mb/biostar: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I18ddd8a4821d83c038f0a1d17f50247271566e42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-10 12:54:09 +00:00
Angel Pons 1a0e048656 mb/amd/olivehill: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: Ic09b0ee6437766a3ddf126217540f25854a2a562
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-10 12:53:53 +00:00
Angel Pons 2825d6cb14 mb/bap/ode_e20XX: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I9cc4fe7c643458c9d2fa124539a0fd21013ef451
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-10 12:53:17 +00:00
Angel Pons a69a687ec7 sb/intel/i82801ix/Makefile.inc: Sort entries
Sort them by stage execution order, then alphabetically. Place more
complex rules at the end.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Ieadda7c264e0288a212b73febbe9f73351cc4de4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42649
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 12:50:22 +00:00
Angel Pons 8642c659e1 sb/intel/i82801jx/Makefile.inc: Sort entries
Sort them by stage execution order, then alphabetically. Place more
complex rules at the end.

Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.

Change-Id: I1b36d6c0b2e615938272d65456cf10be54f66c38
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42648
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10 12:49:55 +00:00
Angel Pons e8ea97c945 mb/lippert: Align whitespace and comments
This reduces the diffstat between the two boards.

Change-Id: I6754d22139be52c66a9dda5d8e71f1092ecf0697
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43272
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 23:55:36 +00:00
Angel Pons dd1da42f85 ACPI: Drop commented-out DSDT DefinitionBlock instances
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I9b5589d4596eead83a5897b083ccb85ef05a03d5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43270
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 23:55:06 +00:00
Angel Pons e70d1d4b58 drivers/i2c/adt7463: Drop dead code
Nothing selects this driver. Drop it before it grows moss.

Change-Id: I9311dd07b8259384badec65da649fa0cf2da1e01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43267
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 23:54:43 +00:00
Angel Pons 0ac24fc405 drivers/generic/generic: Drop dead code
Nothing selects this driver. Drop it before it grows moss.

Change-Id: I7f06ea45f90d502053c52ea0b7cd7aa6d52295c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43266
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 23:54:30 +00:00
Angel Pons 6065ead9c5 sb/intel/bd82x6x/acpi/lpc.asl: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: Idc600d7a1ce1e47ea4c361caf2b32f1faa56e0f7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43265
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 23:54:18 +00:00
Angel Pons c9e42b98ef nb/intel/gm45/acpi/gm45.asl: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I41a4f73df7fdd372ec7a80a41c8216c502054c39
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43262
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 23:53:40 +00:00
Angel Pons b9bdcaecc1 vc/amd/agesa/f15tn: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I9ceb37186e3622f2eac37393fa7ac5ced8efadf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43258
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 23:53:07 +00:00
Angel Pons 82ab9ca72c drivers/usb/ehci_debug.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I27e4d66a1c8e2ed0eb5152f6bd56cc3fec2dea8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michael Niewöhner
2020-07-09 23:52:36 +00:00