Add CONFIG_FSP_STATUS_GLOBAL_RESET Kconfig to get correct FSP global
reset type from respective SoC Kconfig.
Supported value: 0x40000003-0x40000008, These are defined in FSP EAS
v2.0 section 11.2.2 - OEM Status Code
Unsupported value: 0xFFFFFFFF
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Idc04eb3a931d2d353808d02e62bd436b363600d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
List of changes:
1. Rename do_global_reset() to force_global_reset()
2. Make force_global_reset() function static
3. Implement force_global_reset() into common/reset.c to avoid
dedicated SoC implementation
4. Remove redundant force_global_reset() implementation from
dedicated SoC
5. Make direct call to global_reset() from cse_lite.c
7. Drop CONFIG_HAVE_CF9_RESET_PREPARE Kconfig from APL SoC due
to common reset (soc/intel/common/reset.c) code migration
8. Remove unused function send_global_reset() from SKL me.c due
to common reset code migration
9. Delete heci.c from APL SoC as unused
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I1c5dc8d5606ef28ffaed4a64d90f470ae1ffc2a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
get_prmrr_size does not return the actual PRMRR size but a valid PRMRR
size with repect to the users choice in Kconfig. Thus, rename it from
`get_prmrr_size` to `get_valid_prmrr_size` to avoid confusion about what
it does.
Also fix the broken comment in cpulib.h.
Change-Id: Id243be50acb741f2c3118ddde082743d08983a53
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since PRMRR size can only be set when SGX is enabled and since SGX
depends on PRMRR size >= 32MB, any lower setting (including "Disabled")
is invalid. Drop these settings.
Change-Id: If7a19c7223a0de2e03b7df9184cddf7c9fc87a68
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
PRMRR size shall only be set when SGX is enabled. Make PRMRR depend on
SGX enablement in Kconfig.
Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Defer cse_fw_sync to BS_DEV_RESOURCES boot state so that MRC training
data can be cached before CSE FW Sync and a second MRC training can be
avoided.
BUG=b:168850641
TEST=Build and boot the waddledoo board to OS. Ensure that the memory
training is performed only once.
Change-Id: I0ef5693eaa6ed34dc08c94e5db153f4295578f5f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Lets have the Kconfig depend more directly on CSE_LITE_SKU
than indirectly on the PUFF baseboard.
BUG=none
BRANCH=puff
TEST=builds
Change-Id: I8784b506629ceedc2770dc86d8caabbef5eb8a1d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45523
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enhanced Intel SpeedStep Technology (EIST) and Intel Speed Shift
Technology (ISST) - also know as HWP - are two independent mechanisms
for controlling voltage and frequency based on performance hints.
When HWP is enabled, it overrides the software-based EIST. It does not
depend on EIST, though, but can be enabled on its own.
Break up that currently existing dependency in ACPI generation code.
It was tested that HWP can be enabled and gets used by the Linux pstate
cpufreq driver. With HWP disabled, the frequency does not decrease, even
not in powersave mode. After enabling HWP the frequency changed in
relation to the current workload. (Test device: Acer ES1-572)
Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44137
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All octopus board share the same power off sequence.
Move to smihandler.c instead variant.c.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2be5a656fb42fff99c56d21aaa73ed9140caad37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45436
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pre-RAM CBMEM console is tiny. Do not fill it with largely redundant
information, when we could instead store more useful raminit debug logs.
Change-Id: I3a93fdeb67b0557e876f78b12241b70933ad324d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of decoding the entire SPD, just check the memory type directly.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I3afa0ca5aae984895e50fe7b3792192fdd2ee6c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.
PAVP feature is enabled with CSE Lite SKU for Chrome and HECI1 interface
is required between kernel and CSE Lite.
BUG=None
TEST=Build and boot tglrvp. Run lspci and check pcie device
00:16.0 Communication controller: Intel Corporation Device a0e0
Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Coverity detects variable dsd going out of scope leaks the storage it
points to. Move dsd resource allocation after sanity check for
config->nvm_compact to avoid leak.
Found-by: Coverity CID 1432727
TEST=Built and boot up to kernel on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I86af322dc78845b8b312b6815135336c2c56b4dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Elyes HAOUAS