Commit Graph

17473 Commits

Author SHA1 Message Date
Kyösti Mälkki 08311f5033 AGESA vendorcode: Build a common amdlib
Having CFLAGS with -Os disables -falign-function, for
unlucky builds this may delay entry to ramstage by 600ms.
Build the low-level IO functions aligned with -O2 instead.

Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 10:44:43 +02:00
Kyösti Mälkki 82171ea0ff AGESA vendorcode: Move compiler class definition
Change-Id: Ia4cef7d584e43f1911db2f81d8b86ed406b75aad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14786
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-18 10:44:22 +02:00
Andrey Petrov f87275f821 soc/intel/apollolake: Enable ACPI PM1 timer emulation
Enable emulation for ACPI PM1 timer. This is needed by FSP-M
MemoryInit.

Change-Id: I7a441f5f1673e6430697615ae7251da948e77548
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14821
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 07:06:39 +02:00
Andrey Petrov 664d585882 soc/intel/apollolake: Remove hardcode for TCO watchdog timer
Change-Id: Ie528b0ee3d447dcb819ccb7c0f832885da0f4257
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14820
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18 07:05:32 +02:00
Andrey Petrov 0e46307574 soc/intel/apollolake: Work around FSP-M CAR layout
As of now FSP-M can not be relocated and it can not be instructed
to use a specific resource for temporary memory. As result coreboot
is forced to use CAR layout dictated by default FSP-M configuration.

Change CAR size to 1MiB, link romstage at such CAR address so it
doesn't overlap with FSP-M's default heap/stack.

Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14804
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18 07:05:00 +02:00
Andrey Petrov 5ede3d8cce soc/intel/apollolake: Do not use StackBase FSP-M parameter
Currently, StackBase field doesn't work and changing it from default
value leads to crash.

Change-Id: Id3f3ea9a834d0c04a8381938535109d6a729cca2
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14803
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 07:04:36 +02:00
Andrey Petrov 9be1a115f1 drivers/intel/fsp2_0: Add recipes for FSP blobs in CBFS
Add recipes that insert FSP blobs into CBFS and get rid of
CBFS names hardcoding.

Change-Id: I350abeffc4d23e45e339464d036716ecdb2ba83a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-18 07:04:10 +02:00
Andrey Petrov 868679fe96 soc/intel/apollolake: Take advantage of common opregion code
Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14807
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 07:03:44 +02:00
Andrey Petrov dc4ae11366 soc/intel/common: Add IGD OpRegion support
Add helper function that fills OpRegion structure based on
VBT file content and some reasonable defaults.

Change-Id: I9aa8862878cc016a9a684c844ceab390734f3e84
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 07:03:13 +02:00
Andrey Petrov 060b215fa7 soc/intel/common: Add utility to load VBT file
Change-Id: I8d3d47ca2fc1fc4c10e61c04b941b6378b9c0f80
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14815
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 07:02:43 +02:00
Aaron Durbin 493ec92eb3 util/cbfstool: allow option to honor FSP modules' linked address
If '-b' isn't passed when adding an FSP file type to CBFS allow
the currently linked address to be used. i.e. don't relocate the
FSP module and just add it to CBFS.

Change-Id: I61fefd962ca9cf8aff7a4ca2bea52341ab41d67b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14839
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-18 03:19:12 +02:00
Lee Leahy 15843bdad0 mainboard/intel/galileo: Add I2C chip initialization
Add I2C chip initialization for the Galileo boards.

TEST=Build and run on Galileo Gen2

Change-Id: Ib5284d5cd7a67de2f3f98940837ceb2aa69af468
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14829
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18 00:58:06 +02:00
Lee Leahy ac690b1e9b soc/intel/quark: Add I2C support
Add the I2C driver.

TEST=Build and run on Galileo Gen2

Change-Id: I53fdac93667a8ffb2c2c8f394334de2dece63d66
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14828
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18 00:57:48 +02:00
Jonathan Neuschäfer 0e962eeb93 board_status: Abort early if the coreboot image doesn't exist
Change-Id: I274c990e69634ebcb9dd77470cbf1515281de312
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14683
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18 00:17:18 +02:00
Lee Leahy 5d9f5ff910 soc/intel/quark: Fix spelling error
Change Memroy to Memory in comment.

TEST=None

Change-Id: Ic57fcf962be6a302dcd7b52b9256a182577e734b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14881
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 23:32:33 +02:00
Lee Leahy 3f0fe68c4b soc/intel/quark: Perform GPIO initialization
Set the base address and enable the GPIO and legacy GPIO controllers.
Call the mainboard routine to initialize the GPIO controllers.

TEST=Build and run on Galileo Gen2

Change-Id: I06aed5903d6655d2a0948fb544cf9e0db68faa26
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14827
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 23:30:52 +02:00
Lee Leahy 274d20a065 mainboard/intel/galileo: Add GPIO initialization
Add Kconfig to configure coreboot for a specific Galileo board.
Configure the GPIOs for the specific Galileo board.

TEST=Build and run on Galileo Gen2

Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14826
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 23:30:09 +02:00
Jonathan Neuschäfer 0ba307f0fe acpigen: Fix ?: operator confusion
strlen(string) was on the "negative" side of the selection operator, the
side where string is NULL.

Change-Id: Ic421a5406ef788c504e30089daeba61a195457ae
Reported-by: Coverity Scan (CID 1355263)
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-17 23:27:02 +02:00
Julius Werner 2296479dfd libpayload: cbfs: Add cbfs_handle API for more fine-grained accesses
The libpayload CBFS APIs are pretty old and clunky, primarily because of
the way the cbfs_media struct may or may not be passed in and may be
initialized inside the API calls in a way that cannot be passed back out
again. Due to this, the only real CBFS access function we have always
reads a whole file with all metadata, and everything else has to build
on top of that. This makes certain tasks like reading just a file
attribute very inefficient on non-memory-mapped platforms (because you
always have to map the whole file).

This patch isn't going to fix the world, but will allow a bit more
flexibility by bolting a new API on top which uses a struct cbfs_handle
to represent a found but not yet read file. A cbfs_handle contains a
copy of the cbfs_media needed to read the file, so it can be kept and
passed around to read individual parts of it after the initial lookup.
The existing (non-media) legacy API is retained for backwards
compatibility, as is cbfs_file_get_contents() (which is most likely what
more recent payloads would have used, and also a good convenience
wrapper for the most simple use case), but they are now implemented on
top of the new API.

TEST=Booted Oak, made sure that firmware screens and software sync
worked okay.

Change-Id: I269f3979e77ae691ee9d4e1ab564eff6d45b7cbe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14810
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-17 22:48:28 +02:00
Stefan Reinauer 4bab6e79b0 intel/sch: Merge northbridge and southbridge in src/soc
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-05-17 21:38:17 +02:00
Lee Leahy 083da160af soc/intel/quark: Add GPIO register access
Add register access routines for the GPIO and legacy GPIO controllers.

TEST=Build and run on Galileo Gen2

Change-Id: I0c023428f4784de9e025279480554b8ed134afca
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14825
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 20:26:28 +02:00
Lee Leahy 4c56a58f63 soc/intel/quark: Add LPC symbols
Add LPC_DEV and LPC_FUNC symbols

TEST=Build and run on Galileo Gen2

Change-Id: I8485e2671af439f766228d4eaf9677c2ff8ff3f6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14880
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 20:18:04 +02:00
Lee Leahy 76684bf75b soc/intel/quark: Reformat include/soc/pci_devs.h
Replace # define with #define
Align the right hand column to prepare for further expansion

TEST=Build and run on Galileo Gen2

Change-Id: Ie4d9fb56d52d7291be5523d31c1d3aa51f94dcd6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14879
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 20:16:59 +02:00
Lee Leahy d3989a26c1 drivers/intel/fsp1_1: Simplify union references
Simplify the union references to enable Coverity to properly process
the routine.

Found-by: Coverify CID 1349854

TEST=Build and run on Galileo Gen2

Change-Id: I667b9bc5fcde7f68cb9b4c8fa85601998e5c81ff
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14870
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 20:16:24 +02:00
Lee Leahy 00c35c1a98 drivers/intel/fsp1_1: Replace for/break with returns
Coverity does not like the use of for/break, switch to using returns
instead.

Found-by: Coverity CID 1349855

TEST=Build and run on Galileo Gen2

Change-Id: I4e5767b09faefa275dd32d3b76dda063f7c22f6f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14869
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17 20:15:59 +02:00
Lee Leahy c1cbc605cd soc/intel/quark: Add Ioh.h from EDK-II
Add Ioh.h from EDK-II to enable easy comparisons between EDK-II and
coreboot implementations.

TEST=Build and run on Galileo Gen2

Change-Id: I9320101a4a2c16ed18f682f3d04623c54afb52fd
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14824
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-05-17 19:41:21 +02:00
Lee Leahy 016d8f75d8 drivers/intel/fsp2_0: Fix array indexing error
Don't allow an array index of 2 to be processed by the code referencing
the array.

Found-by: Coverity CID 1353337

TEST=None

Change-Id: I586ca14416a6e40971f8f6f4066fbdb4908ca688
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14868
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-17 18:49:27 +02:00
Aaron Durbin 451b1e0b9d mainboard/google/reef: add first pass of full pad configuration
This is an initial stab of configuring the reef pads.

Change-Id: I8d8060745af6fbada268c6c6f3492b985ddf9eb8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14831
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
2016-05-17 06:18:17 +02:00
Paul Kocialkowski 1811768c64 vboot: Call verification_should_run directly in the if statement
Using a dedicated variable is slightly less readable and makes the code
less consistent, given that other test functions are called directly in
the if statements.

Change-Id: If52b2a4268acb1e2187574d15cc73a0c1d5fe9bb
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14817
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-16 22:37:50 +02:00
Duncan Laurie abe2de8854 acpigen: Add functions to generate _STA() and _PRW()
Add helper functions for generating some common objects:

acpigen_write_STA(status) will generate a status method that will
indicate the device status as provided:
  Method (_STA) { Return (status) }

Full status byte configuration is possible and macros are provided for
the common status bytes used for generated code:
ACPI_STATUS_DEVICE_ALL_OFF = 0x0
ACPI_STATUS_DEVICE_ALL_ON  = 0xF

acpigen_write_PRW() will generate a Power Resoruce for Wake that describes
the GPE that will wake a particular device:
  Name (_PRW, Package (2) { wake, level }

Change-Id: I10277f0f3820d272d3975abf34b9a8de577782e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14795
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-16 19:55:59 +02:00
Duncan Laurie f7c3876c28 acpigen: Add an abstracted integer output method
In order to produce smaller AML and not rely on the caller to size the
output type appropriately add a helper function that will output an
appropriately sized integer.

To complete this also add helper functions for outputting the single
OpCode for Zero and One and Ones.

And finally add "name" variants of the helpers that will output a
complete sequence like "Name (_UID, Zero)".

Change-Id: I7ee4bc0a6347d15b8d49df357845a8bc2e517407
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14794
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-16 19:55:33 +02:00
Duncan Laurie 56b69aa9c7 acpigen: Add helper functions for strings
Add helper function to emit a string into the SSDT AML bytestream with a
NULL terminator.  Also add a helper function to emit the string OpCode
followed by the string itself.

acpigen_emit_string(string)  /* Raw string output */
acpigen_write_string(string) /* OpCode followed by raw string */

Change-Id: I4a3a8728066e0c41d7ad6429fad983e6ae6962fe
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14793
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-16 19:51:58 +02:00
Duncan Laurie 9ccae7558d acpigen: Add helpers for word/dword output
Add helpers for writing word and dword values in acpigen and use them
throughout the file to clean things up:

acpigen_emit_word - write raw word
acpigen_emit_dword - write raw dword
acpigen_write_word - write word opcode and value

Change-Id: Ia758d4dd25d0ae5b31be7d51b33866dddd96a473
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-16 19:51:36 +02:00
Duncan Laurie 4650f5baff sconfig: Add a new generic device type
Add support for a basic generic device in the devicetree to bind to a
device that does not have a specific bus, but may need to be described
in tables for the operating system.  For instance some chips may have
various GPIO connections that need described but do not fall under any
other device.

In order to support this export the basic 'scan_static_bus()' that can
be used in a device_operations->scan_bus() method to scan for the generic
devices.

It has been possible to get a semi-generic device by using a fake PNP
device, but that isn't really appropriate for many devices.

Also Re-generate the shipped files for sconfig.  Use flex 2.6.0 to avoid
everything being rewritten.  Clean up the local paths that leak into the
generated configs.

Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14789
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-16 19:49:59 +02:00
Duncan Laurie b7ce5fe311 sconfig: Add 10bit addressing mode to i2c device type
Use the second token for an i2c device entry in devicetree.cb to
indicate if it should use 10-bit addressing or 7-bit.  The default if
not provided is to use 7-bit addressing, but it can be changed to
10-bit addressing with the ".1" suffix.  For example:

chip drivers/i2c/generic
  device i2c 3a.1 on end
end

Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14788
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-16 19:49:46 +02:00
Duncan Laurie b1fb0152bf sconfig: Allow strings in devicetree.cb
Currently you cannot assign a string to a register in devicetree because
the quotes are removed when parsing and the literal is assigned directly.

Add a parse option for two double-quotation marks to indicate a string
and return a quoted literal that can be assigned to a register with a
'const char *' type.

Example:

chip drivers/i2c/generic
  register "hid" = ""INT343B""
  register "uid" = "1"
  device i2c 15 on end
end

Change-Id: I621cde1f7547494a8035fbbab771f29522da1687
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14787
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-16 19:49:37 +02:00
David Hendricks b2aa5283e6 board_status: Add longopt equivalents for older options
Long options can be useful when writing examples and documentation
as they are more expressive and obvious to the reader.

Change-Id: I39496765ba1f15ccc2ffe1ad730f0f95702f82b8
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14736
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-05-16 19:19:54 +02:00
Aaron Durbin e065bb43d7 mainboard/google: add reef reference board
This adds the initial scaffolding for the reef reference board.
One big thing missing is the GPIO configuration.

Change-Id: I8e2d275df296bb397bb33dbd0c66fc87c82ff10f
Signed-off-by: Aaron Durbni <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14798
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13 22:38:53 +02:00
Aaron Durbin fc2e7413b3 soc/intel/apollolake: provide common LPDDR4 memory init
Instead of having the mainboards duplicate logic surrounding
LPDDR4 initialization provide helpers to do the heavy lifting.
It also handles the quirks of the FSP configuration which allows
the mainboard porting to focus on the schematic/design.

Change-Id: I686eb3097c33399a3b94af89237f7fe1b2d34c2f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14790
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13 22:38:26 +02:00
Stefan Reinauer 0b4db13994 vendorcode/intel/fsp1_0: Don't break GCC strict aliasing
Change-Id: I6b345670db7df652b8b712b721dfe2905373e0d5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14630
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: York Yang <york.yang@intel.com>
2016-05-13 17:34:13 +02:00
Stefan Reinauer 1eaf58be2c HobLib: Don't break GCC strict aliasing
Change-Id: I1bd33e423b0fcb69597e001b61c6ea916f5fe44a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14622
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-13 17:33:30 +02:00
Kyösti Mälkki a53977e232 AMD fam14: Blacklist Intel Centrino n6235 from PCIe ASPM
PCI device ID of this mini-PCI-e WLAN card is 8086:088e.

With this card inserted on pcengines/apu1 mini-PCI-e slot J17,
system halts late in ramstage, in agesawrapper AMD_INIT_MID.

Offending operation is enabling PCIe ASPM L0s and L1 for the card.
That is, writing PCIe capability block Link Control [1:0] = 11b
in the card's configuration space. AGESA already has a blacklist
for the purpose of masking such unstable ASPM implementations.

Change-Id: I9623699c4ee68e5cdc244b87faf92303b01c4823
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/8496
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-13 17:32:29 +02:00
Jonathan Neuschäfer 4aef682819 board_status: Add an option to set the SSH port
If the option is not provided, ssh uses the default port for the host,
which is usually 22, but may be overridden in the user's SSH
configuration.

Change-Id: I303e9aeae16bd73a96c5e6d54f8e39482613db28
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14522
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-05-13 17:30:58 +02:00
Jonathan Neuschäfer 478c889847 board_status: Use explicit branch name in "git push"
In some configurations, "git push <remote>" (without a branch name)
refuses to do anything.

Change-Id: I23a401b39dd851e9723676586c7f29afa111b49d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14539
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-05-13 17:29:35 +02:00
Aaron Durbin fc6a9f2c20 soc/intel/apollolake: implement common gpio API
In order for apollolake mainboards to utilize the common GPIO API
it actually needs to be implemented.

Change-Id: I41de8d5d9f3c39e7e796eae73b01cb29e9c01347
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14797
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13 17:22:53 +02:00
Aaron Durbin c10ac755f0 ec/google/chromeec: don't guard function declarations
In order to allow using the same C source to be compiled
for multiple stages (with #if/#endif guards) one needs the
necessary function delcarations. Therefore, remove the
guards.

Change-Id: Iea94d456451c5d3db8b8b339e81163b3b3fed3ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14796
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13 17:22:33 +02:00
Stefan Tauner 572f074971 inteltool: update documentation
- manpage
 - usage message
 - new warning message if -S is used on an unsupported chipset

Change-Id: I1acaa5f4232b65244ec00fd22ec7460d9cc387f1
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14624
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-05-13 16:58:56 +02:00
Aaron Durbin c3ee3f6d7e soc/intel/apollolake: use common FADT infrastructure
Instead of having the mainboards duplicate the same boilerplate
code utilize the common FADT infrastructure to reduce duplication.

Change-Id: If824619fd619433974e588050a933d2c19b97ec8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14779
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-12 20:06:06 +02:00
Kyösti Mälkki d867b7d87c AGESA vendorcode: Drop alternate image dispatcher
Not used as we link AGESA into same romstage and ramstage ELF.

Change-Id: Ia427b9c0cc88b870de75df14bba4ca337a28adff
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14395
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-12 11:38:18 +02:00
Kyösti Mälkki 898c47c5dc AGESA f12: Build as libagesa.a
Change-Id: If48fffee1441b6bb012a8d99abb794f7a35efcf6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14412
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-12 11:37:51 +02:00