Commit Graph

40744 Commits

Author SHA1 Message Date
Tim Wawrzynczak 0c057c21e5 soc/intel/adl, mb/google/brya: Add IPU to devicetree
BUG=b:181843816

Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05 20:09:41 +00:00
Tim Wawrzynczak e94a578039 mb/google/brya: Add IPU ASL to DSDT
BUG=b:181843816

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I74246cd0d2f866022604ec3e8a8d523c273cdef4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05 20:09:30 +00:00
Tim Wawrzynczak ba2e51bd49 mb/google/brya: brya0: Add ACPI support for Type-C ports
BUG=b:181160586, b:181843816

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51258
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05 20:09:15 +00:00
Brandon Breitenstein 7b42492bed mb/google/volteer: Configure tcss port information for early tcss init
Implement the mainboard_tcss_get_port_info weak function so that the TCSS
muxes can be properly configured to ensure mapping is correct in mux. This
ensures that any devices that are connected during boot are not improperly
configured by the Kernel.

BUG=b:180426950
BRANCH=firmare-volteer-13672.B
TEST= Verified that the SOC code that initialized TCSS muxes to disconnect
mode is executing properly for all TCSS ports and verified that USB3 devices
are no longer downgrading to USB2 speed if connected during boot.

Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05 17:02:31 +00:00
Brandon Breitenstein d8774f6899 soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
TCSS muxes being left uninitialized during boot is causing some USB3
devices to downgrade to USB2 speed. To properly configure the Type C ports
the muxes should be set to disconnected state during boot so that the port
mapping of USB2/3 devices is properly setup prior to Kernel initializing
devices.

BUG=b:180426950
BRANCH=firmware-volteer-13672.B
TEST= Connected USB3 storage device and rebooted the system multiple
times to verify that devices were no longer downgrading to USB2 speed.

Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05 17:02:20 +00:00
Angel Pons 54d59ef7b7 drivers/intel/gma/gma.ads: Uniformize casing
Use lowercase `port` in both the spec and the body.

Change-Id: I3d1e2abe03eedcaf57716af444a3e3b8a61b60d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-05 10:59:00 +00:00
Arthur Heymans 54c04d5536 sb/ti/pcixx12: Remove NOOP chip driver
Change-Id: I46bc854239e723a1685279f634e635b72e7b3af9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-05 10:58:33 +00:00
Angel Pons 418190cbba sb/intel/lynxpoint: Refactor `usb_xhci_port_count_usb3`
Change the function parameters to avoid preprocessor usage.

Change-Id: Iec43e057ed2a629e702e0f484ff7f19fe8a0311b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05 10:58:17 +00:00
Angel Pons b9338ba502 soc/intel/broadwell/pch: Rename USB files
Done to ease diffing against Lynxpoint.

Change-Id: Ib4280b26799eab6d4a2bb41a14a76695caa31e86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-05 10:57:41 +00:00
Angel Pons 8af3e0eb42 soc/intel/broadwell/pch: Use Lynx Point smbus.c
Continue unifying Lynx Point and Wildcat Point (PCH for Broadwell) code.
Define the WPT-LP SMBus PCI device ID, add it to smbus.c of Lynx Point,
and drop all now-unnecessary SMBus code from Broadwell.

Change-Id: I864d7c2dd47895a3c559e2f1219425cda9fd0c17
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05 10:57:10 +00:00
Karthikeyan Ramasubramanian ba7b90ecf2 security/tpm/tss/vendor/cr50: Introduce vendor sub-command to reset EC
Add marshaling and unmarshaling support for cr50 vendor sub-command to
reset EC and a interface function to exchange the same.

BUG=b:181051734
TEST=Build and boot to OS in drawlat. Ensure that when the command is
issued, EC reset is triggered.

Change-Id: I46063678511d27fea5eabbd12fc3af0b1df68143
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05 10:57:01 +00:00
Zanxi Chen 7cdcf64f71 mb/google/dedede/var/blipper: Generate SPD ID for supported memory parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE

BUG=None
TEST=Build the blipper board.

Change-Id: Ia7e4c1d5c06013c1902816d6dcafb5a8a0386bb3
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-05 10:56:42 +00:00
Angel Pons 81e9263caa soc/intel/apollolake: Add `GPE0_STS_BIT` macro
The datasheet indicates that this bit is reserved. However, subsequent
patches need to use this macro in common code, or else builds fail. To
iron out this difference, mask out the bit in `soc_get_smi_status`, so
that common code always sees it as zero. Finally, add an entry for the
bit in `smi_sts_bits` for debugging usage, noting that it is reserved.

Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05 10:55:58 +00:00
Subrata Banik e4606bbff7 soc/intel/common/block/cpu: Use tab instead of space
Convert the lines starts with whitespace with tab as applicable.

Change-Id: Ife7b27360661cbfd2c90e2b643ed31225ded228c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51250
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05 08:38:26 +00:00
John Su 99059d170a mb/google/zork/var/vilboz: Update telemetry settings
Update telemetry settings for vilboz.

VDD Slope : 26939 -> 27225
VDD Offset: 125   -> 187
SOC Slope : 20001 -> 26559
SOC Offset: 168   -> 89

BUG=b:177162553
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iaf7c5083c4c5affec5ae0b5583efb5237e10d0ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-03-05 04:47:36 +00:00
Nick Vaccaro 2f78ce0995 mb/google/volteer: Fix FPMCU pwr/rst gpio handling
1. No gpio control in bootblock
2. Power on and then deassert reset at the end of ramstage gpio
3. Disable power and assert reset when entering S5

On "reboot", the amount of time the power is disabled for is
equivalent to the amount of time between triggering #3 and wrapping
around to #2.

This change affects the following volteer variants that include an FPMCU:
  1. Drobit
  2. Eldrid
  3. Elemi
  4. Halvor
  5. Malefor
  6. Terrador
  7. Trondo
  8. Voema
  9. Volteer2
 10. Voxel

BUG=b:178094376
TEST=none

Change-Id: Ib51815349cea299907c10d6c56c27bd239e499e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05 04:28:36 +00:00
Brandon Breitenstein 29144554fb soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and soc
The original implementation of early tcss resulted in calling to mainboard
then back to soc then back to mainboard to properly configure the muxes.
This patch addresses that issue and instead just gets all the mux
information from mainboard and does all config in the soc code.

BUG=none
BRANCH=firmware-volteer-13672.B
TEST=Verified functionality is not effected and early TCSS still functions

Change-Id: Idd50b0ffe1d56dffc3698e07c6e4bc4540d45e73
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05 03:53:24 +00:00
Furquan Shaikh 338d668b6f soc/intel/tigerlake: Fix NULL being passed for response buffer
`pmc_send_ipc_cmd()` expects the caller to pass in a pointer to a valid
request and response buffer. However, early_tcss driver was passing in
a NULL pointer for response buffer which would result in invalid
access by `pmc_send_ipc_cmd()`.

Currently, the response buffer is not used in `update_tcss_mux()`. So,
this change drops the passing of `rbuf` parameter to `send_pmc*`
helpers and instead uses a local `rsp` variable in the respective
functions. All the PMC functions used in early_tcss driver return some
kind of response. These should be checked to return appropriate
response code back to the caller. However, this needs to be done as a
separate change.

Change-Id: I215af85feed60b6beee17f28e3d65daa9ad4ae69
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05 03:53:16 +00:00
Felix Held 4a88b03a6c soc/amd/cezanne/chipset.cb: clean up and change some aliases
With the aliases some of the comments are redundant. I'm still not sure
if the Ethernet controller on the embedded SKUs supports 10G or only 1G.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e432c12f92a622f8ee05be19acb2c304dd74afb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-04 23:51:39 +00:00
Felix Held e84111c352 vc/amd/fsp/picasso: fix DDI enum name prefix
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12ec6a3c2704effc1a626181898a9ed7a17f0640
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51239
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04 23:51:21 +00:00
Felix Held 913dcf6482 soc/amd/cezanne/smihandler: implement S3 entry SMI handler
Since the support for the GSMI ELOG isn't implemented in the SMI handler
yet, the corresponding code isn't added to fch_slp_typ_handler in this
patch.

BUG=b:181766974

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia27b2486dde1a373607ce895a975e873d9026ba1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-04 19:55:56 +00:00
Felix Held 7f3f52d7c6 soc/amd/cezanne: add SMU support
BUG=b:181766974

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5b9b4c3d57945ea7c3287cf47f3d9704f42ff24b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-04 19:55:27 +00:00
Werner Zeh dac1a456f9 src/drivers/i2c/rx6110sa: Add official ACPI ID
In commit 2609eaaa8f (src/drivers/i2c/rx6110sa: Omit _HID temporarily)
the randomly assigned and therefore wrong ACPI ID for RTC RX6110SA was
removed. In the meantime Seiko-Epson did a great job and registered an
official vendor ID in the ACPI database [1]. Further on, Seiko-Epson
has now assigned the unique Product Identifier for the RX6110SA, which
is '6110'. The assignment of the Product Identifier is controlled by
the vendor and there is no official database where this ID is stored
in. It is up to the vendor to make sure that this ID stays unique.

This patch adds this new vendor and product ID to the driver. Together
with a pending Linux patch this RTC is now useable as ACPI device in
Linux.

[1] https://uefi.org/ACPI_ID_List?search=SECC

Change-Id: I45838162f014a760520692c6dcaae329ad98547d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51176
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04 11:49:23 +00:00
Eric Lai f8c167549b drivers/generic/max98357a: Use depends HAVE_ACPI_TABLES
Replace if HAVE_ACPI_TABLES statement with depends HAVE_ACPI_TABLES.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie6ebfde49f0f3c205e174c5113feb75444dedba8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-04 08:47:58 +00:00
Eric Lai 16b34ed8f8 drivers/generic/alc1015: add ALC1015 AMP driver
Add ALC1015 AMP support.
ALC1015Q-VB Datasheet Rev 0.1

BUG=b:177971830
TEST: ALC1015P driver can probe properly.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id93845024aa2cded69acc88d594c222f2f821f79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51051
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04 08:47:51 +00:00
hao_chou b967c60dc7 mb/google/volteer/variants/copano: Describe USB ports in devicetree
Modify USB port to match schematics.
And assigned USB2 port to type-c use.

BUG=b:177481079
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Change-Id: I25412d16df8ad809c05635022c11bd8882d002c5
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49980
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04 08:47:40 +00:00
Moritz Fischer abefcc2e2c soc/rockchip/rk3399/sdram: Add channel to error message
When printing error information during DRAM training, be more verbose
by printing the channel number.

Change-Id: If4109bd0573e3d9f90d699d89350ddbcc48714d3
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-04 01:22:10 +00:00
Moritz Fischer 1e192138d1 soc/rockchip/rk3399/sdram: Simplify error condition
There is no need for explicit 0 comparison, any return value not equal
to 0 is treated as error.

Change-Id: I72612af4108a616b6247ee68c8ac2a53242b0853
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-04 01:22:03 +00:00
Nikolai Vyssotski a2e5746c81 vc/amd/fsp/picasso: increase FSPS UPD block size from 0x152 to 0x202
We will need more FSPS UPD space for PEI GOP changes coming.

BUG=b:171234996
BRANCH=Zork

Cq-Depend: chrome-internal:3609213, chromium:50576
Change-Id: I35d0bb0ee30e04f66882b6103acd9d673d040c07
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-03 23:35:15 +00:00
Nikolai Vyssotski 794f1e785d amd_blobs: update submodule pointer
Pick up build 0x26 Picasso FSP binaries. The changes include increased
FSPS UPD block size from 0x152 to 0x202.

Change-Id: I11fc199ca7bc6ee7431c59d35a60d9ebd977bf10
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-03 22:20:07 +00:00
Patrick Georgi 517097f659 MAINTAINERS: Add Jakub as maintainer for tests/
He practically is, so let's make it official.

Change-Id: I8adae5071f94ff309834fcab17b5a722e5c44b10
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
2021-03-03 20:55:25 +00:00
Felix Held af6a434236 soc/amd/cezanne/chipset.cb: rename alias for SATA controllers
Renoir/Cezanne have two SATA controllers with 2 ports each, so call them
sata_0 and sata_1.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 19:42:18 +00:00
Frank Wu edd748fdb3 mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz
Loading wifi_sar-vilboz-1.hex for vilboz360 LTE sku for the present.

BUG=b:177684735, b:176168400
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are
in CBFS and loaded by iwlwifi driver.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I477b55d64fd9d33d753b10b2de443041a12d13e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-03 18:59:55 +00:00
Zheng Bao 2494aa952c mb/amd/majolica: Add eSPI support
Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-03 18:39:27 +00:00
Amanda Huang b2f3151ed9 mb/google/brya: Add support for 2 new DRAM parts
1) Micron MT53E1G32D2NP-046
2) Micron MT53E2G32D4NQ-046

BUG=b:181378727
TEST=none

Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03 15:50:54 +00:00
Amanda Huang d925ca70d9 util: Add new memory part to LP4x list
Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes
are derived from data sheets.Also, regenerate the SPD files for ADL
SoC using the newly added parts.

BUG=b:181378727
TEST=Compared generated SPD with data sheets and checked in SPD

Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03 15:50:47 +00:00
Aamir Bohra 1d14ef25f3 mb/google/brya: fix BT enumeration issue
Current implementation exposes GPP_F4 cnvi reset pin as reset
gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven
by SoC. It should not be driven by driver.

BUG=b:180875586

Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 15:22:14 +00:00
Maxim Polyakov b77cf2299c soc/intel/common/block/smbus: Add config to use ACPI
Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44865
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 09:36:07 +00:00
Angel Pons d3a65deb25 soc/intel: Guard macro parameters in pm.h
Guard against unintended operator precedence and associativity issues.

Change-Id: I342682a57fde9942cdf7be10756ee21c10af802a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50917
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 09:07:59 +00:00
Angel Pons b0f52fb5bf soc/intel/cannonlake: Move `gpi_clear_int_cfg()` call
To allow unifying bootblock.c in follow-ups, move a function call.

Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03 09:07:04 +00:00
Angel Pons a4cd9117da soc/intel: Factor out common smmrelocate.c
There are seven identical copies of the same file. One is enough.

Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 09:06:09 +00:00
Benjamin Doron 482d3a1f03 soc/intel/skylake: Always print ME FW SKU
State of ME firmware SKU is independent of power-down mitigation.

Change-Id: I014c1697213efaefcb0c2a193128a876ef905903
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03 09:05:19 +00:00
Benjamin Doron 27af8da7cb soc/intel/skylake: Enable compression on FSP-S
Use LZ4 algorithm to compress FSP-S. This saves ~40 KiB and reduces the
boot time by ~7 ms. LZMA would save a further ~1 KiB, but adds ~9 ms to
the boot time.

LZMA size:
fsps_lzma.bin	0xb0dc0    fsp	146578 LZMA (188416 decompressed)
LZMA decompression time:
  15:starting LZMA decompress (ignore for x86)         388,716 (47,646)
  16:finished LZMA decompress (ignore for x86)         406,167 (17,450)

LZ4 size:
fsps_lz4.bin	0x242dc0   fsp	147442 LZ4  (188416 decompressed)
LZ4 decompression time:
  17:starting LZ4 decompress (ignore for x86)          384,736 (47,864)
  18:finished LZ4 decompress (ignore for x86)          384,796 (59)

Change-Id: Idace01227cfd2312b2c4c4ea1e6aaac8c21cd6b0
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-03 09:04:48 +00:00
Tim Wawrzynczak 242da79a3f soc/intel/alderlake: Log internal device wake events
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI,
south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-03 09:04:12 +00:00
Tim Wawrzynczak d828aed1dd soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devices
Change-Id: I5cf54ae0456147c88b64bd331d4de5ca2e941f8a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47413
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 09:03:55 +00:00
Tim Wawrzynczak 3fca2c7922 soc/intel/alderlake: Add PCIe root port wake sources to elog
Log PCIe root port wake events in the elog.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-03 09:03:42 +00:00
Angel Pons 71505f5f47 sb/intel/lynxpoint/lpc.c: Relocate lock bit write
This lock bit can be set later, and should also be set for LynxPoint-H.
This eases merging with Broadwell, which already sets this lock bit
after `spi_finalize_ops()` in a dedicated finalisation function.

Tested on Asrock B85M Pro4 (LynxPoint-H), the lock bit is now set.

Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 09:03:18 +00:00
Paul Menzel bd78c5a649 AGESA boards: Captilize ASL names
ASL+ Optimizing Compiler/Disassembler version 20200925 remarks:

        IASL       build/dsdt.aml

    Intel ACPI Component Architecture
    ASL+ Optimizing Compiler/Disassembler version 20200925
    Copyright (c) 2000 - 2020 Intel Corporation

    dsdt.asl    222:  Name(PSa, Package(){
    Remark   2182 -         ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (PSA_)

    dsdt.asl    228:  Name(APSa, Package(){
    Remark   2182 -          ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (APSA)

Execute the command below to fix all occurences:

    git grep -l PSa | xargs sed -i 's/PSa/PSA/g'

Change-Id: Ia458c98a4774fb5745825aecf996a476e66eaa3f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03 09:03:02 +00:00
Angel Pons ebf5ae5bd5 configs/config.google_volteer.build_test_purposes: Add file
This is meant to build-test Crashlog and various debug options.

Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com>
2021-03-03 09:02:39 +00:00
Francois Toguo 4280b43473 soc/intel/tigerlake: Re-use existing define in CrashLog implementation
TEL_CFG_BAR variables have the same value as PCI_BASE_ADDRESS.
This fix re-uses an already existing variable in crashLog.

BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03 09:02:16 +00:00