Commit Graph

41156 Commits

Author SHA1 Message Date
Yidi Lin 7de8df467a soc/mediatek/mt8192: Reserve 44K SRAM for MCUPM working buffer
Reduce PRERAM_CBMEM_CONSOLE buffer from 63K to 19K and reserve
0x00115000 ~ 0x0011ffff for MCUPM.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ic82a194736eecd7bdc8df80b493290090a2ccba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-16 11:04:11 +00:00
Eric Lai 93538c9969 mb/google/zork/: Enable REGULATORY_DOMAIN on Vilboz
WRDD table is needed for Intel WiFi module to enable SAR function.

BUG=b:173066178
BRANCH=zork
TEST=dump ACPI and check WRDD exist with Intel WiFi module.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9fd6fd19ed188f7ab91faab9e2599b9b09ca5b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2020-11-16 11:03:57 +00:00
Nick Chen b7a55fd804 volteer/variants/eldrid: Goodix touch panel power-on sequence tuning
1. Enable panel stop GPIO in ramstage
2. generic.reset_delay_ms change to 30

BUG=b:171365316
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I90ca39312252c668da6298183e598392bc9f9f28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-16 11:03:50 +00:00
Tim Chu e41f595310 arch/x86/smbios: Update memory_array_handle for SMBIOS type 19
Update memory array handle for SMBIOS type 19.

TEST=Execute "dmidecode -t 19" to check if memory array handle is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I49078b870bac3c6162913b91651ec09632800f1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 11:03:37 +00:00
Martin Roth 726504a61a mb/google/zork: Init fingerprint GPIOs for boot vs resume
Add a function that initializes GPIOs based on the sleep type that
the system is coming back from.  This allows initialization of the
fingerprint GPIOs which need to be handled differently between wake
from S3 and boot from S5.

On initial boot, the state of the FP sensor could be either
enabled or disabled.  Because of this, on boot, we power off
the sensor for >200ms, to reset its state, then power it back on.

In suspend/resume, the fingerprint sensor should remain powered
the entire time.

If fingerprint is disabled on the trembyle-based board, set the pins
to no-connect.  Dalboz doesn't have fingerprint and the GPIOS are
configured differently due to the FT5 chip having fewer GPIOS than
FP5, so nothing needs to be initialized there.

There were also a couple of trivial comment clean ups regarding the
FPMCU GPIOS.

BUG=b:171837716
TEST=Boot & Check GPIO states.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-16 11:03:25 +00:00
Martin Roth fc2047b1f7 src: Change bare 'unsigned' to 'unsigned int'
This fixes all of the current code in coreboot/src where a bare
unsigned is used incorrectly. A follow-on will fix the comments
so that we can enable the unsigned lint checker for src/coreboot.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I37f34a95bb1894e70cd9e076d4b81ebac665eaeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 11:03:16 +00:00
Johnny Lin c6b77d5bf6 vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW45 FSP Memory map HOB mismatch
Tested=On OCP Delta Lake, verify the memory map hob data are correct.

Change-Id: I86bd809e21270395c4115788e5521606e9dcc2fb
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 11:03:00 +00:00
Martin Roth 863b3ad45b commonlib: Add timestamp values for forced delays
Add a timestamp entry to allow forced delays to to be seen and accounted
for in the timestamp data.

BUG=None
TEST=Build only

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I26c9fa5c8599a349de2631ac24b9ea8858d8d6c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-16 11:01:37 +00:00
David Wu df9901eacb mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs
This change adds memory parts used by variant voema to
mem_parts_used.txt and generates DRAM IDs allocated to these parts.

Added memory
1. H9HCNNNCRMBLPR-NEE
2. H9HCNNNFBMBLPR-NEE
3. MT53D1G64D4NW-046 WT:A

BUG=b:172751925,b:172781673,b:172782100,b:172781562
TEST=emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic832155448fb07152b906aa04ca49d384ec47b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47351
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 11:01:12 +00:00
David Wu ed993f5faf lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list of
available LP4x parts and to the global JSON file containing LP4x parts
and their characteristics.
1. H9HCNNNCRMBLPR-NEE
2. H9HCNNNFBMBLPR-NEE
3. MT53D1G64D4NW-046 WT:A

BUG=b:172751925,b:172781673,b:172782100,b:172781562
TEST=cd <path_to_coreboot_src>/util/spd_tools/lp4x &&
./gen_spd <path_to_coreboot_src>/src/soc/intel/tigerlake/spd \
global_lp4x_mem_parts.json.txt "TGL"

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I37702770f707fe078920694468552c5db59c478f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47350
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 11:01:02 +00:00
Kangheui Won b2c39b563a drivers/i2c/dw: Check for TX_ABORT in transfer
When the host sends data in i2c bus, device might not send ACK. It means
that data is not processed on the device side, but for now we don't
check for that condition thus wait for the response which will not come.

Designware i2c detect such situation and set TX_ABORT bit. Checking for
the bit will enable other layers to immediately retry rather than
wait-timeout-retry cycle.

BUG=b:168838505
BRANCH=zork
TEST=test on zork devices, now we see "Tx abort detected" instead of I2C
timeout for tpm initializtion.

Change-Id: Ib0163fbce55ccc99f677dbb096f67a58d2ef2bda
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-16 11:00:57 +00:00
Felix Held 93231b45e4 MAINTAINERS: add maintainers of soc/amd/picassso
Change-Id: Id39bd55a9a05b062892defadeb652980213b1e9c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47577
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 08:14:04 +00:00
Felix Held 14e3432148 soc/amd/common/block: drop double underscores from include guards
Since coreboot is written in C and not C++, having the double
underscores as a prefix is not an issue, but it also doesn't add much
information, so drop them and the trailing ones as well.

Change-Id: I1028fb9097efab8ffae5ffa9fe85a97feebc78a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47583
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 08:12:56 +00:00
Felix Held e70c32f7b7 soc/amd/stoneyridge: unify and align include guards with picasso
Change-Id: I0cc06e33ed5c9b9bd97ed1f10f9c2d8019b1b5ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47582
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 08:12:37 +00:00
Felix Held 4feef09c65 soc/amd/picasso/include: unify include guards
Change-Id: I980cdd03d4283cd4bd9db8bd90fde9a43bebc1e5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-16 08:12:22 +00:00
Felix Held aa003fecfd soc/amd/picasso/include/amd_pci_int_defs: remove duplicate comment
This also reduces the difference to the equivalent file from
stoneyridge.

Change-Id: I3fc44f057047995cc4054a85a1bb69427aa28531
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47581
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 08:11:18 +00:00
Tao Xia f3c0a01dc6 mb/google/kukui: Fix LCD sequence T3 fail issue
The T3 that PPVARN_LCD low to LCM_RST_1V8 high is 0.1269ms and
it does not meet the LCD specification that the T3 must be larger
than 5ms. Because there is a delay between PPVARN_LCD_EN and
PPVARN_LCD. An extra 9ms delay should be added on LCM_RST_1V8
in order to meet the specification "ProductSpec_NV105WUM-A51_
V4.3_P2(TLCM).pdf".

BUG=b:172201138
BRANCH=kukui
TEST=The LCD sequence T3 is larger than 5ms when power on.

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Iaf7ae494e30c4c207103d949287b335288688c54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-11-16 07:15:19 +00:00
Felix Held 17cd905828 util/cbfstool/amdcompress: fix argument requirement
The compress and uncompress options don't have arguments and shouldn't
consume the next token. So replace required_argument with no_argument
for the two options.

Change-Id: Ib9b190f2cf606109f82a65d00327871d6ffb7082
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-15 16:49:30 +00:00
Felix Held e0117b1489 util/cbfstool/amdcompress: fix short option for maxsize
Both the help and the maxsize option had the same short option character
assigned. Change the short option for maxsize to m to fix this and to
make it consistent with the rest of the code.

Change-Id: Icac1a7d4906345c37a5c7bed2b4995fea25f860e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-15 16:49:17 +00:00
Felix Held 60a4643d6f soc/amd/common: factor out SMU code from Picasso
The SMU mailbox access code from Picasso can be reused in the next
generation, so factor out the code to soc/amd/common/block/smu. Since
the mailbox register offsets in the indirect address space, the number
of arguments and the message IDs don't always match between different
devices, keep those in the soc-specific directories.

Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-15 16:48:38 +00:00
Srinidhi N Kaushik 34c5905614 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444
Update FSP headers for Tiger Lake platform generated based on FSP
version 3444. Previous version was 3425.

BUG=b:173160613
BRANCH=none
TEST=build and boot delbin

Cq-Depend:chrome-internal:3403586, chrome-internal:3403392
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47555
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-15 05:14:55 +00:00
Michael Niewöhner c66e1c2a31 soc/intel/cnl: enable ACPI CPPC entries generation
Enable CPPC entries generation, needed for Intel SpeedShift.

Test: dumped SSDT from Clevo L140CU and checked decompiled version

Change-Id: I0c8066a31d3bec27776836aac54c335c0e5d74e6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47541
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-14 18:54:35 +00:00
Michael Niewöhner ed21df6cec soc/intel/common/block: add code for ACPI CPPC entries generation
Copy the code for CPPC entries generation, needed for Intel SpeedShift,
from SKL to common ACPI code.

SKL is going to use common ACPI code, too, in the future, so this code
duplication will vanish soon.

Test: dumped SSDT from Clevo L140CU and checked decompiled version after
enabling CPPC entries via Kconfig

Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45535
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-14 18:54:23 +00:00
Arthur Heymans 77038b16ff soc/intel/xeon_sp: Improve generating PCH IOAPIC MADT entry
The PCH IOAPIC ID is 0x8 so it needs to be generated before the IIO
IOAPICs. Since we will get rid of the ioapic_id array this makes it
more readable.

Change-Id: I64a3b259e438ef666fb68a433cceda10aebdb1bf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-14 12:29:29 +00:00
Shelley Chen 6615c6eaf7 mrc_cache: Move code for triggering memory training into mrc_cache
Currently the decision of whether or not to use mrc_cache in recovery
mode is made within the individual platforms' drivers (ie: fsp2.0,
fsp1.1, etc.).  As this is not platform specific, but uses common
vboot infrastructure, the code can be unified and moved into
mrc_cache.  The conditions are as follows:

  1.  If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain
      switch is true)
  2.  If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this
      means that memory training will occur after verified boot,
      meaning that mrc_cache will be filled with data from executing
      RW code.  So in this case, we never want to use the training
      data in the mrc_cache for recovery mode.
  3.  If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this
      means that memory training happens before verfied boot, meaning
      that the mrc_cache data is generated by RO code, so it is safe
      to use for a recovery boot.
  4.  Any platform that does not use vboot should be unaffected.

Additionally, we have removed the
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the
mrc_cache driver takes care of invalidating the mrc_cache data for
normal mode.  If the platform:
  1.  !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data
  2.  HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set

BUG=b:150502246
BRANCH=None
TEST=1. run dut-control power_state:rec_force_mrc twice on lazor
        ensure that memory retraining happens both times
        run dut-control power_state:rec twice on lazor
        ensure that memory retraining happens only first time
     2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig
        boot twice to ensure caching of memory training occurred
	on each boot.

Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 22:57:50 +00:00
Stanley Wu 0c3845d2ee mb/google/volteer/variant/lindar: Update devicetree settings
Update I2C address for Goodix touchscreen and add ELAN touchscreen &
Synaptics trackpad device. Follow CB:47415 to correct HID over I2C
device to be level triggerd.

BUG=b:160013582
TEST=emerge-volteer coreboot and check system dmesg and evtest can get
device.

Change-Id: I070fb0e06b588f128253270502c9c2c427c62b84
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-13 22:50:13 +00:00
Michael Niewöhner 50a1072180 soc/intel/cnl: replace the remains of HeciEnabled by device state in dt
The option `HeciEnabled` was partly replaced by use of the device on/off
state in the devicetree in commit 3de90d1. The option has been removed
from the corresponding boards, so `HeciEnabled` is always 0 and ME
always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM`
is set.

Replace the option in the finalize function by the same dt state check
that sets the FSP option and drop the remaints of `HeciEnabled`.

Devicetrees still having `HeciEnabled` have been adapted to keep the
current behaviour.

Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 22:30:29 +00:00
Brandon Breitenstein 99b38a9c2f soc/intel/tigerlake: Add code for early tcss
In order for USB Type-C idisplays to be detected prior to loading Kernel
PMC IPC driver is needed to communicate with PMC in order to correctly set
the USB Mux settings. This patch is adding in support for early detection
of both Displays.

BUG=b:151731851
BRANCH=NONE
TEST=built and verified that TCSS MUX is being set on Volteer

Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42079
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 20:01:29 +00:00
Arthur Heymans 7598b4b40b soc/intel/xeon_sp/acpi.c Loop over HOB stack for MADT generation
To align MADT generation with DMAR, we loop over HOB entries instead
of over copied HOB entries fetched from get_iio_stacks(). This makes
it easier to see what is going on.

Tested on ocp/deltalake

Change-Id: I8ffe0322bb182b7ec5887354ec801e1f9f3d3288
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-13 19:37:43 +00:00
Arthur Heymans 6408ada4a2 soc/intel/xeon_sp: move get_iiostack_info() to a common place
All this function does is looping over IIO stacks in the FSP HOB. The
only 'SOC/FSP specific' thing is the way to detect if the stack is an
IIO stack so add a callback to determine this.

Change-Id: I4fa9c54d50279213a4174186a23c3cc156e21c9a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-13 19:27:33 +00:00
Arthur Heymans 165893b67b soc/intel/xeon_sp: Change the return type of get_iio_stack_info()
The somewhat unrelated return value makes the function harder to
understand and the return type is not consistently used. Use a
different helper function to get the HOB Pci64BitResourceAllocation
data.

Change-Id: I9a03cbb0ebbb48cc052d4c082d359c0087aaeb3e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-13 19:27:16 +00:00
Michael Niewöhner 89e83b76b4 soc/intel/common/block/acpi: add Kconfig for CPPC entries generation
Change-Id: Ieae9f221ffb27cf52cab21a130e18aa3929caea3
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47540
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 18:42:49 +00:00
Subrata Banik 11f212b825 mb/intel/adlrvp: Update WWAN GPIO as per latest schematics
WWAN_RST#: E10 -> F14
WWAN_PWR_EN: E13-> F21

Change-Id: I7182f384eb7a404dfe623c64e29467b41c6b0bdd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-13 17:56:55 +00:00
Subrata Banik 19325dac95 vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454
List of changes:
1. FSP-M Header:
- Add new UPD Lp5CccConfig
- Adjust Reservedxx UPD Offset
2. FSP-S Header:
- Adjust UPD Offset for Reservedxx, PsOnEnable, RpPtmBytes, PmSupport,
GtFreqMax, Hwp, TccActivationOffset, Cx, PchLockDownGlobalSmi,
PcieRpLtrMaxSnoopLatency, PcieRpLtrMaxNoSnoopLatency, UnusedUpdSpace45

Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47244
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 17:56:46 +00:00
Michael Niewöhner a1843d8411 soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and
set the FSP option for PM ACPI timer enablement from its value instead
of using the old devicetree option.

Also drop the obsolete devicetree option from soc code and from the
mainboards and add a corresponding Kconfig entry instead.

Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 17:32:37 +00:00
Michael Niewöhner 8a64ad09a1 soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disabling
FSP already disables the PM ACPI timer, when EnableTcoTimer=0.

Test: clevo/l140cu and supermicro/x11ssm-f have the PM ACPI timer
disable bit set when EnableTcoTimer=0.

Change-Id: If370d3acf87ae6d1d7c64bf27228877cdd92ab2d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-13 17:18:20 +00:00
Michael Niewöhner 5df952bc2b soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
Currently, the ACPI PM timer state gets set in devicetree by the option
PmTimerDisabled. However, it is not board design dependent. Thus, add a
user-selectable Kconfig option.

Disabling the PM ACPI Timer is only valid when PM Timer emulation is
supported and is only possible, when there is a hardware PM Timer (APL
does not have one for example). SoCs, where the hardware PM Timer can be
disabled must select `PM_ACPI_TIMER_OPTIONAL`.

This new Kconfig gets used in the follow-up commits of this series.

Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-13 17:18:08 +00:00
Angel Pons 12cfcd90dd mb/hp/folio_9480m: Update northbridge ACPI filename
Fix build errors, since `haswell.asl` was dropped in commit 79e3a1f8a5
(nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`)

Change-Id: Iaec5de2d74dd81c58a581bb511ba6a63629141aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47575
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 17:05:32 +00:00
Angel Pons 9fe0615ecc Doc/relnotes/4.13: Add several relevant changes
While some of these have little impact, they are worth mentioning here.

Change-Id: Idbf629ae77b8918ff1d93edb7b6c4669bbbe17df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-13 16:11:48 +00:00
Felix Held 16433c9c92 soc/amd: factor out _SOC_DEV macro into common block
TEST=Timeless build doesn't change for Mandolin and Gardenia.

Change-Id: I1aef68459569536207697bfca407145a7b5334f4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-13 14:42:49 +00:00
Felix Held a262fc6b07 soc/amd/common/block/include: make include guards more uniform
TEST=Timeless build doesn't change for Mandolin and Gardenia.

Change-Id: I5d3ae1459c333658f4c86388f1822d92ca13c658
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-13 14:42:39 +00:00
Angel Pons 33b92efa51 mb/supermicro/x11-lga1151-series: Fix up comment style
Change-Id: I5b6191d2b5f6fd6d127934eda56e3c24181b0c4c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47565
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 13:28:35 +00:00
Angel Pons 50650427dc mb/clevo/cml-u: Fix up comment style
Change-Id: Idefc15fec1d62d68d88e91c76f59e1a60a3996b6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47564
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 13:28:28 +00:00
Angel Pons ed222f12ec soc/intel/broadwell: Split up acpi.c
Change-Id: Ie9c57b6f5c226cee8797027941fa03e69de52923
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46796
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 13:26:02 +00:00
Angel Pons 1500dd081b soc/intel/broadwell: Flatten northbridge folder structure
Having folders for bootblock and romstage is no longer necessary.

Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46795
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 13:23:33 +00:00
Angel Pons 3bd017356a soc/intel/broadwell: Relocate CPU files
Change-Id: Ib2ddce78db21db9c8deac632a77ecd71eb9887c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46794
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 13:17:49 +00:00
Angel Pons a0426267e3 broadwell: Flatten `acpi_init_gnvs` function
Instead of relying on mainboards to call it, do like Lynx Point.

Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46793
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 13:17:31 +00:00
Angel Pons a472e33634 broadwell: Factor out `acpi_fill_madt` function
It is identical for all Broadwell mainboards, thus deduplicate it.

Change-Id: I74559fbe42e44aa4d15ced5d88f6c15a1bf5203b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46792
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 13:17:20 +00:00
Angel Pons c29d8e0468 nb/intel/haswell/acpi: Do not add PEG devices for LP
Haswell Low Power variants do not have PEG at all.

Change-Id: Ia5577104b00bfc8713b54c3c43f8dcdd3bc367df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46791
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 13:13:58 +00:00
Angel Pons 90f6a31bc2 nb/intel/haswell/acpi: Move PEG and CTDP includes downwards
This change is just to align with Broadwell.

Change-Id: I25a481503f5df79502f5ae60c87e7dacb781adad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46790
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 13:10:05 +00:00