If the LTE USB DB is connected, enable LTE-related settings.
Otherwise, disable LTE-related settings.
BUG=b:229938024, b:229048361, b:229040345
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I37719cee48370a04534067aa64a3aa77e453948a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
To make sure daughter board LTE existing, we update probe to DB ports
value of FW_CONFIG field, (https://partnerissuetracker.corp.google.com/issues/226910787#comment11)
as well as, refer to Google Henry and Ivan comments (https://partnerissuetracker.corp.google.com/issues/226910787#comment14)
BRANCH=dedede
BUG=b:226910787
TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I9ab4412b614ec665fbafc998756b805591982b65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch configures external V1p05/Vnn/VnnSx rails for Nereid
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1df4ea10798354f41fe9cce0f8c478930517207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This patch configures external V1p05/Vnn/VnnSx rails for Nivviks
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: If8da0dfe3059087526f74042be3c8b7e4a7ece82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This patch configures external V1p05/Vnn/VnnSx rails for adlrvp-n
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I06298eb1aec07eae34420c5736e912c707fefbc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:221461379
TEST=Verify the build for primus board
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I4d7d52bdeafe8b1b55822b5c8d040c94ce1f3878
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The Nvidia GPU supports another function named NBCI (NoteBook Common
Interface), which has some subfunctions which are required for the
Nvidia kernel driver to consume. The specification for this function
comes from the Nvidia GN20 Software Design Guide.
BUG=b:214581763
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I19eb9417923d297a084d6f5329682e91cd506a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The agah variant will include an Nvidia GN20 series GPU, therefore
select the INCLUDE_NVIDIA_GPU_ASL Kconfig to include the respective
ASL code into the DSDT.
BUG=b:214581763
TEST=build patch train
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icc718d01506ccb4dd42841239e96926f4ddaa9c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Some brya variants will use a GN20 series Nvidia GPU, which requires
quite a bit of ACPI support code to be written for it. This patch
lands a decent bit of the initial code for it on the brya platform,
including:
1) PEG RTD3 methods
2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods)
3) NVOP _DSM method
There will be more support to come later, this is all written to
specifications from the Nvidia Software Design Guide for GN20.
BUG=b:214581763
TEST=build patch train
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
On some x86 targets it the bootblock is loaded via a different
mechanism, like via the AMD PSP or Intel IFWI. Some payloads need that
pointer so add it to cbfs.
Note that on Intel APL this file is not used, which is why the
bootblock still needs to contain the pointer in the ARCH_X86 part.
It is not worth it to add logic to specifically deal with APL as this is
a legacy feature anyway.
For AMD non-car platform this fixes cbfs access in SeaBIOS.
Change-Id: If46e80e3eed5cc3f59964ac58e507f927fc563c4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use defines for a better reading of the code.
Change-Id: I8e696240d649c0ea2341b8f04b62eebffebc1d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64519
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on quick fix on this commit 7b0fe59be (soc/intel/ehl: Fix
logical bug for PseTsnGbePhyInterfaceType), disable PSE TSN
SGMII as the original intention is to set the PSE TSN phy
interface as RGMII.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Id2e05b19f156621a945110791038bc0d19a0aad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
By right if PseTsnGbeSgmiiEnable is disable,
PseTsnGbePhyInterfaceType should use RGMII setting.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: If593a5534716a9e93f99cb155fb5e86e12b1df17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to
provide common routine for reading skudid and boardid from Chrome EC.
BUG=b:229052726
TEST=emerge-skyrim coreboot chromeos-bootimage
Check the corresponding directory gets mounted to /run/chromeos-config/v1
Change-Id: I6aff02d29d44e95cd9b9e9485593c81f0d4a4b0e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
The audio codec used by crota has a level-sensitive interrupt,
therefore configure the GPIO pad as level-sensitive.
BUG=b:230418589
TEST=emerge-brya coreboot and verified pass
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I588c21e44b9bb17cd5a48bf5f22465ec328496e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fix descriptors for USB ports to align with their function and
placement with respect to the schematics.
BUG=N/A
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If57bebf9bffd4616c437ec655b64cab3298ac08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Update the PSP header to set the SOC FW ID to 0x0149 for
this platform
BUG=b:217414563
TEST=Build and verify header is set correctly
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic604ec96560c2d4d89c48c4a27528c5cfe4ca7e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There are efforts to have bootflows that do not follow a traditional
bootblock-romstage-postcar-ramstage model. As part of that CBMEM
initialisation hooks will need to move from romstage to bootblock.
The interface towards platforms and drivers will change to use one of
CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called
in the first stage with CBMEM available.
Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add 'pci_map_bus' function and PCIE_MEDIATEK config for MediaTek
platform.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Move the common APIs to pci_ops.c and IO based operations to
pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
In order to pass PCIe base address to payloads, implement pcie_fill_lb()
to fill coreboot table with PCIe info.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Remove the stop pin declaration for LAN. Confirmed with LAN vendor,
8111K do not need to implement stop pin. It caused S0ix fail.
BUG=b:232327947
TEST=Build and suspend_stress_test -c 5 pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9bdaa28cd879c1ea7de2de8afb25761df39bcfc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add 'lb_fill_pcie' function to pass PCIe information from coreboot to
libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the
__weak function.
ARM platform usually does not have common address for PCIe to access the
configuration space of devices. Therefore, new API is added to pass the
base address of PCIe controller for payloads to access PCIe devices.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
AGESA has a lot of code in the .data section (initialized data). However
there is no such section in CAR stages as the code runs in XIP mode and
CAR is too small to contain the data section. When the linker can not
match code to a section it will just append it, which is why AGESA
worked at all.
Follow-up patches will attempt to fix AGESA and set Kconfig parameter to
'n'. After all AGESA sources have been fixed, this can be removed.
Change-Id: I311ee17e3c0bd283692194fcee63af4449583d74
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Currently, the LTE pins are enabled in gpio.c, then disabled in
fw_config.c if LTE is not present. However, since there's a short delay
between mainboard_init() and fw_config_handle(), this means that when
LTE is not present GPP_H19 (SOC_I2C_SUB_INT_ODL, used for the SAR
sensor) will be floating for a short period of time.
Rework the GPIO config so that the LTE pins are disabled in the
baseboard, then enabled in fw_config.c for variants using LTE. However,
this doesn't work for WWAN_EN and WWAN_RST_L since they need to be
enabled in bootblock. So these are instead enabled in the variant
gpio.c, then disabled in fw_config.c if LTE is not present.
BUG=None
TEST=LTE still works on nivviks
Change-Id: I9d8cbdff5a0dc9bdee87ee0971bc170409d925a2
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
To make sure Realtek RTL8822CE suspend stress test smoothly, we remove
1c.7 as wireless LAN (WLAN) connects the signal PCIE_4 and it will map
to 1c.7. refer to Intel Simon comment (https://partnerissuetracker.corp.google.com/issues/230386474#comment12),
as well as, remove redundant 17.0 and 1c.6 that both are described by
baseboard/devicetree.cb
BRANCH=dedede
BUG=b:230386474
TEST=on beadrix, verified by Realtek RTL8822CE can run suspend stress
test properly.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ib418eed57f07afaa6b397b42a057808eab142f7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This patch fixes a potential corner case scenario where the value of
CONFIG_DEFAULT_CONSOLE_LOGLEVEL is less than `BIOS_SPEW` hence, coreboot
is unable to redirect FSP serial messages over UART.
Rather than passing hard coded `BIOS_SPEW` for the FSP debug handler,
this patch now calls get_log_level() function to pass the supported log
level while printing FSP serial msg.
BUG=b:225544587
TEST=Able to build and boot taeko. Also, able to see FSP debug log with
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8a18101f5c3004252205387bde28590c72e05b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64460
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.
We checked power on sequence requires enable pin prior to reset pin
delay of 50ms and add delay of 20ms to meet the sequence on various
eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in
chapter 7.2.
BUG=b:231291431
TEST=USE="project_crota" emerge-brya coreboot chromeos-bootimage
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Id9bed46e801602f3f327753053ec6a1ceb0656e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Follow this commit 95986169f (soc/intel/alderlake: Skip FSP Notify APIs)
to skip FSP Notify APIs.
Elkhart Lake SoC deselects Kconfigs as below:
- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
to skip FSP notify APIs (Ready to boot and End of Firmware) and make
use of native coreboot driver to perform SoC recommended operations
prior booting to payload/OS.
When deselecting these Kconfigs, cse_final_ready_to_boot() and
cse_final_end_of_firmware() in the common cse driver will be used
instead as required operations to perform prior to booting to OS.
Check out this CL for further info:
commit 90e318bba (soc/intel/common/cse: Add `finalize` operation for
CSE)
Additionally, create a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again config.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I477c204233f83bc96fd5cd39346bff15ed942dc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove two redundant `void *` casts in `clrsetbits32()` calls. In
addition, preemptively retype the `io_mem_base` variable in order
to avoid having to add casts in future commits.
Change-Id: Iae9c8189a6f8cd29181c52c2241789c6d392d77b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch adds the support to enable the external V1P05/Vnn rails
in S0 state via devicetree.
BUG=b:223102016
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I555e5607af15a5f5d83ef74321b1b71f17cca289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This patch updates the VccIn Aux Imon IccMax for ADL-N to SOC SKU
specific value of 27A.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified that VccIn Aux Imon IccMax value is set to 27mA.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: If09cd1112fac9b30ff04c45aa5a6062c2513c715
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
EC wake event doesn't work. Nissa has a separate EC wake pin. SCI only
is not handled by EC, so we need to set dual route to wake the system.
BUG=b:229142661
TEST=EC wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ide1f4a2494bb0a64b11ab4c5135fc43d2a635f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
There are two APL specific config switches for RAPL and min. cpu clock
(APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches
could be used in future in other CPU platforms. Move them to common code
instead of having them just for one SOC.
Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings
(MSR0x610) do not change with this patch applied on mc_apl{1,4,5}
mainboard.
Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Now that the bootblock isn't added to cbfs anymore, on some targets it's
only conditionally build. One example would be Intel APL where it only
gets build when stitched into an IFWI. This is always done when
compiling for real targets but not by the CI builder. This adds a dummy
target to make sure the bootblock always gets buildtested.
Change-Id: I60601e01a2c370b5c21493b71d51f495bb42f41d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
AGESA.h has a '#pragma pack' nested somewhere. The pack pragma packs all
structs which is not what is expected in the structs inside the headers
included below AGESA.h.
Change-Id: Ia70f68ea0ece7c097a37517206d75b71d695561f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's
state in the devicetree. This avoids having to manually make sure the
SMBus PCI device and the `SmbusEnable` setting are in sync.
Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Builds are failing sporadically with:
src/lib/master_header_pointer.c:5:10: fatal error: fmap_config.h: No such file or directory
5 | #include <fmap_config.h>
| ^~~~~~~~~~~~~~~
Correct the filename in the Makefile from header_pointer.c to
master_header_pointer.c so that there's a dependency from
master_header_pointer.c to fmap_config.h.
Change-Id: I41bcb2a21fdbc48f09d5b6be3e211ca56607d849
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64431
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Update override devicetree based on schematics.
2. Update Kconfig based on schematics.
BUG=b:229191897
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ia28ae16f609fda6d90558e69b2d41139dbe533fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Add the support RAM parts for mithrax.
Here is the ram part number list:
DRAM Part Name ID to assign
K4U6E3S4AA-MGCR 0 (0000)
K4UBE3D4AA-MGCR 1 (0001)
H9HCNNNBKMMLXR-NEE 0 (0000)
MT53E1G32D2NP-046 WT:A 2 (0010)
MT53E1G32D2NP-046 WT:B 1 (0001)
BUG=b:229191897
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I2d19721a44f0176365a81da30d2f49b68a14df7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Configure GPIOs according to schematics
BUG=b:229191897
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I31a1e02b2fa3d2075efbf488cd611b6c5a88500f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
The psp_notify_boot_done call is done at the entry of BS_PAYLOAD_BOOT,
so it's not guaranteed that the psp_set_spl_fuse call is done before the
psp_notify_boot_done call. Moving the psp_set_spl_fuse call makes sure
that it's done before the psp_notify_boot_done call. This also brings
the psp_set_spl_fuse call in line with the enable_secure_boot call that
sends the PSB fusing command to the PSP.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id76b462608c3d788cd90e73a64d18c8e8b89dbfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Hook up the hyper-threading setting from the FSP to the option API so
that related mainboards don't have to do that. Unless otherwise
configured (e.g. the CMOS setting or overriden by the mainboard code),
the value from the Kconfig setting `FSP_HYPERTHREADING` is used.
Also, remove related code from the mainboard kontron/bsl6, since it is
obsolete now.
Change-Id: I1023d1b94acb63f30455c56b394b68059deaaa16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On this mainboard there are legacy PCI devices connected behind a
PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This
patch disables the unused PCI clock outputs on the XIO2001 bridge.
Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tyler Wang