1. Add RECOVERY_MRC_CACHE region to reef FMAP.
2. Implement helper function for getting event for recovery mode with
memory retraining.
3. Select HAS_RECOVERY_MRC_CACHE.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified recovery mode behavior with and without memory training
request on reef.
Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17243
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or
RECOVERY_MRC_CACHE based on the boot mode.
- If normal mode boot, use RW_MRC_CACHE, if available.
- If recovery mode boot:
- Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is
requested explicity with retrain memory request.
- Use RECOVERY_MRC_CACHE otherwise.
2. Protect RW and RECOVERY mrc caches in recovery and non-recovery boot
modes. Check if both are present under one unified region and protect
that region as a whole. Else try protecting individual regions.
3. Update training data in appropriate cache:
- Use RW_MRC_CACHE if normal mode.
- Use RECOVERY_MRC_CACHE if present in recovery mode. Else use
RW_MRC_CACHE.
4. Add proper debug logs to indicate which training data cache is used
at any point.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified that correct cache is used in both normal and recovery
mode on reef.
Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17242
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Add new function vboot_recovery_mode_memory_retrain that indicates if
recovery mode requires memory retraining to be performed.
2. Add helper function get_recovery_mode_retrain_switch to read memory
retrain switch. This is provided as weak function which should be
implemented by mainboard just like {get,clear}_recovery_mode_switch.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified behavior of recovery mode with forced memory retraining on
reef
Change-Id: I46c10fbf25bc100d9f562c36da3ac646c9dae7d1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17241
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If this information is needed, use make V=1. That will print the actual
command, not a command that needs to be updated with every addition if
it's going to stay in sync.
Change-Id: I64d33d93c7fad3359d8ef78657bdb86d1fb4d4a1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17328
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
amdfwtool was getting the ROM size as a #define when it was built.
It has been updated to pass it in as a command line parameter, so
now it can be built just once for abuild as a shared tool.
Update the calls to amdfwtool to pass the ROM size.
All platforms using amdfwtool had the output verified using
a binary compare.
This reverts commit 0529236ed2
(Makefile.inc: Don't share amdfwtool between platforms)
Change-Id: I188b34e08249f2d00bd48957ced750b21f1ec348
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17327
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
- Return an error if the specified file could not be opened. To do this
cleanly, the return value was added.
- Since there's now a unified return value, use it where it makes sense.
- Don't return an error from --help. If you've asked for usage, it's
not an error.
Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17324
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This reverts commit 21fdd8d0b2.
I meant to abandon the original change and clicked submit instead.
Change-Id: I1db29b62c5c071113d308583f094f77285c9ba1e
Reviewed-on: https://review.coreboot.org/17346
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Various fixes for clang warnings:
warning: arithmetic on a pointer to void is a GNU extension
- change *rom from void* to char* and cast back to void* as needed
warning: implicit conversion changes signedness
- In ALIGN macro, pass in value as unsigned
warning: no previous prototype for function
- Change functions to static
warning: no previous extern declaration for non-static variable
- Change global variables to static
warning: comparison of integers of different signs
- Make loop variable 'i' unsigned
warning: variable 'output' may be uninitialized
- Make sure an output filename was specified
warning: implicit conversion loses integer precision
- cast fd_stat.st_size to the appropriate type
Change-Id: I0134a79c00938e121e63b52fd63bd502f4cb9e99
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17322
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Previously, the ROM size was passed into amdfwtool solely as a #define,
meaning that all boards built with the tool would assume the same size
ROM. This became a problem when the default rom for abuild was updated
to be a board with a 256KB ROM.
The temporary solution was to build amdfwtool individually for each
board that needed it. This replaces that workaround by allowing the
ROM size to be passed in as a command line parameter.
- Add the -f | --flashsize option to accept a hex value for the ROM
size.
- Add checks to make sure the ROM size supplied is large enough.
- Because the ROM size is not hardcoded, it needs to be passed to
various functions.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615
Reviewed-on: https://review.coreboot.org/17321
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This library is needed for calculating sha-256 of recovery mrc data in
romstage.
BUG=chrome-os-partner:59355
BRANCH=None
TEST=Compiles succesfully for reef.
Change-Id: Ie257208c7b3ad07d00e4eb777debf19c42a2fc0c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17271
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace the use of the old device_t definition inside
mainboard/kontron/986lcd-m.
Change-Id: Ib47a4bb3580cb72ee51fb06c6faa6d2d1bd3a80c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/intel/i82801dx.
Change-Id: I32888930d3742432a73dfc0a32c6586186e6757c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17297
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/jetway/j7f2.
Change-Id: I37f59f74ac22fbf6e036cdb0515301e8dec400fb
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17296
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/iei/pm-lx2-800-r10.
Change-Id: I60e5b84141aa4998427c3ecaadf8fce1654b8210
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17295
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/ibase/mb899.
Change-Id: Id5b460090db58e91b2c210d8633a69114a9c7f6b
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17294
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/getac/p470.
Change-Id: Ifb81976ed7068f9d51edb0d297cd4a12265c51ec
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17293
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
chip.h has a config array PcieRpClkReqNumber which corresponds
to a FSP UPD parameter, the size is currently set to 20.
However the size of PcieRpClkReqNumber UPD in FSP2.0 is 24,
so memcpy (config buffer to UPD buffer) in chip_fsp20.c will read
beyond the bounds of config array.
Hence set the size of PcieRpClkReqNumber array based on the FSP in use.
Found-by: Coverity Scan #1365385, #1365386
Change-Id: I937f68ef33f218cd7f9ba5cf3baaec162bca3fc8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/17292
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Newer AMD families have multiple models within them, each often
requiring unique support. The chip_name files were starting to
have a lot of duplication. Specify the model in the name, as well
as the family.
Change-Id: I236b260e2a565e212c486347c4a633eadcdf0042
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17187
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds definition FREQ_LIMIT_RATIO MSR. FREQ_LIMIT_RATIO
register allows to determine the ratio limits to be used to limit
frequency.
BUG=chrome-os-partner:58158
BRANCH=None
Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/17211
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add implementation to use actual requirements of ramstage size
for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB.
Only the required amount of low memory is backed up when ACPI_TINY_LOWMEM_BACKUP
is selected for the platform. Enable this option for AGESA and binaryPI, other
platforms (without RELOCATABLE_RAMSTAGE) currently keep their romstage ramstack
in low memory for s3 resume path.
Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15255
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Provide an option to deliver the mainboard smbios version in the
form of 'rev%d' based on the board_id() value.
BUG=chromium:663243
Change-Id: If0a34935f570612da6e0c950fd7e8f0d92b6984f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17290
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
There's no need to keep the snprintf() declaration hidden
for early stages. romcc is the entity that has issues. Therefore,
be explicit about when to guard snprintf().
BUG=chromium:663243
Change-Id: Ib4d0879e52c3f73c6ca61ab75f672f0003fca71f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17289
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
WACOM request to add a new identifier `WCOMNTN2`,
and use that for the board Pyro with all LCD combinations.
BRANCH=master
BUG=chrome-os-partner:58093
TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage
Signed-off-by: Janice Li <janice.li@quantatw.com>
Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307
Reviewed-on: https://review.coreboot.org/17257
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Dependencies on EC code should be specified at board level and not here.
We can include the file unconditionally in romstage and let the linker
decide if it's needed.
Change-Id: Ie2d1970ac1dd175a9d42651573a88cd866f19cb9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17123
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This change may slow down the raminit by maximum 200usec,
but reuses the lapic udelay definition.
Change-Id: I60a68f8a7911b257c0eecda96f7c5bf302bb51ed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17152
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The T400 features a socket P (mPGA478MN) and could potentially support
model_6fx CPUs.
Change-Id: I24f3356aa213c29011953daed31f46404e7a4d9d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17155
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This mobile CPU socket supports model_6fx and model_1067x.
Change-Id: Iecd6aae22831de7c3810545f0cb0be9738f96a2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17154
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Startpoint was Intel d945gclf, which has same chipset and
Gigabyte ga-g41m-es2l which has same Superio.
What works and is tested:
* PCI slot;
* PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card;
* onboard VGA output (only textmode implemented) with native graphic init;
* 533, 800, 1067MHz FSB CPU (1333MHz is unsupported by the chipset);
* serial output during and after boot.
What does not work:
* resume from suspend (does not work for d945gclf either).
Quirks:
* The Realtek ethernet card requires a reset which currently also
hardcodes a MAC adress.
This board was only tested with the SeaBIOS payload due to flash size
constraints (512KB) and with GNU/Linux.
Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17033
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Since IFD format is floating, ifdtool needs to be parameterized with a
chipset it is dealing with. Add -p <chipset> argument to ifdtool
invocations if chipset provides it.
Change-Id: I4fd1783b5d994617912aedcf17adc2a98c97227b
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17258
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Apollo Lake uses yet another descriptor format where only two masters
are used: CPU/BIOS and CSE/TXE. CSE stores data in a region number 5
that has not been used previously and CPU must not write it. Add quirk
(-p aplk) that locks descriptor according to recommended values.
BUG=chrome-os-partner:58974
TEST=ifdtool -p aplk -l bios.bin; ifdtool -d bios.bin.new. Make sure
FLMSTR1 and FLMSTR2 are set correctly. unlock with -l and make sure
FLMSTRs are restored.
Change-Id: I3f33372bef3ff75d0e34030694c79cd07d5540de
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17202
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
No boards left in the tree for this northbridge.
Change-Id: Id45da11b9d78cbd6bd50acb5a3c6c3c270f9020e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17281
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move old sockets to use romstage_legacy.c, these are ones
using intel/car/cache_as_ram.inc.
These will not be converted to RELOCATABLE_RAMSTAGE as boards
are candidates for getting dropped from the tree anyways.
Change-Id: I2616b4edee53446f1875711291e9dfed2911e2fb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17280
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure overcurrent pins for various usb ports.
Configure CdClock to 3.
Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17251
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Furquan Shaikh