Commit Graph

24342 Commits

Author SHA1 Message Date
Shamile Khan 12f345d671 mb/google/octopus: Configure pins to reflect delta w.r.t yorp
Changes in pin usage between yorp and bip
- LTE_OFF_ODL pin moved from GPIO_161 to GPIO_66
- I2S0 interface is not used in bip. It was used in
yorp for DMIC Wake on Voice through Nuvoton EC.

Also fix both bip and yorp pin settings for
LTE_OFF_ODL (Enable LTE and add an internal pull up).
Internal pull up can be removed later when sub-board (which
will have an external pull up for this signal) is available.

BUG=b:77869623
BRANCH=none
TEST=Build coreboot for octopus.

Change-Id: I8907bd63a43c4bc51ca991c3ec7c1cae9e39e2d1
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-02 07:58:50 +00:00
Patrick Georgi d13c4cd621 lib/cbfs.c: fix typo
Change-Id: I39c12ab3f28b5448fa4f46958cf23f2623a92378
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25928
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02 07:58:23 +00:00
Patrick Rudolph f5180a957a pci: Fix MMCONF_SUPPORT on non x86
Move x86 specific pci_bus_default_ops into arch/x86 folder.
Fixes compilation on platforms that do neither have MMCONF_SUPPORT
nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI.

Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02 06:54:22 +00:00
Subrata Banik 8cfd76d44e arch/x86: Print CPU Index and APIC ID in case of exception
BUG=b:74436746
BRANCH=none
TEST=Able to get APIC ID number for debug.

Change-Id: I2d3776c9259747197a5f2410032f9b03786407fb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-02 01:39:34 +00:00
Julius Werner 6dc7b220a3 software_i2c: Improve error behavior
This patch fixes a bug in the software_i2c (bitbang) framework where it
would previously not return an error when receiving a NACK on a write
transaction (deviating behavior from our hardware I2C drivers). It also
adds explicit error codes to be returned for the different kinds of
failure conditions so they are more useful for debugging when dumped.

Change-Id: Ie63bf35123d89dcd99a1f9c079d4cae6a33b0b09
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-05-02 00:23:30 +00:00
T Michael Turney 9b5c28af18 libpayload: Add Timer for sdm845
Uses ARCH64 Timer

TEST=build

Change-Id: Ic312bcf3bc7e80482b7f038e2dbc4abaaffd5956
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-01 23:35:25 +00:00
T Michael Turney 1e3e02a1d2 libpayload: Add raw_read_ functions
Add: raw_read_cntfrq_el0() and raw_read_cntpct_el0()

Required to support Arch64 Timer

Change-Id: I86aa97039304b9e9336d0146febfe1811c9e075a
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-01 23:34:03 +00:00
T Michael Turney 7978b8b725 sdm845: Add Timer support
Frequency set to 19.2 MHz

TEST=build

Change-Id: I56e57156df8a74cf629f7ada86cf5a5fcd5ad3c4
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-01 23:33:45 +00:00
Iru Cai d9105846bc asrock/b75pro3-m: fix the HDMI port
At the time I ported coreboot to this board, the HDMI port of my board
was broken, so I couldn't test libgfxinit on HDMI.

Change-Id: Ibb8a4ef55bd97fd2d0baacdbc72863c0985d3d76
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/25820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-01 19:20:26 +00:00
Nick Vaccaro 1799994730 mb/google/poppy: Add variant for nocturne
Add a new variant of poppy for the nocturne board.

Key differences from baseboard include:
- GPIO changes
- devicetree.cb changes
- memory stuffing option changes

BUG=b:78122599
BRANCH=none
TEST=./util/abuild/abuild -p none -t google/poppy -x -a

Change-Id: I11c7829041b3c45407c17f71b08cc7fc17f717e8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-01 19:19:02 +00:00
ivy_jian b7641e899c mb/google/poppy/variants/nami: Enable Synaptics touchpad
BUG=b:74595037
TEST=
1. emerge-nami coreboot chromeos-bootimage
2. check touchpad function
3. evtest
/dev/input/event5:	PNP0C50:00 06CB:CD84

Change-Id: I47cb1b13881f0d52860f0afe4bbca7483409de54
Signed-off-by: ivy_jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25913
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01 19:18:27 +00:00
Arthur Heymans 16a70a48c6 nb/intel/x4x: Change memory layout to improve MTRR
This change also makes sure that the sum the uma regions (TSEG, GSM,
GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between
2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR
setup for ramstage. At least tianocore requires this and fails to boot
without it.

Better MTRR are achieved by making the memory 'hole' till 4GiB exactly
2Gib.

This code mimics how it is done in nb/intel/gm45 and achieves similar
results.

TSEG is enabled and set to 8M since this makes it easier to reuse the
common smm setup / parallel mp code and makes it possible to cache the
ramstage in there like how it's done on newer targets.

TESTED on Intel DG43GT.

Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-01 17:42:30 +00:00
Arthur Heymans dfce932cf0 nb/intel/x4x: Fix programming CxDRB
Programming CxDRB should be cumulative as explained in "Intel ® 4
Series Chipset Family datasheet".

This does not seem to have any real impact but better do according to
the documentation and what vendor firmware does.

This also removes some dead code.

Change-Id: I7ff3264824c843f84b9eb6c06a06aa3f151fe4b3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22911
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01 17:41:49 +00:00
Arthur Heymans 95c48cbbb5 nb/intel/x4x: Implement both read and write training
This training find the optimal write DQ delay and read DQS delay
settings. It does so on all lanes at the same time, like
vendor (training each lane individually has poor results).

The results are stored in the sysinfo struct and restored on next
boots and S3 resume.

This potentially increases stability as optimal settings are chosen
and is more necessary for DDR3 raminit where the write DQS delays are
leveled/variable due to the flyby topology.

TESTED on Intel DG43GT with (2G + 1G) on each channel, see that the
results are quite close to the safe original ones (that previous
worked fine) and tested with memtest86+.

Change-Id: Iacdc63b91b4705d1a80437314bfe55385ea5b6c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-01 17:41:31 +00:00
Elyes HAOUAS 66f1bd2085 mainboard/hp/dl145_g3: Fix coding style
Change-Id: I78b43cbc052e6d243d67ca8cdd86b242e477a2c7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23532
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01 16:55:36 +00:00
Matthias Gazzari cc1e3b64ed Fix freeze during chipset lockdown on Nehalem
Remove locking of PCI device 00:00.0 registers (nehalem/finalize.c)
and remove setting the zeroth bit of the MSR_LT_LOCK_MEMORY = 0x2e7 MSR
register (model_2065x/finalize.c) to fix a frozen boot and S3 resume issue
which became apparent with commit d533b16669.

More detailed, either setting the LSB of the 32 bit register at 0x98
of the PCI device 00:00.0 (in the intel_nehalem_finalize_smm function) or
setting the LSB of the the MSR register MSR_LT_LOCK_MEMORY = 0x2e7 (in the
intel_model_2065x_finalize_smm function) indepentenly causes a freeze
during bootup or a complete session loss on resuming from S3 as described
here: https://mail.coreboot.org/pipermail/coreboot/2018-April/086564.html

It seems like Nehalem CPUs do not have a MSR_LT_LOCK_MEMORY register.
Additionally, the "Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile
Processor Series, Datasheet Volume Two" indicates that registers of the
PCI device 00:00.0 cannot be locked manually. Instead, they can only be
locked by TXT, VT-d, CMD.LOCK.MEMCONFIG, ME_SM_LOCK or D_LCK.
Finally, the addresses and sizes of these registers were partially wrong.

Tested on Lenovo X201i with a Core i3 330M (no AES-NI, no VT-d and no TXT
support compared to the Core i5 and Core i7 processors of a X201).

Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/25914
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01 16:23:56 +00:00
Martin Roth 15f232df08 chromeec platforms: Update ACPI thermal event handler call
Currently the thermal event handler method TEVT is defined as an extern,
then defined again in platforms with thermal event handling.  In newer
versions of IASL, this generates an error, as the method is defined in
two places.  Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.

Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-01 15:54:55 +00:00
Subrata Banik 3dc02ff637 drivers/intel/fsp2_0: Include MP services header for UDK2017 supported platform
BRANCH=none
BUG=b:74436746
TEST=Able to include EFI_MP_SERVICES_PPI without any error.

Change-Id: I5add8e533dfd3f6d03abf7b2ca1a83f81f1c5920
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-01 13:30:14 +00:00
Elyes HAOUAS 9c5d4634dd southbridge/intel: Remove space before/after parenthesis
Change-Id: Id1bc0c88aeecc3f1d12964346326e5b087a2985e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25880
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-30 16:26:43 +00:00
Patrick Rudolph 9ab9db0bc5 lib/bootmem: Introduce custom bootmem tags
Introduce bootmem custom memory tags and use them instead of reusing
LB_MEM tags.
Use asserts in bootmem_add_range to verify parameters.

Tested with uImage payload on Cavium SoC.

Change-Id: I7be8fa792fc7933ca218ecd43d250d3a9c55caa6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30 09:33:49 +00:00
Patrick Rudolph 666c172d38 lib/devicetree: Integrate flattened devicetree support
* Adapt to coreboot coding style.
* Use coreboot's endian conversion functions.
* Fix header and header guards.
* Get rid of unused functions.
* Add Kconfig to build it on ramstage.
* Replace size32 with ALIGN_UP and DIV_ROUND_UP.
* Add NULL pointer checks
* Convert constants to defines

Required for Cavium's BDK and uImage FIT support.

Change-Id: I6e6cd9f78fb402bd54d684097326d26eb78d552a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30 09:33:32 +00:00
Patrick Rudolph 67aca3e7dc lib: Raw import FDT devicetree from depthcharge
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge
Required for general devicetree patching and FIT support.

Coding style and coreboot integration will be done in a separate commit.

Change-Id: Ida75d4786eae38d84bfc71bf53573dafca8eda40
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30 09:33:21 +00:00
Arthur Heymans 4c81d4464f mb/lenovo/x220: Allow optional use of the mrc.bin
Besides the FSP codepath, Sandy Bridge has two codepaths, one native
and one in the form of a binary. This allows the use of the binary.

This can be useful to find flaws in the native raminit.

The native raminit is still selected by default.

Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-30 09:32:23 +00:00
Iru Cai 317bb56428 asrock/b75pro3-m: use the ASPM blacklist driver
After commit 2188f57a (src/device: Update LTR configuration scheme)
coreboot will hang when reading resources on the ASMedia SATA
controller, although there is already an ASPM config override. So use
the ASPM blacklist driver instead of setting the ASPM override in the
devicetree.

Change-Id: I807d9bd4deef8c1528dff96c7646240ef75e1953
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/25819
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-30 09:26:42 +00:00
Elyes HAOUAS 09d1d5969d nb/intel/fsp_rangeley: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: I0b969a5109276d108e6140bad338c74786b967f3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:24:11 +00:00
Elyes HAOUAS f925c56fe9 cpu/intel: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: I17675b004023453f137abd387cfacd308d9b98b5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:23:58 +00:00
Elyes HAOUAS d2d8a31305 cpu/amd: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: I4b930a191130941c8349861cdd803a5be4219274
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23653
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-30 09:23:47 +00:00
Elyes HAOUAS fc1b49691f cpu/x86: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: I4c8acebb4a957a9600de15ea844f620a8909977b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:23:38 +00:00
Elyes HAOUAS 64d2d106a4 nb/intel/i440: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: Ibd01659f518b7a2b1aaf334fe5b16cfb936b68b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:23:28 +00:00
Elyes HAOUAS 6275360d56 nb/intel/pineview: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: Icec2e5f722c1f15493e5861b47f64698250f5813
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:23:18 +00:00
Elyes HAOUAS ab8743c02e nb/intel/sandybridge: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: I585aa48b99f4ef63905cab5d6d1502bfed0e6e42
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:23:09 +00:00
Elyes HAOUAS 706aabcd4c nb/intel/nehalem: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: Idcb8ff4081f2c45427aabb455a70fae1b46bcfc4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:22:44 +00:00
Elyes HAOUAS fea02e1439 nb/x4x: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: Ib3e708a7fa9f0a78dc704a502a2f01ee0fe209ae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:22:32 +00:00
Elyes HAOUAS 658a9348f0 nb/intel/i945: Get rid of device_t
Use of `device_t`has been abandoned in ramstage.

Change-Id: I2cc938958097e416b85f6592cb8a4e645a3746ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:22:19 +00:00
Elyes HAOUAS 6dcdaaf205 nb/intel/gm45: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: If064a4027265e8fc2ea919d9742a554abf29b8db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:22:04 +00:00
Aaron Durbin a8bb6c10c5 soc/intel/braswell: remove stale spi_loading.c
CONFIG_ALT_CBFS_LOAD_PAYLOAD has long since been removed.
Clean up the remnants in braswell.

Change-Id: I88483a4c3a74ed0c7defacf872b1564c3ce7f909
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-30 09:21:21 +00:00
Caveh Jalali 2261e91ad8 google/poppy: enable trackpad as wake source
This configures GPP_A23 as a wake source for the trackpad.  We also
need to set up GPP_A GPE0_DW0, thus evicting GPP_B.  We don't have any
interesting signals in GPP_B, so we won't be missing it.

I don't have hardware with A23 wired up, so i just tested the wake
source using A19 which is essentially identical to A23.

BUG=b:78541883
TEST=verified we can trackpad can wake system from suspend

Change-Id: If800464c8b2319d758b1823850571919f85bdc6c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/25850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-30 07:41:24 +00:00
Richard Spiegel 7a52c17f16 soc/amd/stoneyridge/gpio.c: Fix gpio_output()
Function gpio_output() is only setting the pin as an output, when in fact
it should also set the state (high/low) of the pin. Fix the procedure to
set the state of the pin.

BUG=b:78328773
TEST=None

Change-Id: I516192a0782a9bbb40124029f264a2711114c800
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-30 06:28:01 +00:00
Daisuke Nojiri ccfa18feff cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amode
Currently, google_chromeec_pd_get_amode infinitely loops if a TCPC port
is connected to a device with alternate mode(s) and the call is made
for the mode with the index higher than 0 (e.g. Zinger).

Cros EC manages alternative modes entered in an array (amode[]). The
command is designed to accept a query for an particular index and a
particular SVID.

Zinger has a 'Google' mode. It's stored in amode[0]. When AP queries
first time for DisplayPort with index=0, EC says 'no' as expected.

AP sends the next query with index=1 but EC_CMD_PROTO_VERSION (0x00)
is sent instead because cmd_code is cleared by google_chromeec_command.
res.svid is supposed to be 0 when EC hits the last index + 1 but
res.svid is set to 2 by the EC_CMD_PROTO_VERSION handler because
EC_PROTO_VERSION is currently 2. So, the call succeeds and AP goes to
the next index and this repeats forever.

Any USB-C device with non-DisplayPort alternate mode can cause this
hang unless HDMI port is used.

This patch resets all the fields of chromeec_command in each iteration
in case google_chromeec_command changes them.

BUG=b:78630899
BRANCH=none
TEST=Verify Fizz boots without monitors on Zinger. Verify the svid
enumeration happens as expected.

Change-Id: I388ed4bdfac9176d8e690c429e99674ed267004f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/25878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-30 06:27:24 +00:00
Julius Werner c01a9ab562 cubieboard/qemu-armv7/am335x: Add fake TTB region for consistency
All ARM architecture boards are supposed to have a TTB region for their
page tables. ARM systems cannot use the data cache without enabling
paging, so it is imperative to do that as soon as possible. They will
also fault on unaligned accesses when not using the cache, which breaks
assumptions in CBFS code.

Unfortunately, we have some old boards in various stages of disrepair in
the tree that don't always follow these sorts of standard conventions.
It's not clear whether they actually boot anymore and if anyone still
has the respective hardware available to maintain them. I cannot really
fix and test them right now, but we should at least create a fake TTB
section for them so that common architecture code may make the correct
assumptions about which regions exist.

Change-Id: I51aa259fbb7a9c0ade72db905b1762c1c721f387
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30 06:26:41 +00:00
T Michael Turney 3775f1c0e1 arm64: Add ARCH Timer
SoC sdm845 uses ARCH Timer

Change-Id: I45e2d4d2c16a2cded3df20d393d2b8820050ac80
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30 06:25:58 +00:00
T Michael Turney 6e0f0f7f9c arm64: Add mmu context save/restore APIs
New API required by sdm845 DDR init/training protocol

TEST=build & run

Change-Id: I8442442c0588dd6fb5e461b399e48a761f7bbf29
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30 06:25:15 +00:00
Werner Zeh 7850b5836b cbfstool: Add region offset information to layout command
The layout command prints all FMAP regions in the final image among with
the region size. Extend this command to show the offset of each region
in the image.

Change-Id: I5f945ba046bd2f1cb50a93e90eb887f60c6fde8a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30 06:24:12 +00:00
Justin TerAvest 3a2fd57e71 mb/google/octopus: Create phaser variant
This creates a phaser variant for octopus. Nothing is set in the variant
files here; everything is picked up from baseboard.

BUG=b:78572180
TEST=None

Change-Id: Ia03e8af91741f1f7aa3a42ac28688b8b6a708932
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-30 06:23:33 +00:00
Ravi Sarawadi 036aff9e65 mb/google/octopus: save dimm info as SMBIOS Table-17
Save FSP provided memory HOB info as SMBIOS Table-17 format.
Firmware tools such as mosys, dmidecode uses SMBIOS Table-17 to
report memory metadata.

BUG=b:78651920
TEST=Build for Octopus and check 'dmidecode -t17' and
'mosys memory spd print all' to verify dimm info.

Change-Id: I9b032b766a2927725b2378f7f720644d4459f602
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/25881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-30 06:23:13 +00:00
Lubomir Rintel 294446a137 x86/mpspec: order the I/O APICs by the APIC Id
Linux (4.16) assumes that the PIT interrupt is connected to the pin 0 of the
IOAPIC[0] and panics otherwise.

This might be a Linux bug. The MP Specification 1.4 does seem to mandate
sequential ordering for bus entries, but not for the I/O APICs.

Change-Id: Ibf823eb5b3a29e4590cba915069cdfe5f780edcd
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30 06:22:46 +00:00
Lubomir Rintel 9ba8f7c28e device: constify some variables
Change-Id: I6830a65bc9cea2907f4209bb97a53ccebcbf248d
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25873
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-30 06:22:13 +00:00
Hannah Williams ecef322bf4 mb/google/octopus: Fix crossystem wpsw_cur error
With only one entry for Write Protect gpio in the OIPG package, the sysfs
entry /sys/devices/platform/chromeos_acpi/GPIO.x is created as "GPIO"
instead of "GPIO.x". This was causing crossytem to return error for wpsw_cur.

BUG=b:78009842

Change-Id: Ica60f342420d95d09a45580f2f940443c03601de
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-30 03:23:36 +00:00
Paul Menzel 621abec1e8 sb/amd/cimx/sb800: Remove unused variable
scan-build from Clang 4.0.1-3 from Debian Sid/unstable warns about the
issue below.

```
    CC         ramstage/southbridge/amd/cimx/sb800/lpc.o
src/southbridge/amd/cimx/sb800/lpc.c:102:6: warning: Value stored to 'end' is never read
                                        end = resource_end(res);
                                        ^     ~~~~~~~~~~~~~~~~~
1 warning generated.
```

The variable is only used in the commented out print statement. So,
remove the unused variable, and directly use the value directly in the
print statement.

Change-Id: I3f759f6361ffeb07980cb10e17930e11d738a6a7
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-29 18:26:46 +00:00
Elyes HAOUAS 03f2536f9d libpayload/drivers/usb/ohci_private.h: Add parentheses around macro
Change-Id: Ib90564e32f5ff204aa5d856024b7eed2624a77b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-29 18:13:08 +00:00