Commit Graph

825 Commits

Author SHA1 Message Date
Jeremy Soller b44202b29a mb/system76/oryp8: Add System76 Oryx Pro 8
https://tech-docs.system76.com/models/oryp8/README.html

Tested with TianoCore (UeifPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack*
- S3 suspend/resume
- Booting to Pop!_OS Linux 21.10 and Windows 10 20H2
- Flashing with flashrom

Not working:

- Discrete/Hybrid graphics

Not tested:

- Thunderbolt functionality
- S/PDIF output

Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 20:48:37 +00:00
Jeremy Soller fdaccd875d mb/system76/bonw14: Add System76 Bonobo Workstation 14
Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 20:48:29 +00:00
Jeremy Soller c840bc4e32 mb/system76/oryp6: Add Oryx Pro 7 as a variant
Change-Id: Id00a45a6a6acf0880934c55f1a3f18e63f2aed43
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:21:41 +00:00
Felix Singer 8bea7027cd Documentation/releases/4.15: Fix typo
Change-Id: I3e64793c58f2acfbfc42e46782d68bec97088601
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-11-01 03:24:04 +00:00
Jason Glenesk 18b34f98ba Documentation/releases: Update index.md
Change-Id: I0fa24b233383bdc778b2c641f68e4e87f92206d1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-30 19:05:28 +00:00
Jason Glenesk 079c3f28ce Documentation/releases: Add 4.16 release notes template
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I42ce11914d7e7b32017747bbc6d3c7ac77e2868b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58758
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-30 19:04:35 +00:00
Patrick Georgi c69da57d63 Documentation: Open up avenue for codifying our best practices
Change-Id: I3a2612ae64ecea2d1d7ecb695215bc50dccb1b19
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58663
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-29 06:31:29 +00:00
Paul Fagerburg aae5cdf1aa Documenation: call out `lcov` as required
Code coverage requires `lcov`, so update the docs to call it out
specifically.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie2898faa5188a7174c4e56ba34f1a4f02f939b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-29 05:09:57 +00:00
Jason Glenesk 2c78ee2997 Documentation/releases: Update 4.15 release notes
Update details for upcoming 4.15 release

Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I4517f7c17ce5788c82a1eafb1589e39b1ce403ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58422
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-28 09:35:58 +00:00
Patrick Georgi 2f105ed9ab Documentation: Remove libretrend from coreboot distributors
As of 2020-07-21 their website says "we'll stop any device produce
and won't have a date to return (if we return)."

While wishing them best of luck (and welcome them back to the list
of distributors), let's take them off the list while they don't
ship hardawre.

Change-Id: Ia110d0e25bf73c3d7db270b0c2c0e23b99fc36ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-27 14:51:41 +00:00
Jakub Czapiga 965b05adaf Documentation/releases/4.15: Add note about libpayload improvements
Change-Id: I3043e70523db1b7f1df90789a69eadd155848bb0
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-10-26 16:27:56 +00:00
Patrick Georgi 0c12bdc9f8 Documentation: Improve preamble of coding style
The coding style doc isn't short, so scrap that, and it's specific to
the C parts of our tree, so add that.

Change-Id: Ib1ef7c1a96ff40f0cfbae7d22a47a95128981eb8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58381
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-17 11:47:01 +00:00
Angel Pons d4d4f08f54 Doc/releases/coreboot-4.11-relnotes.md: Fix typo
Replace `bee` with `been`.

Change-Id: I206f9b33d79386fc4f204db3e21a92fa20b703bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-16 01:04:52 +00:00
Angel Pons 6c08b1ff81 Doc/mainboard_io_trap_handler_sample.c: Drop file
Looks like nothing references this example. Remove it. If one needs an
example, there's several mainboards which contain an I/O trap handler.

Change-Id: I4a238fbf354926cb6568e1709bfb79cc546dfd73
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-15 18:25:48 +00:00
Patrick Georgi 3394f4a8f6 Documentation: Explain how to join Slack
Change-Id: I6a4d5011ea47576c9a459f20e0b368cff8a326c2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-08 15:42:25 +00:00
Martin Roth 6c3ece9c9e Documentation: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05 18:06:24 +00:00
Sheng-Liang Pan 2970f45fe6 mb/google/trogdor: Add new vaviant quackingstick
New boards introduced to trogdor family.

BUG=b:201263032
BRANCH=none
TEST=make

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I8299ddda14eb82103f17f8464a14992aa757afa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-04 22:40:03 +00:00
Jonathan Zhang 7f1e6f2727 doc/mainboard/ocp: update Delta Lake documentation
Update Delta Lake documentation upon:
* Delta Lake and Yosemite-V3 design specs acceptance by OCP.
* Delta Lake OSF acceptance by OCP.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I315db879b75f0df2fbca2fa8bb6d00987a69efba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-09-23 06:28:39 +00:00
Tim Crawford 67772d27a6 mb/system76/addw1: Add Adder WS 2 as a variant
Change-Id: I3965a90151bd9250a87dabc715d68a39699ff9e1
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-22 13:46:59 +00:00
Tim Crawford 6a93a45242 mb/system76/addw1: Add System76 Adder Workstation 1
Change-Id: I5dd3bc320ca640728e1d86180c6bfa0dc7295760
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-22 13:45:55 +00:00
Tim Crawford 800754fea3 mb/system76/cml-u: Add Darter Pro 6 as a variant
Change-Id: I9ba7d2af3c9c298fda2b2997d52546cc2f702a82
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-20 12:11:50 +00:00
Tim Crawford f8ba8980fd mb/system76/cml-u: Add System76 Galago Pro 4
Change-Id: I3dfa2ab430439d8dc71531b92aa7800db94d603b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-20 12:11:28 +00:00
Tim Crawford 42e61fbb32 mb/system76/darp7: Add System76 Darter Pro 7
https://tech-docs.system76.com/models/darp7/README.html

Tested with TianoCore (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe SSD
- M.2 SATA SSD
- MicroSD card reader
- All USB ports
- USB-PD
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- HDMI output
- DP over USB-C output
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone/microphone jack
- S0ix suspend*
- Booting to Ubuntu Linux 21.04 and Windows 10
- Flashing with flashrom

Not working:

- S0ix when a device is attached to the TBT port

Not tested:

- Thunderbolt functionality

Change-Id: I80e5c5375f9d3881fc89a45a91ba68ed2e104a93
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52349
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16 17:28:00 +00:00
Angel Pons 184d5d0429 Doc/Intel: Remove out-of-date documentation
There's dead links, CorebootPayloadPkg was replaced by UEFIPayloadPkg,
the development procedures are severely out-of-date, the only FSP 1.1
platform is Braswell (which is no longer actively developed), and the
pages don't appear in doc.coreboot.org (which uses Sphinx to generate
HTML pages from .md files). Oh, and it doesn't seem to have a license
associated to it.

Get rid of outdated documentation.

Change-Id: If359f554e85d32cdb65c3d928b5155db30bc40a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-15 22:43:44 +00:00
Tim Crawford 94594608be mb/system76/galp5: Add System76 Galago Pro 5
https://tech-docs.system76.com/models/galp5/README.html

Tested with TianoCore (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe SSD
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- HDMI output
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone/microphone jack
- S0ix suspend*
- Booting to Pop!_OS Linux 21.04 and Windows 10
- Flashing with flashrom

Not working:

- Discrete/Hybrid graphics
- S0ix when a device is attached to the TBT port

Change-Id: I0d9052c0b064d4d43812ad837578d4a097149cc8
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15 15:30:48 +00:00
Tim Crawford 4dcee4f21d mb/system76/lemp10: Add System76 Lemur Pro 10
https://tech-docs.system76.com/models/lemp10/README.html

Tested with TianoCore (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- DIMM slot and onboard RAM
- Both M.2 NVMe SSDs
- MicroSD card reader
- All USB ports
- USB-PD
- Webcam
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- HDMI output
- DP over USB-C output
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone/microphone jack
- S0ix suspend*
- Booting to Pop!_OS Linux 21.04 and Windows 10
- Flashing with flashrom

Not working:

- S0ix when a device is attached to the TBT port

Change-Id: I15f7a3b6e9af07fcfde9a71d3f4a84ed625159b7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15 15:30:03 +00:00
Maxim Polyakov 7e45bb1a12 documentation: Update information about Kontron mAL10
1. The video output now works correctly with Intel IGD (tested with
   TianoCore, edk2-stable201903-3392-gf7fe27d686).
2. The kempld EC driver now supports GPIO configuration since
   commit 9941e5a5e6 (ec/kontron/kempld: Add minimal GPIO driver).
3. CorebootPayloadPkg is practically dead by now, so delete the comment
   about the problem with it.

Change-Id: Ic216c3437b2670638c845ee8964f831b80e18fce
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15 13:52:51 +00:00
Kevin Chiu a472c54a63 google/trogdor: add new variant kingoftown
This patch adds a new variant called kingoftown.
it's clamshell only, no FPR, eDP panel.

BUG=b:198365759
BRANCH=master
TEST=make

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I648664c50dfad11530a854f574f39264158b44e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-15 01:13:44 +00:00
Arthur Heymans c2d0a494a3 intel/xeon_sp/cpx: Hook up public microcode release
Change-Id: I7e575cb17e2004bd931f4fa1d05f17c4cdca29ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-09 14:40:37 +00:00
Peter Marheine 8e1a767c9c documentation: add a section on devicetree refs
There is no existing documentation on how `device ref` and aliases work
in the devicetree, and the behavior around devices not being in the same
location is difficult to discern as well as somewhat unexpected.

This should help prevent confusion leading to bugs such as the one fixed
by https://review.coreboot.org/c/coreboot/+/57298

Change-Id: I4b30f7d531cfc3453d6523a76084f1969125b4bf
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57354
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-07 01:24:37 +00:00
Bill XIE d00febc99b mb/supermicro: Add X9SAE and X9SAE-V
Mainboard information can be found in the included documentation.

Change-Id: I9dfc58bb99e14cd9dac2ac53afc0ea11d2252aa9
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-05 20:37:50 +00:00
Iru Cai cd8267b69c Documentation: add Intel Broadwell
Change-Id: I0b1c29162a64030b5c100368f2471702e22b8311
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-02 23:33:39 +00:00
Jakub Czapiga 7c6081e02b tests: Improve test output readability
When running multiple tests, e.g. by using unit-tests target, it is hard
to differentiate, which output comes from which file and/or
configuration. This patch makes the output easier to analyze and
understand by using new wrapper macro cb_run_group_tests(). This macro
uses __TEST_NAME__ value (containing test path and Makefile test name)
as a group name when calling cmocka group runner.

Example:
 Test path: tests/lib/
 Makefile test name: cbmem_stage_cache-test
 Test group array name: tests
 Result: tests/lib/cbmem_stage_cache-test(tests)

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4fd936d00d77cbe2637b857ba03b4a208428ea0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-01 19:38:09 +00:00
Johnny Lin 15fc6cf3c6 Doc/mb/ocp: Add hyperlink to src/mainboard/ocp/deltalake/vpd.h
It would be easier for people to find the defined variables.

Change-Id: I6d181f6602aa5d55019ea2110b2d8e1fa7e0159c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-09-01 15:22:05 +00:00
Felix Singer 0dcdb217cf soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.

If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.

Also, add a release note for the upcoming 4.15 release.

Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28 18:21:26 +00:00
Johnny Lin b69d1dea47 Doc/mb/ocp: Update Delta Lake documentation for RAS features
Change-Id: I71b97930f1a1ca4a60f830a90d80af6ca0236c8e
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-08-27 02:51:59 +00:00
Julius Werner 5ff1808f20 device/mipi: Move to drivers/mipi
Sounds like we prefer to have this under drivers/ instead of device/.
Also move all MIPI-related headers out from device/ into their own
directory.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-26 15:18:45 +00:00
Yu-Ping Wu d019bfc2d1 Documentation/util/kconfig: Remove silentoldconfig
The "silentoldconfig" target has been removed in Linux 5.13's kconfig
(CB:37152). As explained by Michal Marek at
https://lkml.org/lkml/2011/8/31/189, the "silentoldconfig" target has
become an internal interface and "oldconfig" is just as silent now.
Therefore, correct the target for syntax checking.

Change-Id: I8416bd4a96d15415f46c591ceb26ebb29aef1ab0
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-08-16 14:53:01 +00:00
Patrick Rudolph ad82106eb9 Documentation: Mark ECC as working on Sandy Bridge
Change-Id: I9f9aa5bf6ed4e1430e7067bfe5d3ce8e59e85812
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-16 14:46:13 +00:00
Zanxi Chen b412638c5a mb/google/trogdor: Add new variant Wormdingler
New board introduced to trogdor family.

BUG=b:193870279
BRANCH=none
TEST=make

Change-Id: If3d9662e8725e30e1308d77b05545efbee29f846
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-08-12 17:39:18 +00:00
Werner Zeh 06bc2c8498 Documentation: Remove KASAN from the project ideas list
This project is already implemented and therefore should not be
mentioned anymore as a new project idea in the documentation.

Change-Id: I38c6e274e416b98485943d36536a57a14743945b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-14 08:15:20 +00:00
Patrick Georgi 53ea1d44f0 util/kconfig: Uprev to Linux 5.13's kconfig
This was originally several commits that had to be squashed into one
because the intermediate states weren't able to build coreboot:

 - one to remove everything that wasn't our own code, leaving only
   regex.[ch], toada.c, description.md and Makefile.inc.
 - one to copy in Linux 5.13's scripts/kconfig and adapt Makefile.inc
   to make the original Makefile work again.
 - adapt abuild to use olddefconfig, simplifying matters.
 - apply patches in util/kconfig/patches.
 - Some more adaptations to the libpayload build system.

The patches are now in util/kconfig/patches/, reverse applying them
should lead to a util/kconfig/ tree that contains exactly the Linux
version + our own 5 files.

Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-13 20:28:14 +00:00
Sumeet Pawnikar 590eb2bb9c Documentation/drivers/dptf: Add oem variables support
Add oem variables information with usage example.

BRANCH=None
BUG=b:187253038
TEST=Built and tested on dedede board

Change-Id: I45db17f6ee3328da28f985c6854d65a430c9c61b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08 15:49:55 +00:00
Angel Pons 16fe5e1511 src: Consolidate x86_64 support Kconfig
Introduce `USE_EXP_X86_64_SUPPORT` in `src/arch/x86/Kconfig` and guard
it with `HAVE_EXP_X86_64_SUPPORT`. Replace the per-CPU implementations
of the same functionality with the newly-added Kconfig options. Update
documentation and the config file for QEMU accordingly.

Change-Id: I550216fd2a8323342d6b605306b0b95ffd5dcd1c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02 08:19:21 +00:00
Bill XIE 3b1a9944aa mb/asus/p8x7x-series: Add P8C WS as a variant of P8X7X series
Mainboard information can be found in the included documentation.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Idb696193e5a67c42adf45e54d455d2dff7681ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-01 09:42:34 +00:00
Zanxi Chen 4dce0990f9 mb/google/trogdor: Add new vaviant mrbland
New boards introduced to trogdor family.

BUG=b:191800434
BRANCH=none
TEST=make

Change-Id: I93b74e79188bd0cc36c8b48e552230ae0d6f593a
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-24 21:06:20 +00:00
Bill XIE 1109246cd1 mb/asus/p8x7x-series: Add P8H77-V as a variant of P8X7X series
Mainboard information can be found in the included documentation.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ic811e24bd72da84e5ca8f5b09f2eb65872153b72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55111
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16 09:52:56 +00:00
Bill XIE 8dd8f66807 mb/asus/p8z77-series: Add P8Z77-V as a variant of P8Z77 series
Mainboard information can be found in the included documentation.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-14 05:31:50 +00:00
Krystian Hebel dee3bc34ad docs/flashmap: state the endianness of FMAP
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: Idf6d46ed262b18c176d69352e333c56f4fdff66a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-06-11 07:41:59 +00:00
Patrick Georgi ce55ca2fca tests: Rework mocking facility
Using the linker's --wrap feature has the downside that it only covers
references across object files: If foo.c defines a() and b(), with b
calling a, --wrap=a does nothing to that call.

Instead, use objcopy to mark a weak and global so it can be overridden
by another implementation, but only for files originating in src/.

That way mocks - implemented in tests/ - become the source of truth.

TEST=Had such an issue with get_log_level() in a follow-up commit, and
the mock now takes over. Also, all existing unit tests still pass.

Change-Id: I99c6d6e44ecfc73366bf464d9c51c7da3f8db388
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-06-10 19:26:46 +00:00
Yunlong Jia aee70a8a8e google/trogdor: Add new variant Pazquel
This patch adds a new variant called Pazquel that is identical to Lazor
for now.

BUG=b:187232137
TEST=make

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ib531ea5df19fe91e619f23baada73842554538ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-08 21:29:58 +00:00
Tim Wawrzynczak fb1858539f Revert "src/mainboard: Add Star Labs labtop series"
This reverts commit 2e665eb8da.

Reason for revert: Was submitted too early and out-of-order.

Change-Id: I119b7a81b849bbe3424d73d5fdf9b55481444686
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54971
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04 18:52:32 +00:00
Sean Rhodes 2e665eb8da src/mainboard: Add Star Labs labtop series
Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-04 17:21:21 +00:00
Arthur Heymans 098f1fa802 Documentation/community: Add link to the OSF Slack
We are also present on Slack so advertise that.

Change-Id: I7d9887e524e47e6f42a5013e9f696881ef54a631
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-06-01 06:05:08 +00:00
Patrick Georgi a539817b1d Documentation/community: Add Discord to forums
Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-06-01 06:04:57 +00:00
Patrick Georgi 71099258cc Documentation: Fix up toctree
Some files weren't properly hooked up, making Sphinx complain.

Change-Id: If959fa63d4ddbc3916c49c5ad6602e76b12a7e60
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55020
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28 17:58:06 +00:00
Patrick Georgi 5a45c41782 Documentation: Fix named link
The syntax requires two bracketed fields.

Change-Id: I98ebe714e57f50017755eed7888f0dd2637a3066
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-28 17:58:01 +00:00
Patrick Georgi 34d5f9130e Documentation: Update real time chat options
Change-Id: I3035266c5e035b954c0d709bd2c09069128c3340
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55010
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28 11:44:34 +00:00
Angel Pons 9bc780fc9f option: Allow mainboards to implement the API
Some mainboards need a mainboard-specific mechanism to access option
values. Allow mainboards to implement the option API. Also, add some
documentation about the current option API, and describe when should
one reimplement the option API in mainboard code: only when the code
is mainboard-specific to comply with externally-imposed constraints.

Change-Id: Idccdb9a008b1ebb89821961659f27b1c0b17d29c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28 11:37:25 +00:00
Angel Pons 76619b01c8 Doc/releases: Mention that Asus H61 boards got squashed
Not physically squashed, the coreboot code got turned into a variant
setup with override devicetrees to drop redundant boilerplate.

Change-Id: I7ae5530d2603d6d108ef3829004de7e1cad130f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-20 21:11:14 +00:00
Paul Fagerburg de6cbac3c4 tests: improve code coverage support
Fix the exclusion path for lcov; it should exclude the directory
with source code, not object files.

Use the COV environment variable to
* control whether we build for coverage or not
* select the output directory

Add a separate target for generating the report, so we can get a
report for all of the tests together or just a single test.

Add documentation.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I2bd2bfdedfab291aabeaa968c10b17e9b61c9c0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-05-19 19:56:02 +00:00
Patrick Georgi 69f0df2c54 Documentation/gerrit: Describe core developer responsibilities
Change-Id: I8885e9fb401838229ead72b97394f3e2343aabed
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-17 22:20:44 +00:00
Paul Menzel 1e66479e93 Documentation/distributions: List System76
Copy the text from the [Web site](https://coreboot.org/users.html).

Change-Id: I805f558514eb50580b5bd79bd4f964e66a15158d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-16 21:56:15 +00:00
Paul Menzel 1b242b6618 Documentation/distributions: Order vendor list lexicographically
Change-Id: Id1f27d68124de745ff0eaad669ee86ce0b57ec09
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-05-14 10:16:48 +00:00
Paul Menzel 6415d9bffc Documentation/distributions: Separate all vendors by exactly one blank line
Change-Id: Ib1718dfa174e2a4e9c2c4b5564e196e8483a8f3c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-14 10:16:45 +00:00
Paul Menzel 6cb9188683 Documentation/distributions: Separate parenthesis by dashes
Change-Id: I5d6095c6d8423e3a67f027f23d4c00dcb34a50cb
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-14 10:16:39 +00:00
Matt DeVillier d3b49b4cda payloads/Tianocore: Update default build target, simplify build options
Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
option since it applied only to CorebootPayloadPkg. Clean up the Makefile now
that we're only building from a single Tianocore package/target.

Test: build/boot qemu Q35 target with both UefiPayload and Upstream options.

Change-Id: If545fbd0c30be6dcc6ff43107b80980fa23a527e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54019
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13 08:30:57 +00:00
Angel Pons 918e5352b7 Doc/nb/intel/sandybridge: Fix up some typos and cosmetics
Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-12 08:01:00 +00:00
Patrick Georgi 5d24231427 Documentation/releases: Add more details about release notes
There are some steps when updating the release notes that are easily
missed (see: I missed them for 4.14), so document them.

Change-Id: Icdb69eb74f8dd3a7189eb8803b0259c4e6a31f96
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12 07:41:03 +00:00
Patrick Georgi 6aa3238dc1 Documentation/releases: Add 4.15 release notes template
Change-Id: I52bd1ee6b297ba08e335f5c65941b09f14689a00
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12 07:40:34 +00:00
Patrick Georgi 970ebd67a5 Documentation/releases: Update checklist
Since we want commits to go through 24 hours of review, move the
vboot list update a week earlier. Also point more directly at the
right script to execute.

Change-Id: I49e6dfe22894402d5a0526588f8a04595ac88862
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12 07:40:20 +00:00
Patrick Georgi 67a5b4573c Documentation: Update vboot support list
Created by util/vboot_list/vboot_list.sh

Change-Id: I49536c26540c0fd1940a32f588fa49afb55b108a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12 07:40:14 +00:00
Michael Niewöhner 2765275467 docs: add recommendation for gpios regarding soft straps
Soft straps, that can be configured by the vendor in the Intel Flash
Image Tool (FIT), can influence some pads' default state. It is possible
to select either a native function or GPIO mode for some pads on
non-server SoCs, while on server SoCs most pads can be controlled.

Thus, add a recommendation to always configure all pads for a board to
guarantee integrity between different board or vendor firmware revisions
where the soft straps might have been changed.

Change-Id: I33063a3f6a1c9cd5267d85f7da84deb554489a26
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-11 17:28:07 +00:00
Michael Niewöhner 6d2fbba0ed docs: correct and rewrite documentation regarding n/c / unused pads
Intel PDGs starting from Skylake / Sunrise Point state that, different
from the general recommendation in digital electronics, unconnected
GPIOs defaulting to GPIO mode do explicitly not require termination.

The reason for this is, that these GPIOs have the `GPIORXDIS` bit set,
which effectively disconnects the pad from the internal logic by
disabling the input buffer.

This bit - besides `GPIOTXDIS` - can also be set explicitly by using
the gpio macro `PAD_NC(pad, NONE)`.

In some cases, a pull resistor may be required due to bad board design
or when a vendor sets the RX/TX disable bits together with a pull
resistor and schematics are not available to check if the pad is really
unconnected or just unused. In this case the pull resistor should be
kept.

Pads defaulting to native functions usually don't need special handling.
However, when pads requiring external pull-ups are missing these due to
bad board design, they should be configured with `PAD_NC` to disconnect
them internally.

Rewrite the documentation to reflect these new findings.

Also clarify the comment in soc/intel gpio code accordingly.

Change-Id: Id01b197ebe8f2b8bb4ecf3d119ec2298b26d9be0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52139
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-11 13:14:53 +00:00
Patrick Georgi a0aee78c82 Documentation/releases: Fill in coreboot 4.14 release notes
Change-Id: I79530c91424112247e485a5a41debc666e0072d4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10 20:32:07 +00:00
Jonathan Zhang 206dfbf173 doc/relnotes/4.14: add Intel Xeon-SP support status change
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52735
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10 20:31:19 +00:00
Kyösti Mälkki 8618cf1edc doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes
Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-10 19:56:58 +00:00
Patrick Georgi 9b330fafeb Documentation/gerrit: Document our Gerrit user roles and procedures
Document the roles we have on review.coreboot.org, the expectations
associated with them, and how to become part of any of these groups.

Change-Id: Ib31083f5a07bd89efd13ecd6aaf34a69d438d59d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52265
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-09 16:23:43 +00:00
Felix Held 07eb01bc02 doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53924
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08 19:35:40 +00:00
Tony Huang 1282b007be drivers/i2c/generic: Set S0W to D3hot for wake device
If device is supported as a wake source, _S0W should be set to D3hot.
This ensures that the device is put into D3hot by the OSPM.

Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM.

The devices we are currently looking at for touchscreen/touchpad
do not really support auxiliary power and so do not support wake from D3cold.

BUG=b:186070097
TEST=build and check device wake state _S0W set to 3 in ssdt table.

Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-05 01:16:29 +00:00
Tim Wawrzynczak 13e240c602 util/sconfig: Add support for discontiguous FW_CONFIG fields
Sooner or later, some board was going to need extra FW_CONFIG bits for
a field that was already in production, so this patch adds support for
adding extra (unused) bits to a field.

The extra are appended via a syntax like:
`field FIELD_NAME START0 END0 | START1 END1 | START2 END2 ...`
and the suffixed bits are all treated as if they are contiguous when
defining option values.

BUG=b:185190978
TEST=Modified volteer fw_config to the following:
field AUDIO 8 10 | 29 29 | 31 31
        option NONE 0
	option MAX98357_ALC5682I_I2S 1
        option MAX98373_ALC5682I_I2S 2
	option MAX98373_ALC5682_SNDW 3
        option MAX98373_ALC5682I_I2S_UP4 4
        option MAX98360_ALC5682I_I2S 5
        option RT1011_ALC5682I_I2S 6
        option AUDIO_FOO 7
	option AUDIO_BAR 8
        option AUDIO_QUUX 9
        option AUDIO_BLAH1 10
        option AUDIO_BLAH2 15
        option AUDIO_BLAH3 16
        option AUDIO_BLAH4 31
end

which yielded (in static_fw_config.h):
 FW_CONFIG_FIELD_AUDIO_MASK 0xa0000700
 FW_CONFIG_FIELD_AUDIO_OPTION_NONE_VALUE 0x0
 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98357_ALC5682I_I2S_VALUE 0x100
 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_VALUE 0x200
 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682_SNDW_VALUE 0x300
 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_UP4_VALUE 0x400
 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98360_ALC5682I_I2S_VALUE 0x500
 FW_CONFIG_FIELD_AUDIO_OPTION_RT1011_ALC5682I_I2S_VALUE 0x600
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE 0x700
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE 0x20000000
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_QUUX_VALUE 0x20000100
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH1_VALUE 0x20000200
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH2_VALUE 0x20000700
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH3_VALUE 0x80000000
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH4_VALUE 0xa0000700

Change-Id: I5ed76706347ee9642198efc77139abdc3af1b8a6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52747
Reviewed-by: Duncan Laurie <duncan@iceblink.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03 07:40:57 +00:00
Michael Niewöhner f3e82459a8 docs/mb/supermicro/x11ssm-f: rework flashing section
The board can be flashed without adding a diode by just leaving VCC
unconnected. Rework the flashing section to describes that.

Change-Id: I37d55ffdbcfba4f3a1113a82f16ec8766bbb6e6c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-29 05:23:38 +00:00
Stefan Ott dc77bc0546 mb/asus/p5q: Document working fan control and FireWire port
Fan control and FireWire work fine on my board.

Signed-off-by: Stefan Ott <stefan@ott.net>
Change-Id: Idc69e902370c4094daef93e843abc6ae564625f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-28 09:56:06 +00:00
Tim Crawford 109c4d05d6 mb/system76/oryp6: Add System76 Oryx Pro 6
https://tech-docs.system76.com/models/oryp6/README.html

Tested with TianoCore (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe
- M.2 SATA
- MicroSD card slot
- All USB ports
- Integrated graphics using Intel GOP driver
- Webcam
- Ethernet
- Internal microphone
- Combined headphone + mic 3.5mm jack
- Combined microphone + S/PDIF 3.5mm jack
- Booting to Ubuntu Linux 20.10 and Windows 10
- Flashing with flashrom

Not working:

- S3 suspend/resume: System hangs on wake from S3
- Discrete/Hybrid graphics: Requires a new driver
- Internal speakers: Enabled in separate patch

Not tested:

- Thunderbolt functionality
- S/PDIF output

Change-Id: If017d65ca6cb36fe1f631d4dadd050a1547c93fa
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47768
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 20:45:50 +00:00
Furquan Shaikh 66ab5eb521 [RFC] Address the leftover TODO in soc/intel/cannonlake
Change-Id: I4c989de4d2af3e810fb0e4803d0fa2396917d93e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50829
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16 17:42:12 +00:00
Patrick Georgi 69cb494749 Documentation: List the leadership meeting as one of our forums
Change-Id: I00822cc631c5451862bd94683ff45289ecc75679
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
2021-04-15 19:11:01 +00:00
Ravi Kumar Bokka 0c9eb31533 sc7280: Provide initial SoC support
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board

Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15 19:07:26 +00:00
Jonathan Zhang e73bae7b0a Documentation/mb/ocp: Update Delta Lake documentation
Update OCP Delta Lake documentation following OSF (Open System Firmware)
solution reaching DVT exit parity. This alternative host firmware
solution uses FSP/coreboot/Linuxboot stack.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ifd6ab251cd7806cf8cd3f984ad88c091f85035cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-15 07:37:46 +00:00
Piotr Szymaniak 5b5b8afdf1 Docs/mb/lenovo/t420: List working, tested and non-working features
Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl>
Change-Id: I6fb4a8da44125b4280d37d0cf7c372f8024fb2d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-06 06:47:29 +00:00
Michael Niewöhner 0887fc4dbc docs/mb/supermicro: add SUM tool for flashing with disabled ME
Change-Id: I08543c0908a6cb4ef9fb46d0eb3a7aa481fb95d9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49887
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-03 20:25:44 +00:00
Matt DeVillier fcb68f31b6 mb/purism/librem_14: Move/fix touchpad interrupt GPIO
On production boards, the touchpad interrupt line was moved
from GPP_B20 to GPP_B3. Fix the GPIO pad config and devicetree entry,
and update documentation to remove touchpad config issue.

Change-Id: Iaefeba8f78c567b67e7a416c27299bff574c23ab
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51797
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:05:57 +00:00
Matt DeVillier 385667f679 documentation: Add documentation for Purism Librem 14
Change-Id: Ic68a3d17534f78dae8c432253982e8d10a6427f0
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28 16:05:51 +00:00
Julius Werner 4dd857723b Documentation/coding_style: Issues not mentioned and cleanup patches
This patch adds a bit of a "preamble" to the coding style to provide
guideance on how it should be applied and how style questions that
aren't mentioned should be handled.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I88efd5f1006bd1fd82cea14ea65422d9958dc197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-26 05:09:40 +00:00
Tim Crawford 427487b173 mb/system76/gaze15: Add System76 Gazelle 15
Tested with TianoCore payload (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux 20.10 and Windows 10

Not working:

- Discrete/Hybrid graphics

This requires a new driver to work correctly, which will be added and
enabled later.

Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24 07:53:40 +00:00
Julius Werner 698b05fdd5 Documentation/coding_style: Add more details on include-ordering
This patch is trying to address some of the concerns raised in CB:50247
after the patch had landed. The preference for alphabetized headers was
just supposed to discourage leaving headers completely unordered, and
wasn't intended to disallow other intentional include orderings such as
grouping local includes after system ones or specific ordering
constraints that exist for technical reasons. This patch adds a few more
sentences to try to clarify that.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6825f4a57613fabb88a00ae46679b4774ef7110b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-22 11:30:13 +00:00
Jakub Czapiga 61fcb7e965 acpi/acpigen.h: Add more intuitive AML package closing functions
Until now every AML package had to be closed using acpigen_pop_len().
This commit introduces set of package closing functions corresponding
with their opening function names. For example acpigen_write_if()
opens if-statement package, acpigen_write_if_end() closes it.
Now acpigen_write_else() closes previously opened acpigen_write_if(),
so acpigen_pop_len() is not required before it.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22 11:21:55 +00:00
Kevin Chiu 4490689d88 google/trogdor: Add new variant Marzipan
This patch adds a new variant called Marzipan that is identical to Lazor
for now.

BUG=b:182181519,b:182018606
BRANCH=master
TEST=make

Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20 01:31:06 +00:00
Angel Pons da12ca98c9 doc/mb/lenovo/montevina: Update link within page
Commit c4aa24fc12 (doc/mb/lenovo/montevina: Clarify use of bincfg)
renamed a section, and the link referencing it by its old title no
longer works. Update the link, and remove the `a completely new one`
part from it as well, for consistency with the aforementioned commit.

Change-Id: I22e8b3237dafb3397bc901804a57e905f806839d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-19 12:46:06 +00:00
Patrick Georgi ce9b26cdd5 Documentation/releases: Add note about CBFS stage format change
Change-Id: I2e4f1d1551141c6225e762631e52d71357112425
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-18 08:21:02 +00:00
Patrick Georgi a763e8f92b Documentation: Describe the site-local hook in our config/build system
Change-Id: Ia682b784540fa82e1f216f76d87d59a4f0b94486
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51546
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17 23:07:07 +00:00
Furquan Shaikh 82dcd5b9ba Documentation: Add deprecation notice for SAR support in VPD
This change updates the release notes for coreboot-4.14 to add
deprecation notice for SAR support in VPD for Chrome OS platforms.

BUG=b:173465272

Change-Id: If6d511a22a3a2a31671dac91e57e801134d4ecf8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51486
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17 07:56:39 +00:00
Alexander Couzens 1295fa218f mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-F
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same
PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in
difference to the X11SSH-F which only has 2 NICs. The two additional
NICs aren't populated on the X11SSH-F. Enable the PCIe root ports
connected to the two additional Intel NICs.

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-15 09:45:23 +00:00
Nico Huber 3b14a5f92a doc/mb/lenovo/montevina: Fix constants for 16MiB flash
The current values are actually for 32MiB and result in a brick if used
with a 16MiB chip because of the invalid bios region.

Change-Id: I08337394ce0d6e31e5c03cda2bfb3b9f0282f2c3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51322
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14 16:35:37 +00:00
Dmitry Torokhov 39c1b4f951 Documentation/acpi: switch example from edge to level interrupts
Configuring touch controllers to use edge-triggered interrupts is not
recommended as it is very easy to lose an edge when kernel drivers
disable the interrupt for one reason or another, and recovering from
this condition requires workarounds in the kernel.

Unfortunately the example setting up a touchpad used edge-triggered
interrupts, and this set up has been propagating through the boards.
Let's switch the example to use level interrupts instead.

Change-Id: I4dc8b91ed070ce117553b00a087ad709aeaf16af
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-11 22:38:52 +00:00
Nico Huber c4aa24fc12 doc/mb/lenovo/montevina: Clarify use of bincfg
`bincfg` is not creating anything new, it just converts
from text to binary.

Change-Id: I14e67ee8bc449d171a951f6edeaa9f9d0c04dbe1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51319
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-07 13:59:23 +00:00
xuxinxiong 9a446bdf07 mb/google/trogdor: Add new configs homestar
New boards introduced to trogodor family.

BUG=b:180668002
BRANCH=none
TEST=make

Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: If0f9b6c89198a882acae7191d08b166eb8c1dd71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-26 01:37:40 +00:00
Johnny Lin aed1952f05 doc/mb/ocp: Update DeltaLake for VPD variables used in LinuxBoot
u-root commits:
bmc_bootorder_override
https://github.com/u-root/u-root/pull/1902
systemboot_log_level:
https://github.com/u-root/u-root/pull/1922

Change-Id: I3da7291188ee06c50008aa3fc7142210215044d4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-24 11:27:43 +00:00
Angel Pons 83e6c15b0e Doc/releases/checklist.md: Clarify tag push command
Change-Id: I0a6d1ed014c6454c4bde390283351c19fe097201
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47813
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 17:25:59 +00:00
Alexey Vazhnov 63b87e985c Document Gigabyte GA-G41M-ES2L
To replace wiki page https://www.coreboot.org/Board:gigabyte/ga-g41m-es2l

+ configs/config.gigabyte_ga-g41m-es2l
+ lshw output examples
+ memory modules compatibility

Tested in Devuan 4 Chimaera.
Tested from exact steps from this documentation.

Change-Id: Ib45cfea15b43d7399e9d209f7ba7c6b24fe860dd
Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2021-02-22 07:21:30 +00:00
Alexey Vazhnov f595984043 Documentation: move `coding_style.md` inside contributing/
Keep less files in the root directory.

Change-Id: I9eebd0b0826181340ead41af5284362d1cca09d7
Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-22 07:20:59 +00:00
Martin Roth 5c7341331d treewide: Remove trailing whitespace
Remove trailing whitespace in files that aren't typically checked.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I8dfffbdeaadfa694fef0404719643803df601065
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17 17:30:05 +00:00
Paul Menzel c4062c78a9 device: Add unit to Kconfig option name: `PRE_GRAPHICS_DELAY_MS`
It’s good practice to put the unit into the name.

Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-15 17:05:18 +00:00
Evgeny Zinoviev b08543a640 Doc/mb/lenovo/montevina_series: Use Makefile to generate IFD
util/bincfg's Makefile already has target that generates flash
descriptor. Use it instead.

Change-Id: I1756514e1ab7b64de23a98314d8a32e9258e648c
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 07:48:13 +00:00
Evgeny Zinoviev d2b3961fdc Documentation: Use correct KiB/MiB units instead of KB/MB
Fix a common mistake of using KB/MB where KiB/MiB is what actually is meant.

1 MB = (10^3)^2 = 1000000
1 MiB = (2^10)^2 = 1048576

Change-Id: I78327652b6c6526318071a9d4bafd7ec279ea614
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39685
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09 07:47:41 +00:00
Julius Werner ca935d1107 Documentation: Codify some guidelines for headers and chain-including
There has been some repeated discussion about how header includes should
be formatted, specifically on the topic of chain-including. The coding
style currently doesn't say anything about the topic but clearly people
have some basic assumptions. This patch tries to codify some common
ground rules that are supposed to reflect the existing practice.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06 09:08:04 +00:00
Martin Roth 064b250fac Update util.md documentation
This is the new output of the util_readme.sh script.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia46924474f75692192ef4b52aab714f5071f9534
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48966
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 20:17:11 +00:00
Tim Crawford fdc8fd3602 mb/system76/oryp5: Add System76 Oryx Pro 5
Tested with TianoCore payload (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics
- Internal microphone
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux and Windows

Not working:

- Discrete/Hybrid graphics
- Internal speakers

These two require new drivers to work correctly, which will be added and
enabled later.

Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28 09:15:00 +00:00
Martin Roth 2cee2ff256 Documentation: Add documentation on jenkins builders
Put this in a new directory called 'infrastructure' and make a link
and an index.md file for the directory.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25 08:56:27 +00:00
Angel Pons 0ec903a73b Doc/mb/lenovo/Sandy_Bridge_series.md: Clarify installation
Unlike Ivy Bridge series, there isn't a method to flash coreboot
internally when running vendor firmware (yet). Until someone finds a way
to bypass flash protections, the first flash has to be done externally.

Change-Id: Idaff264f2b7277516d69d1323f1a0c885b28c3db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24 23:21:23 +00:00
Angel Pons 76943a3443 Doc/mb/lenovo: Correct typo
Change-Id: If31c59f21c5533d8b5b015c9e60edd6e4e7072e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49847
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 23:21:17 +00:00
Michael Niewöhner d509ee55b6 soc/intel/apl: drop LPC pad configuration code
Drop LPC pad configuration code since all boards now do pad
configuration on their own. The comment about LPC_CLKRUNB when using
eSPI is moved to `Documentation/getting_started/gpio.md`.

Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23 09:23:23 +00:00
Patrick Rudolph 6279cabb5b Documentation: Fix toctree and remove dead links
Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-12 13:36:36 +00:00
Patrick Rudolph fc1d50a365 Documentation: Add known bugs of x86_64 code on real hardware
The bugs happen on real hardware or in qemu with KVM enabled.
The very same code runs on some real devices and it runs in qemu
with KVM disabled.

The bugs are so strange that no root cause could be found yet.

Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-12 13:36:30 +00:00
Sam Lewis 1c18f8679f Documentation: Add Beaglebone Black documentation
Change-Id: If1a9808d1f20ee61048182d416f25e9a81c631af
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-24 08:30:28 +00:00
Angel Pons 9223b71a4c Doc/mb/lenovo: Explain simpler GM45 flash method first
Do not mislead newcomers into thinking the GM45 series laptops are hard
to flash. Describe the simple coreboot flashing procedure first, then
explain how to remove the ME firmware and use a custom flash layout.

Also, reword a sentence on the simple flashing procedure for clarity.

Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2020-12-14 08:17:33 +00:00
Angel Pons d0fd7b0693 Doc/mainboard: Sort Lenovo laptop generation groups
GM45 is older than Arrandale, so swap their order.

Change-Id: I5b94d940c0378dd561535257d3352700fd482527
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2020-12-14 08:17:27 +00:00
Furquan Shaikh 339269d587 Docs/cbfstool: Add details about memory mapped window handling
This change adds details memory mapped window handling in cbfstool
required for x86 platforms. It also captures the details about the
newly added support for multiple decode windows.

BUG=b:171534504

Change-Id: Icf970f951e56d717e6a4f8845fc73f10d5a21dd0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-11 01:11:16 +00:00
Jonathan Zhang 36854a831e Documentation/mainboard/ocp: Update DeltaLake
DeltaLake Open System Firmware stack (FSP/coreboot/Linuxboot) has
reached EVT exit parity. Update the documentation accordingly.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-05 09:47:00 +00:00
Michael Niewöhner 43dd2e458f docs/mb/supermicro/x11-lga-series: Update documentation
- Drop issue about non-working TianoCore with Aspeed NGI. see CB:35726
- Add missing reference to X11SSH-F
- Drop TODO reference; there are no TODOs left

Change-Id: I5becfa9ea01a0d9d651c6b51b30ebfcedb6412a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48101
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-27 20:49:16 +00:00
Michael Niewöhner 4c56d79ba6 {docs/,}mb/supermicro/x11ssh-tf: drop TODO section
Drop the TODO comment, since there is no TODO left. Also drop the now
obsolete TODO section from the board documentation.

Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-27 20:49:04 +00:00
Michael Niewöhner ce04a42db9 docs/mb/supermicro/x11ssm-f: Update board documentation
- Drop vanished issue on PCIe warning
- Drop TODO section, since the TODOs are done
- Document the jumper J6, that was not documented by the vendor. Its
  function has been determined by dissecting a dead board.
- The flash is not socketed anymore. Drop that note and compress the
  whole paragraph. Also add a note about flashing via the BMC web
  interface.

Change-Id: I2b5a08a6b6d80717621d6a30f31829fe4b84891a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-27 20:48:55 +00:00
Paul Menzel 9226fe9aee Documentation: Mention newer Intel μ-code updates in 4.13 release notes
Start a new section *Notes* for these kind of information.

Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47762
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:21:29 +00:00
Angel Pons c930c87998 Doc/releases/checklist.md: Fix up URLs
Use angle brackets so that they appear as links, and update a link to a
Gerrit change to use the current format.

Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47812
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:19:58 +00:00
Angel Pons 5ea7bb74bd Doc/releases/checklist.md: Add reminder to unpack relnotes
Explicitly add this easy-to-forget step. Also add a missing period.

Change-Id: Iaf13155fcc8a70f3565fb2404cef886524fa5161
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47811
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:19:48 +00:00
Maxim Polyakov 0fcd37172f mb/kontron: Add Kontron mAL10 COMe module support
This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.

Working:
  - UART console and I2C on Kontron kempld;
  - USB2/3
  - Ethernet controller
  - eMMC
  - SATA
  - PCIe ports
  - IGD/DP
  - SMBus
  - HWM

Not tested:
  - IGD/LVDS
  - SDIO

TODO:
  - HDA (codec IDT 92HD73C1X5, currently disabled)

Tested payloads:
  - SeaBIOS
  - Tianocore, UEFIPayload - without video, EFI-shell in console only

Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)

Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22 22:18:22 +00:00
Angel Pons 5c186c6777 Documentation/releases: Update for 4.13
Fill in some blanks for 4.13, mark it done, add template for 4.14.
Also update the list of vboot supported boards.

Change-Id: Ie593efe515136a3b06620db6f0dbe3da00df7e9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 12:01:35 +00:00
Felix Singer d959a20114 mb/clevo/kbl-u: Add Clevo N130WU/N131WU
Working:
- TianoCore
- NVMe, SATA3
- USB2, USB3
- Thunderbolt
- Graphics (GOP and libgfxinit)
- Sound
- Webcam
- WLAN, LAN, Bluetooth, LTE
- Keyboard, touchpad
- TPM
- flashrom support; reading / flashing from Linux
- ACPI S3

WIP:
- Documentation

Not working:
- EC ACPI (e.g. Fn keys, battery and power information)

Boots Arch Linux (Linux 5.8.12) successfully.

Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-20 11:57:11 +00:00
Angel Pons 27f606b721 doc/relnotes/4.13: Remove duplicated `CPU`
Change-Id: Ib423a0d4341560301138e06b00a704c2baae4867
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47767
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 17:13:22 +00:00
Nico Huber 2421b88381 doc/relnotes/4.13: Fix random spelling mistakes
Change-Id: I7486124fbe43f15bfbbf0875a58935133639b35f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47670
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 16:32:13 +00:00
Furquan Shaikh a8e7b45816 Doc/relnotes/4.13: Add details about resource allocator v4
This change adds details about the new resource allocator v4 in
coreboot to the release notes for 4.13.

Change-Id: I7071bdf0faffda61fc5941886c963181939c07e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-19 16:23:46 +00:00
Nico Huber 900c3a32a3 doc/relnotes/4.13: Add changes to log-level configurability
Change-Id: Ia7ef57d20ea5099f344ccbf58d76597cb0e82c85
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 16:22:23 +00:00
Felix Singer 1268d4081e doc/relnotes/4.13: Add note about PCI bus mastering Kconfig options
Change-Id: I66a636f554d18e08a209a7cfd6a59cf13a88f2e1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47409
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 13:23:30 +00:00
Angel Pons 9fe0615ecc Doc/relnotes/4.13: Add several relevant changes
While some of these have little impact, they are worth mentioning here.

Change-Id: Idbf629ae77b8918ff1d93edb7b6c4669bbbe17df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-13 16:11:48 +00:00
Julius Werner 9c50462fd7 Delete mainboard/google/cheza
Work on this mainboard was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-12 01:43:09 +00:00
Harshit Sharma 678e401eb8 Documentation/releases: Add ASan to 4.13 relnotes
Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45118
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-11 10:28:05 +00:00
Iru Cai 85d0e7611a mb/hp: Add HP EliteBook Folio 9480m
The code is based on autoport, with necessary modifications.

This laptop uses SMSC MEC1322 embedded controller, but the EC
interface is the same as the EliteBook laptops of previous generations
that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need
EC firmware inserted into CBFS. We also need to leave the end of the
OEM flash content untouched, so the default ROM size is set to 12MiB
instead of 16MiB, and we need to modify the IFD when flashing.

Thanks to persmule for providing the laptop and pointing out how to
program the system flash chip of it.

Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-10 06:16:05 +00:00
Iru Cai 136380fcac Documentation: Introduce HP Sure Start and the method to bypass it
Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45577
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 10:38:32 +00:00
Matt DeVillier 12d515dcc5 mb/purism/librem_cnl: Add new variant 'Librem Mini v2'
Add Kconfig entries, and update existing documentation to
accomodate both v1/v2 versions of the board.

Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46984
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:48:23 +00:00
Matt DeVillier 184c794086 docs/librem_mini: update CPU, known issues section
Both 8565U and 8665U CPUs are used in the Librem Mini.

SATA issue updated based on addition of HSIO PHY tuning params
and resulting changes.

Change-Id: I33a093ccfea077402e1b3651f9ca5d6d8a2818f8
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-31 21:46:06 +00:00
Tim Wawrzynczak 24b4af668b fw_config: Convert fw_config to a 64-bit field
We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.

BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 15:24:52 +00:00
Patrick Georgi 6065f616eb .gitignore: Split into subdirectory files
There's no need for the global list of files to ignore, so use git's
ability to work with more local configuration.

Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 07:05:27 +00:00
Patrick Rudolph bc744f5893 drivers/smmstore: Implement SMMSTORE version 2
SMMSTORE version 2 is a complete redesign of the current driver. It is
not backwards-compatible with version 1, and only one version can be
used at a time.

Key features:
* Uses a fixed communication buffer instead of writing to arbitrary
  memory addresses provided by untrusted ring0 code.
* Gives the caller full control over the used data format.
* Splits the store into smaller chunks to allow fault tolerant updates.
* Doesn't provide feedback about the actual read/written bytes, just
  returns error or success in registers.
* Returns an error if the requested operation would overflow the
  communication buffer.

Separate the SMMSTORE into 64 KiB blocks that can individually be
read/written/erased. To be used by payloads that implement a
FaultTolerant Variable store like TianoCore.

The implementation has been tested against EDK2 master.

An example EDK2 implementation can be found here:
eb1127744a

Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-22 12:29:47 +00:00
Bill XIE 14ee0f94f3 mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another X11 series board, the X11SSH-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-20 09:00:18 +00:00
Paul Menzel b9a5152cfa Documentation: Fix spelling of *assumptions*
Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 07:06:59 +00:00
Duncan Laurie 2cc126be2c drivers/intel/usb4: Add driver for USB4 retimer device
The USB4 retimer device needs to declare a _DSM with specific functions
that allow for GPIO control to turn off the power when an external
device is not connected.  This driver allows the mainboard to provide
the GPIO that is connected to the power control.

BUG=b:156957424

Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 06:51:40 +00:00
Iru Cai 871f62c376 lenovo/t440p: Add HDA verbs from the OEM firmware
To get the HDA verbs from the OEM firmware, open the firmware with
UEFITool, search for the existing HDA verbs, extract the UEFI module
and look for the verbs. Copy the consecutive 4 dword sets that look
like HDA verbs.

It is tested to make audio output from both the speaker and headphone
work.

Change-Id: Ie359fdf6785b1c0be8dc201cd76176c0a7fe7942
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30 10:13:48 +00:00
Jonathan Zhang 339fa7389b doc/mb/ocp: update deltalake server documentation
Upon completion of 2nd build/test/release cycle of Deltalake server
alternative firmware engineering, update the document.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I1806526bd477ed407bb7fd36c7fe4ce0e57b72f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28 09:37:57 +00:00
Christian Walter 90b0d85e73 Documentation/mainboard: Add Missing OCP Delta Lake Link
Change-Id: I379d6a7b72a0398c34ea8eeda09ccd663fc372ce
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:32:50 +00:00
Elyes HAOUAS 3f56b87c51 Documentation/getting_started/kconfig.md: Add a note about Kconfig defaults
When the declaration is done after the default, menuconfig will see that
symbol defined at the first place where kconfig tool will find it.
For example, if we run menuconfig and search for 'MAINBOARD_VENDOR', we
will see it defined at ""src/mainboard/51nb/Kconfig" which is odd.

Change-Id: I215a1817e60e6deb6931679f139d110ba762d3c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-25 08:41:45 +00:00
Harshit Sharma d8a722cb61 Documentation: Add ASan documentation
Change-Id: I710ea495798597189941620c7e48fd5aa7476781
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-21 07:45:37 +00:00
Bob Moragues c06c0ce559 strongbad / coachz : Add Initial Support
BUG=b:162409909
BUG=b:164196066
BRANCH=NONE
TEST=Verify build of strongbad target

Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 22:32:34 +00:00
Rob Barnes b2545cc3c6 soc/amd/picasso: Move APCB generation out of picasso
Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.

BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
     Build and boot ezkinil

Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 20:26:03 +00:00
Patrick Georgi 4ad85ed156 Documentation: Discuss how we use language
Change-Id: I44fa30af538c78760821401c8d3c52029d95b72b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-31 20:23:22 +00:00
Patrick Rudolph e828663392 Documentation: Update release notes for x86_64
Change-Id: I7d8d39bde3b3364ff6ce93030aa2bab34598acd8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-31 17:08:58 +00:00
Angel Pons 85a4463976 Doc/soc/intel: Add info about microcode updates
Document a general overview of when and how microcode should be updated.
Also explain what microcode updates are, and why they are required.

Change-Id: I6dbe25122fa45a416ed64180ef1bfb11afe676ba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44400
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-26 07:36:12 +00:00
Matt DeVillier dff9994b96 docs/purism/librem_mini: Fixup CPU model, markup links
Change-Id: I26c0936c912490fc0ba28ee53139e3a1f3a00911
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-21 18:17:17 +00:00
Patrick Rudolph 57907fcebf mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
* Enable optional x86_64 romstage, postcar and ramstage
* Add Kconfig for x86_64 compilation
* Add documentation for x86 qemu mainboards
* Increase CAR stack as x86_64 uses more than 0x4000 bytes

Working:
* Boots to Linux
* Boots to SeaBIOS
* Drops to protected mode at end of ramstage
* Enumerates PCI devices
* Relocateable ramstage
* SMM

Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29667
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19 10:50:49 +00:00
Patrick Rudolph e563815e05 arch/x86/boot: Jump to payload in protected mode
*   On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode.
*   Add a helper function to jump to arbitrary code in protected mode,
    similar to the real mode call handler.
*   Doesn't affect existing x86_32 code.
*   Add a macro to cast pointer to uint32_t that dies if it would overflow
    on conversion

Tested on QEMU Q35 using SeaBIOS as payload.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-19 09:06:43 +00:00
Sam Lewis cb287987a1 arch/arm: Enable FIT payloads
Implements fit_payload_arch for the arm (aarch32) architecture, so that
FIT images can be used. The implementation is very similar to the
existing implementations for arm64 and riscv, and has mostly been
lifted from these other ports.

TEST: Booted Beaglebone Black (in progress port, to be submitted soon!)
with a FIT image containing a 5.4 kernel, dtb and initramfs.

Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-19 07:16:59 +00:00
Matt DeVillier 87093758c5 documentation: Add documentation for Purism Librem Mini
Change-Id: Ie5699942f48d2d5b1417f447a9a36b98e4b18156
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42882
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18 16:01:05 +00:00
Iru Cai 1bda1c356a mainboard: Add HP EliteBook 2560p
Most of the code is generated by autoport. The laptop works well under
coreboot with SeaBIOS 1.13.0 payload, running Arch Linux with kernel
5.4.39 and 5.6.11.

Change-Id: I126916e201fb8e4b9067f2dececebfb5bae6df73
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17 06:25:19 +00:00
Rocky Phagura afb7a81478 cpu/x86/smm: Introduce SMM module loader version 2
Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores).
Current coreboot SMM is unable to handle more than ~32 CPU threads.
This patch introduces a version 2 of the SMM module loader which
addresses this problem. Having two versions of the SMM module loader
prevents any issues to current projects. Future Xeon-SP products will
be using this version of the SMM loader.  Subsequent patches will
enable board specific functionality for Xeon-SP.

The reason for moving to version 2 is the state save area begins to
encroach upon the SMI handling code when more than 32 CPU threads are
in the system. This can cause system hangs, reboots, etc. The second
change is related to staggered entry points with simple near jumps. In
the current loader, near jumps will not work because the CPU is jumping
within the same code segment. In version 2, "far" address jumps are
necessary therefore protected mode must be enabled first. The SMM
layout and how the CPUs are staggered are documented in the code.

By making the modifications above, this allows the smm module loader to
expand easily as more CPU threads are added.

TEST=build for Tiogapass platform under OCP mainboard. Enable the
following in Kconfig.
        select CPU_INTEL_COMMON_SMM
        select SOC_INTEL_COMMON_BLOCK_SMM
        select SMM_TSEG
        select HAVE_SMI_HANDLER
        select ACPI_INTEL_HARDWARE_SLEEP_VALUES

Debug console will show all 36 cores relocated. Further tested by
generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all
cores entering and exiting SMM properly. In addition, booted to Linux
5.4 kernel and observed no issues during mp init.

Change-Id: I00a23a5f2a46110536c344254868390dbb71854c
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-15 02:16:32 +00:00
Patrick Rudolph 8daa12f7e0 arch/x86/postcar: Add x86_64 support
* Add support for loading GDT on x86_64.
* Add x86_64 assembly code to do the same as the x86_32 code.
* Separate x86_32 and x86_64 code.

Tested on qemu x86_32 and x86_64 using additional MTRRs.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30500
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-14 17:55:26 +00:00
Jonathan Zhang 6e36ee2544 doc/mb/ocp: update Delta Lake documentation
Update Delta Lake documentation following ww30 to ww33 build/test/release
cycle.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-14 09:07:32 +00:00
Balazs Vinarz ffa710b9dd mb/asus: Add Asus A88XM-E FM2+ with documentation
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- no optical SPDIF/IO

Successfully booted configurations:
-RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0
-CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland)
-OS:  Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019
-SeaBIOS: 1.12 and 1.13

Known problems:
- IRQ routing is done incorrect way - common problem of fam15h boards
- Windows 7 can't boot because of the incomplete ACPI implementation

Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13 17:34:04 +00:00
Patrick Georgi 20245aa622 Documentation: Fix sphinx configuration
Without the brackets, the string seems to be added as a list of
characters, and since there's no extension called 's', sphinx
bails out.

Change-Id: If0fc9c1a74f334b6154df3cb26836509de913567
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44114
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04 12:18:29 +00:00
Paul Menzel e1574e31f6 Doc/mb/facebook/monolith: Correct grammar by removing plural *s*
Change-Id: I2d14902f9d975e89cd2842f4c12eab8ca4018fbf
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44018
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:09:50 +00:00
Paul Menzel d3d316a28f Doc/mb/lenovo: Mark up file name as code/monospace
Change-Id: I397b1dc0c3faf65811889d4c5814d6dcca7fe6b4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43748
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:08:58 +00:00
Jonathan Zhang b84bd303ee doc/getting_started: update name of file generated by "make savedefconfig"
Update kconfig.md to reflect that defconfig (instead of mini-config)
file is generated by running "make savedefconfig".

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I4075e5b51e3c504eaad25e3abfc52ba593364ee9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-29 09:36:33 +00:00
Patrick Georgi 71a22e3cfc Documentation: Revise "24 hours wait period" rules
They're more or less the same but reworked for hopefully some more
clarity. There have been some best practices around documenting the
reason for expedited processing so let's make them official, too.

Change-Id: I620e48016a1ceda2ac43f26624ed21af01f6a0a5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43484
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 09:18:26 +00:00
Paul Menzel 229616419d Doc/mb/facebook/monolith: Use correct TianoCore commit hash
The commit hash is the same as the SeaBIOS one, and is indeed from the
SeaBIOS repository.

Change-Id: I820b9b748778050fc694c13b1e2b2fc80885b4f1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43749
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 19:24:05 +00:00
Rizwan Qureshi ec321094f6 soc/intel/common/basecode: Implement CSE update flow
The following changes are done in this patch:
 1. Get the CSE partition info containing version of CSE RW using
    GET_BOOT_PARTITION_INFO HECI command
 2. Get the me_rw.version from the currently selected RW slot.
 3. If the versions from the above 2 locations don't match start the update
    - If CSE's current boot partition is not RO, then
        * Set the CSE's next boot partition to RO using SET_BOOT_PARTITION
          HECI command.
        * Send global reset command to reset the system.
    - Enable HMRFPO (Host ME Region Flash Protection Override) operation
      mode using HMRFPO_ENABLE HECI command
    - Erase and Copy the CBFS CSE RW to CSE RW partition
    - Set the CSE's next boot partition to RW using
      SET_BOOT_PARTITION HECI command
    - Trigger global reset
    - The system should boot with the updated CSE RW partition.

TEST=Verified basic update flows on hatch and helios.
BUG=b:111330995

Change-Id: I12f6bba3324069d65edabaccd234006b0840e700
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:42:06 +00:00
Maxim Polyakov a76a64833b soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
This macro is not correct because the RX Level/Edge Configuration
(trig) and the GPIO Tx/Rx Buffer Disable (bufdis) fields in DW0
register do not affect on the pad in the native function mode.

This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":

CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG

Change-Id: Ic0416e3f67016c648f0886df73f585e8a08d4e92
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Michael Niewöhner
2020-07-26 21:33:08 +00:00
David Hendricks 4cdc698707 Doc/tutorial/part1.md: Show how to list toolchain targets
Change-Id: I276ea0a6b52b55b8772c76f48f7a0fb149af6e78
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43518
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 04:56:25 +00:00
Tim Wawrzynczak 0115ba8835 Documentation: Add documentation for drivers/intel/dptf chip driver
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8915ead08a89dcf95fd92983eca5f85b82916dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-18 16:05:43 +00:00
Patrick Georgi b8d0d089b3 Documentation: Remove mention of manual checkpatch.pl invocation
We typically call checkpatch.pl through make lint which properly adds
the option to tell checkpatch that our lines may be 96 columns long.

However there's one mention of calling checkpatch directly and that
confuses people with complaints about overly long lines that exceed
80 columns.

The lint test that runs checkpatch (and with the right options)
can also be used on a per-directory basis, so offer that instead.

Change-Id: If21e925d2d2394c876724a44b0e23c9b2744c56b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-16 10:48:18 +00:00
Patrick Rudolph 03a79520d6 cpu/x86/smm: Add support for long mode
Enable long mode in SMM handler.
x86_32 isn't affected by this change.

As the rsm instruction used to leave SMM doesn't restore MSR registers,
drop back to protected mode after running the smi_handler and restore
IA32_EFER MSR (which enables long mode support) to previous value.

NOTE: This commit does NOT introduce a new security model. It uses the
      same page tables as the remaining firmware does.
      This can be a security risk if someone is able to manipulate the
      page tables stored in ROM at runtime. USE FOR TESTING ONLY!

Tested on Qemu Q35.

Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:28:32 +00:00
Patrick Rudolph d5321bf2fb Documentation: Add TODOs for secure SMM when using x86_64
Change-Id: I157238f18bc1c2eba0adc0b87caa9adaf3fc5d38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 07:27:52 +00:00
Paul Menzel 6663ad99cf arch/x86: Support x86_64 exceptions
*   Doesn't affect existing x86_32 code.

Tested on qemu using division by zero.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-05 19:56:09 +00:00
Jonathan Zhang 34cfeee406 doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04 11:16:44 +00:00
Patrick Rudolph f664321508 Documentation: Add several fixes
* Add support for Sphinx 3.0+
* Add backward support for Sphinx 1.8 and older
* Make sphinxcontrib ditaa an optional extension
* Allow SPHINXOPTS to be set from command line
* Add sphinx and sphinx-lint to top level Makefile

Change-Id: If10aef51dc426445cb742aad13b19ee7fe169c51
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41492
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01 21:51:26 +00:00
Kyösti Mälkki 239abaf759 ACPI GNVS: Replace uses of smm_get_gnvs()
Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01 05:14:24 +00:00
Angel Pons 05ba1e9bf2 Doc/mb/google/dragonegg: Drop abandoned project info
Commit 0013623 (mb/google/dragonegg: remove abandoned project) dropped
this mainboard because it is no longer in development nor used. However,
the associated documentation remained. Rest in pieces, Dragonegg. ;-;

Change-Id: Idd2ee716717132ba3fa237ae97f34686007d3685
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30 09:19:52 +00:00
Bill XIE d87277abbf mainboard/lenovo/x230: Add ThinkPad x230s as a variant
The code is based on autoport and that for X230. Major differences are:
    - Only one DDR3 slot
    - HM77 PCH
    - M.2 socket instead of mini PCIe
    - No docking
    - No TPM

Tested:
    - CPU i5-3337U
    - 8GiB SO-DIMM
    - Camera
    - PCIe and USB2 on M.2 slot with A key for WLAN
    - SATA and USB2 (no SuperSpeed components) on M.2 slot with B key for WWAN
    - On board SDHCI connected to PCIe
    - USB3 ports
    - libgfxinit-based graphics init
    - NVRAM options for North and South bridges
    - Sound
    - ThinkPad EC
    - S3
    - Linux 4.9 within Debian GNU/Linux stable, loaded from SeaBIOS.

Untested:
    - Touch screen, which is said to work under ubuntu but not debian.

Change-Id: Id59cdc5479aaf70809dd1ca613056263661455eb
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41390
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29 15:51:23 +00:00
Jonathan Zhang c664b90f05 Doc/mb/ocp: Add documentation for Tioga Pass
Add OCP platform Tioga Pass documentation.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: If4c2832d5bd006c572dab035040b4242f8a3d53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22 11:51:06 +00:00
Patrick Rudolph 2fdabd9038 smmstore: Verify userspace-provided pointer to protect SMM
Use the introduced functions and verify pointers in the SMMSTORE.
Make sure to not overwrite or leak data from SMM and update the
documentation as well.

Change-Id: I70df08657c3fa0f98917742d8e1a6cb1077e3758
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41085
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:18:05 +00:00
Patrick Rudolph 41fec869fb cpu/x86/smm: Add helper functions to verify SMM access
* Add a function to check if a region overlaps with SMM.
* Add a function to check if a pointer points to SMM.
* Document functions in Documentation/security/smm

To be used to verify data accesses in SMM.

Change-Id: Ia525d2bc685377f50ecf3bdcf337a4c885488213
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:17:56 +00:00
Furquan Shaikh 2778420f7f Documentation: Add section about SPD tools for TGL and JSL
CB:41612 added a new set of tools for generating SPDs for TGL and JSL
based mainboards. This change adds relevant documentation to
coreboot-4.13 release notes.

Change-Id: I168adad25df9195dec64e8104f2dbe992eebddc6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42092
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 18:39:15 +00:00
Kyösti Mälkki 4164476dfc mb,soc/intel: Rename acpi_fill_in_fadt() to acpi_fill_fadt()
Change-Id: I9025ca3b6b438e5f9a790076fc84460342362fc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41919
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07 21:45:45 +00:00
Angel Pons 455097616c Doc/mb/gigabyte/ga-h61m-s2pv: Fix in-circuit programming
It is NOT supported. The board is not meant to be flashed externally.

Change-Id: If422810e84355cb94004e5ca2b95d239804699d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
2020-06-06 20:13:34 +00:00