Commit Graph

42482 Commits

Author SHA1 Message Date
Wisley Chen 1852303682 util: Add DDR4 generic SPD for MT40A512M16TB-062E:R
Add SPD support for DDR4 memory part

BUG=b:190020997
TEST=none

Change-Id: I423131cb674e1e5ec699c7a28e5b5e6746247b2a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55164
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:27:39 +00:00
David Wu a85af8ec52 mb/google/volteer/var/trondo: Update gpio settings
This is the same settings as voxel.

BUG=None
TEST=FW_NAME=trondo emerge-volteer coreboot chromeos-bootimage
Verify that the image-trondo.bin is generated successfully.

Change-Id: I04df68ce1683fa32195df1a93f5bde2e3efe6090
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-14 05:27:04 +00:00
Mark Hsieh 352042f002 mb/google/brya: Create gimble variant
Create the gimble variant of the brya0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:190334274
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_GIMBLE

Change-Id: If425571d95b3b20910f890428fb5726ebad2fdf4
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55300
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:26:46 +00:00
Angel Pons bd36177632 3rdparty/intel-sec-tools: Fix submodule pointer
The commit currently being pointed to is unreachable. Use the same
commit that exists in a reachable branch.

Fixes: Commit 1128817ed6
       (3rdparty/intel-sec-tools: Update to support Boot Guard)
Signed-off-by: Angel Pons <th3fanbus@gmail.com>

Change-Id: I1cfc08d48fe5471592fea1013e8b43bea5d7b565
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55414
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:26:05 +00:00
Angel Pons 0fea2c35b1 mb/apple/macbookair4_2: Drop unnecessary select
`GFX_GMA_PANEL_1_ON_EDP` already defaults to `y` on Sandy Bridge.

Change-Id: I481754dc4f086469216c6e939c77b3c84bebea08
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55391
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:24:03 +00:00
Raul E Rangel cb42874231 lib/hardwaremain: Print individual boot state callback durations
This is useful when trying to find which callbacks are taking the
longest time.

BUG=b:179092979
TEST=See bootstate durations in logs
BS: callback (0xcb79d4d8) @ src/security/vboot/bootmode.c:53 (0 ms).
BS: callback (0xcb79cf20) @ src/vendorcode/google/chromeos/ramoops.c:30 (0 ms).
BS: callback (0xcb79cef0) @ src/vendorcode/google/chromeos/cr50_enable_update.c:160 (18 ms).

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb145fea32ad4e0b694bdb7cdcdd43dce4cc0d27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55374
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:20:59 +00:00
Angel Pons 83156682d6 lib/hardwaremain.c: Hide preprocessor guards in header
The `location` member of `struct boot_state_callback` is conditionally
guarded depending on `CONFIG(DEBUG_BOOT_STATE)` using preprocessor. It
is probably intended to save some space when the `location` strings do
not get printed. However, directly using the `location` member without
any guards will cause a compile-time error. Plus, preprocessor-guarded
code gets nasty really quickly.

In order to minimise preprocessor usage, introduce the `bscb_location`
inline helper function, which transforms the compile-time error into a
link-time error. It is then possible to substitute preprocessor guards
with an ordinary C `if` statement.

Change-Id: I40b7f29f96ea96a5977b55760f0fcebf3a0df733
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-14 05:20:05 +00:00
Jeff Chase 444c24a635 mb/google/hatch: Create scout variant
Create the scout variant of the puff reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:187080143
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_SCOUT

Signed-off-by: Jeff Chase <jnchase@google.com>
Change-Id: I3be9d2d30821c2c9132ed94c9faf1f33b62bbc7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-06-14 05:17:55 +00:00
Ivy Jian 114d3ffe6f mb/google/guybrush: Update memory configuration
Regenerate SPD for MT53E1G32D2NP-046 WT:B with correct value of ranks.

BUG=b:190692797
TEST=Build and boot to OS

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Icee095c7114f1d6dd960f2134db3816b367bf987
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-14 05:16:31 +00:00
Kyösti Mälkki 7742aedb0f mb/*/mptable.c: Use smp_write_pci_intsrc()
Split parameter '(devfn << 2) | intx' to 'devfn, intx'.

Formatted with 'spatch --max-width 96'

Change-Id: I17a6b3919b6e55aaa7ca2873ca713b36ebe7d3a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55285
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:15:11 +00:00
Kyösti Mälkki 860cff96dc mb/*/mptable.c: Replace magic constants
Read I/O APIC ID and version from hardware registers.

With coccinelle below, and minor fixups.

@ r1 @
expression E1, E2, E3, E4;
typedef u8;
@@

-smp_write_ioapic(E1, E2, E3, E4);
+u8 ioapic_id = smp_write_ioapic_from_hw(E1, E4);

@ r2 @
expression E1, E2, E3, E4;
@@

-mptable_add_isa_interrupts(E1, E2, E3, E4)
+mptable_add_isa_interrupts(E1, E2, ioapic_id, E4)

@ r3 @
expression E1, E2, E3, E4, E5, E6, E7;
@@

-smp_write_pci_intsrc(E1, E2, E3, E4, E5, E6, E7)
+smp_write_pci_intsrc(E1, E2, E3, E4, E5, ioapic_id, E7)

@ r4 @
symbol mp_INT;
expression E1, E3, E4, E5, E6, E7;
@@

-smp_write_intsrc(E1, mp_INT, E3, E4, E5, E6, E7)
+smp_write_intsrc(E1, mp_INT, E3, E4, E5, ioapic_id, E7)

Change-Id: I20799f0c09cf0292661e1f3cb93373b2c68b7314
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14 05:14:06 +00:00
Raul E Rangel 170ac85d8f security/vboot: Add timestamps when loading verstage
We are not currently tracking how long it takes to load verstage. The
enum values already exist, they just weren't used.

BUG=b:179092979
TEST=Dump timestamps
 501:starting to load verstage                         2,280,656 (1)
 502:finished loading verstage                         2,340,845 (60,189)

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2cde58cb8aa796829a4e054e6925e2394973484b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-14 05:11:07 +00:00
Nikolai Vyssotski cbc7c50b95 soc/amd/cezanne: Supply SMBIOS/DMI Type 17 data
Enable generation of DMI Type 17 data on Cezanne.

BUG=b:184124605
TEST="dmidecode --type 17" in OS on Majolica

Change-Id: Iaa89ee1ce6efa0280f17a443e07571a1190873a6
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-13 09:55:39 +00:00
Nikolai Vyssotski a289cdd59c soc/amd/picasso: Move Type 17 DMI generation to common
Move dmi.c code to common/fsp to be shared among different SOCs.

BUG=b:184124605

Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-13 09:55:30 +00:00
Kangheui Won bdb08188cb soc/amd/cezanne: call boot_with_psp_timestamp
if VBOOT_STARTS_BEFORE_BOOTBLOCK is set, call boot_with_psp_timestamp to
migrate PSP timestamps into x86 timestamp table.

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I4d51802145263145d40908889de29147af54f50f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-13 09:55:02 +00:00
Rex-BC Chen 262bcc04d4 mb/google/cherry: get SKU ID from EC (CBI)
The SKU ID for Cherry is retrieved via CBI interface.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Icefa016c2e5f68bd194f76d2252856835c65b8e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-06-13 03:51:18 +00:00
Benjamin Doron d593bf7dfe util/intelp2m/fsp: Fix wrong register decoding for direction and interrupt
Using the wrong registers to build the fields led to incorrect
GPIO direction and interrupt trigger values. Change the calls
to fix the tables.

Change-Id: Icbeeb1fec6a863d0f86659c21924e15ae6765d47
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54973
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-12 21:21:16 +00:00
Kyösti Mälkki 06b2049ab6 arch/x86/mptable: Add smp_write_ioapic_from_hw()
Add variant that reads I/O APIC ID and version from
hardware registers.

Change-Id: I01bec5f40c6ea60446a28767c7a1725dc25d0ae3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-12 15:49:35 +00:00
Kyösti Mälkki 401ec98e06 arch/x86/ioapic: Add get_ioapic_id() and get_ioapic_version()
Change-Id: I4ad080653c9af94a4dc73d93ddc4c8c117a682b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-12 15:48:49 +00:00
Boris Mittelberg 8997e7b5ae mainboard/google/brya: Enable software sync
This change removes the GBB flag that disables SW sync

BUG:184229267
TEST:manually running chromeos-firmwareupdate

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: Ie8b759a0cdb0c3a0a6458f64c16216459f076e27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55400
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-12 15:35:01 +00:00
Sheng-Liang Pan f586df4e5c mb/google/volteer/var/volet: remove USB4_GEN3 configuration for volet.
volet don't support usb4, remove it to prevent USBC(P0) issue.

BUG=b:189740531
TEST=build and verify USB(P0) disaply out normal

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia78c7cee76ec2e3a5334ad8805a0d45616aade93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55344
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-12 15:03:24 +00:00
Felix Held c0fd6e5ea6 soc/amd/cezanne: remove warm reset flag code
The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1]
suggested; no matter if something was written to the register, the
NCP_WARM_BOOT bit never got set and the NCP_ERR register in I/O-space
always reads back as 0x7f.

[1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev
3.01

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55101
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11 21:48:28 +00:00
Krystian Hebel dee3bc34ad docs/flashmap: state the endianness of FMAP
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: Idf6d46ed262b18c176d69352e333c56f4fdff66a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-06-11 07:41:59 +00:00
Krystian Hebel 3c75a8db35 commonlib/lz4_wrapper.c: do not use bitfields
Order of bits in bitfields is implementation-defined. This makes them
non-portable, especially across systems using different endianness.

This change removes bitfields and uses masking and shifting instead.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: Ief7d87ddb25c9baa931f27dbd54a4ca730b6ece7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-11 07:41:41 +00:00
MAULIK V VAGHELA 926949d64c drivers/intel/gma: Restructure IGD opregion init code
Restructuring opregion VBT related code to make it more generalize
for future revision of opregion spec.

Moved logic to locate VBT from different region (CBMEM, PCI option
ROM or VBIOS) into separate function.

Created a new function to check if extended VBT region is required.
This will be helpful in the subsequent changes to determine if
extended VBT region is needed and handle memory allocation
accordingly.

BUG=None
BRANCH=None
TEST=check the address of extended VBT region and address is coming
correctly.

Change-Id: I479d57cd326567192a3cd1969f8125ffe1934399
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-11 07:38:13 +00:00
Anand K Mistry dd8e819e6b soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century
On Linux, in order to set wake alarms >24 hours, the RTC Date Alarm
field must be set to a valid non-zero value. If not, there are two
consequences:
1. Alarms >24 hours don't work
2. The kernel will refuse to enter suspend because it can't resume as
   expected to service the alarm.

Since the RTC Date Alarm and RTC AltCentury fields are supported on
Stoneyridge, set them.

This is a mirror of commit 041fcf5902
("soc/amd/picasso/acpi: Set missing RTC offsets") for picasso.

BUG=b:187516317
TEST=On a Chrome OS 'grunt' device, run
     `time powerd_dbus_suspend --suspend_for_sec=172800`
     and verify the system suspended and woke up after 48 hours
BRANCH=grunt

Signed-off-by: Anand K Mistry <amistry@google.com>
Change-Id: I10831b982662e680fa71aa81d02935e1b7e7a7a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-11 07:37:43 +00:00
Rob Barnes c7d12f1165 mb/google/guybrush: Add EC_HOST_EVENT_HANG_DETECT to wake mask
Add EC_HOST_EVENT_HANG_DETECT to S3/S5/S0ix wake mask. This event is
sent when the EC detects the AP didn't fully enter a sleep state.

BUG=b:186571086
TEST=Trigger hang detect while AP is in S0ix, AP wakes from S0ix

Change-Id: I09ccf609fc453c19b4fb1ddaa5a0c86d7a85aad1
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-11 07:37:02 +00:00
Taniya Das e689378d88 sc7280: Add target specific GPIO pin definitions
Add GPIO pin details specific to SC7280 chipset
for the consumers to be able to request for the
gpio functionality as per their requirement.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-11 07:36:16 +00:00
Shaik Sajida Bhanu 5ef1a839c7 drivers/spi: Add winbond chip details
Added winbond W25Q512NW chip details.

Change-Id: I5545c9431891f7fa74c1527591fb7c3cd3aba687
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-11 07:33:33 +00:00
Sridhar Siricilla ef9136ff25 mb/google/brya: Update PMC Descriptor for Alder lake A0(0x906a0) silicon
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons.

BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if
not updated.

coreboot logs appear as below with this patch:

On First boot after flashing the image:

	coreboot-coreboot-unknown.9999.4589c0f Wed Jun  9 18:23:43 UTC 2021 bootblock starting (log level: 8)...
	CPU: Genuine Intel(R) 0000
	CPU: ID 906a0, Alderlake Platform, ucode: 0000001a
	..
	FMAP: Found "FLASH" version 1.1 at 0x1804000.
	FMAP: base = 0x0 size = 0x2000000 #areas = 32
	FMAP: area SI_DESC found @ 0 (4096 bytes)
	SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
	Erasing flash addr 0 + 4 KiB
	Update of PMC Descriptor successful, trigger GLOBAL RESET

Next boot after GLOBAL RESET:

	coreboot-coreboot-unknown.9999.4589c0f Wed Jun  9 18:23:43 UTC 2021 bootblock starting (log level: 8)...
	..
	FMAP: area SI_DESC found @ 0 (4096 bytes)
	SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
	Update of PMC Descriptor is not required!
	VBOOT: Loading verstage.
	..
	CBFS: Found 'fallback/verstage' @0x2264c0 size 0x16b08 in mcache @0xfef84d38

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-11 07:33:03 +00:00
Sridhar Siricilla f93aa04266 soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"
Since common CPU ID between ADL-P and ADL-M CPU IDs, the patch renames all
ADL-P and ADL-M Silicon CPUID macros and defines generic name
"Alderlake Platform" as macro value. Also, this will avoid log ADL-M  for
ADL-P CPU and vice-versa. Although currently name field of "cpu_table"
points to only "Alderlake Platform, but it is retained asa placeholder in
future difference platforms.

Please refer EDS doc# 619501 for more details.

The macros are renamed as below:
CPUID_ALDERLAKE_P_A0 -> CPUID_ALDERLAKE_A0
CPUID_ALDERLAKE_M_A0 -> CPUID_ALDERLAKE_A1
CPUID_ALDERLAKE_P_B0 -> CPUID_ALDERLAKE_A2

TEST=Verify boot on Brya. After change, relevent coreboot logs appear as
below:

CPU: ID 906a1, Alderlake Platform, ucode: 00000119
CPU: AES supported, TXT supported, VT supported
MCH: device id 4601 (rev 03) is Alderlake-P
PCH: device id 5181 (rev 00) is Alderlake-P SKU
IGD: device id 46b0 (rev 04) is Alderlake P GT2

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia06d2b62d4194edd4e104d49b340ac23305a4c15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55252
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11 07:32:46 +00:00
Lean Sheng Tan 0cdcdc736e soc/intel/elkhartlake: Update FSP-S FuSa related settings
Further add initial Silicon UPD settings for FuSa
(Functional Safety). Disable all by default, due to FSP binary
enable all by default.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I88264ba3e3f9f54ad949c55b230082d1fa289fa4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55342
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11 07:32:17 +00:00
Kyösti Mälkki dea42e011a cpu/x86/lapic: Replace LOCAL_APIC_ADDR references
Note that there are assumptions about LAPIC MMIO location
in both AMD and Intel sources in coreboot proper.

Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11 07:11:43 +00:00
Lean Sheng Tan a96be277e1 soc/intel/elkhartlake: Update FSP-S PM & Thermal related configs
Further add initial Silicon UPD settings for thermal and power
management stuffs.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I04ded059c36f18925b7a74c934fef2566c3db8fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-11 05:52:03 +00:00
Aseda Aboagye 08938a9be3 security/vboot: Add support for ZTE spaces
This commit adds support for the Chrome OS Zero-Touch Enrollment related
spaces.  For TPM 2.0 devices which don't use Cr50, coreboot will define
the RMA+SN Bits, Board ID, and RMA Bytes counter spaces.

The RMA+SN Bits space is 16 bytes initialized to all 0xFFs.
The Board ID space is 12 bytes initialized to all 0xFFs.
The RMA Bytes counter space is 8 bytes intialized to 0.

BUG=b:184676425
BRANCH=None
TEST=Build and flash lalala, verify that the ZTE spaces are created
successfully by undefining the firmware antirollback space in the TPM
such that the TPM undergoes factory initialization in coreboot.  Reboot
the DUT. Boot to CrOS and run `tpm_manager_client list_spaces` and
verify that the ZTE spaces are listed.  Run `tpm_manager_client
read_space` with the various indices and verify that the sizes and
initial values of the spaces are correct.
TEST=Attempt to undefine the ZTE spaces and verify that it fails due to
the unsatisfiable policy.

Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55242
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10 23:38:53 +00:00
Aseda Aboagye 4ad0420e82 security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()`
This commit adds support for the TPM2_NV_SetBits command to the TLCL.
This command is used to set bits in an NV index that was created as a
bit field.  Any number of bits from 0 to 64 may be set.  The contents of
bits are ORed with the current contents of the NV index.

The following is an excerpt from lalala undergoing TPM factory
initialization which exercises this function in a child commit:

```
antirollback_read_space_firmware():566: TPM: Not initialized yet.
factory_initialize_tpm():530: TPM: factory initialization
tlcl_self_test_full: response is 0
tlcl_force_clear: response is 0
tlcl_define_space: response is 14c
define_space():197: define_space: kernel space already exists
tlcl_write: response is 0
tlcl_define_space: response is 14c
define_space():197: define_space: RO MRC Hash space already exists
tlcl_write: response is 0
tlcl_define_space: response is 14c
define_space():197: define_space: FWMP space already exists
tlcl_write: response is 0
tlcl_define_space: response is 0
tlcl_write: response is 0
tlcl_define_space: response is 0
tlcl_write: response is 0
tlcl_define_space: response is 0
tlcl_set_bits: response is 0
tlcl_define_space: response is 0
tlcl_write: response is 0
factory_initialize_tpm():553: TPM: factory initialization successful
```

BUG=b:184676425
BRANCH=None
TEST=With other changes, create a NVMEM space in a TPM 2.0 TPM with the
bits attribute.  Issue the command and verify that the TPM command
succeeds.

Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I6ca6376bb9f7ed8fd1167c2c80f1e8d3c3f46653
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55241
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10 23:38:47 +00:00
Martin Roth 455e07e7f3 mb/google/guybrush: Move variant_has_fpmcu() after eSPI init
Currently variant_has_fpmcu() is called very early in bootblock, before
eSPI is initialized.  When checking CBI for its presence, that causes
an error and nothing else can be read from CBI in bootblock.

Moving it slightly later in bootblock doesn't hurt anything from a
timing standpoint, and allows CBI to be read.

BUG=None
TEST=See CBI get read and the FPMCU field read correctly.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6de44119e92c8820b266f9f07287706c7d4eb505
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-10 21:33:56 +00:00
Daisuke Nojiri 494a5dd7f5 vboot: Assign 2 to EC_EFS_BOOT_MODE_TRUSTED_RO
This patch assings 2 to EC_EFS_BOOT_MODE_TRUSTED_RO to make coreboot
set VB2_CONTEXT_EC_TRUSTED when the GSC reports TRUSTED_RO.

Old GSC doesn't use 2. So, the new BIOS won't mistakenly set
VB2_CONTEXT_EC_TRUSTED.

BUG=b:180927027, b:187871195
BRANCH=none
TEST=build

Change-Id: I11a09d0035a4bd59f80018c647ca17e3318be81e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55373
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10 21:26:48 +00:00
Kyösti Mälkki 08f4526b53 cpu/x86/lapic: Drop read/write_around aliases
Change-Id: Ia3935524e57885ca79586f1f4612020bb05956ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-10 20:57:41 +00:00
Martin Roth 146508d749 drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPS
The loads of the FSPM and FSPS binaries are not insignificant amounts of
time, and without these timestamps, it's not clear what's going on in
those time blocks.  For FSPM, the timestamps can run together to make it
look like that time is still part of the romstage init time.

Example:
   6:end of verified boot                              387,390 (5,402)
  13:starting to load romstage                         401,931 (14,541)
  14:finished loading romstage                         420,560 (18,629)
 970:loading FSP-M                                     450,698 (30,138)
  15:starting LZMA decompress (ignore for x86)         464,173 (13,475)
  16:finished LZMA decompress (ignore for x86)         517,860 (53,687)
...
   9:finished loading ramstage                         737,191 (18,377)
  10:start of ramstage                                 757,584 (20,393)
  30:device enumeration                                790,382 (32,798)
 971:loading FSP-S                                     840,186 (49,804)
  15:starting LZMA decompress (ignore for x86)         853,834 (13,648)
  16:finished LZMA decompress (ignore for x86)         888,830 (34,996)

BUG=b:188981986
TEST=Build & Boot guybrush, look at timestamps.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-10 20:47:59 +00:00
Patrick Georgi ae41dd3344 tests/console: Add tests for log message routing behavior
Change-Id: Id978cfe4fa45fef9edbc3d3b55606ff6973521c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-06-10 19:27:44 +00:00
Patrick Georgi ce55ca2fca tests: Rework mocking facility
Using the linker's --wrap feature has the downside that it only covers
references across object files: If foo.c defines a() and b(), with b
calling a, --wrap=a does nothing to that call.

Instead, use objcopy to mark a weak and global so it can be overridden
by another implementation, but only for files originating in src/.

That way mocks - implemented in tests/ - become the source of truth.

TEST=Had such an issue with get_log_level() in a follow-up commit, and
the mock now takes over. Also, all existing unit tests still pass.

Change-Id: I99c6d6e44ecfc73366bf464d9c51c7da3f8db388
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-06-10 19:26:46 +00:00
Kyösti Mälkki 36c90179f0 cpu/x86/lapic: Separate stop_this_cpu()
Function is needed with PARALLEL_MP and excluding guard will
be added to the source file.

The incompatibilities with X2APIC_SUPPORT have been fixed
so the exclusion is removed here too.

Change-Id: I5696da4dfe98579a3b37a027966b6758f22574aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-10 17:51:51 +00:00
Kyösti Mälkki 68fe11beb0 cpu/x86/lapic: Add wait_ipi_completion() helpers
Change-Id: Ib9c404cb55b96dcc5639287c214c5c8f468c0529
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10 17:50:38 +00:00
Arthur Heymans a4ceba4ae5 cpu/x86/lapic: Add lapic_busy() helper
Change-Id: Ife127d6dc8241cccb9d52236a9152da707f0e261
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55191
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10 17:49:16 +00:00
Arthur Heymans 6f77ff7ba5 cpu/x86/lapic: Add lapic_send_ipi() helper
Change-Id: I7207a9aadd987b4307ce8b3dd8dbfd47d0a5768e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55190
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10 17:48:28 +00:00
Kyösti Mälkki 242f1d962f cpu/x86/lapic: Do not inline some utility functions
They are not __always_inline and specially enable_lapic()
will become more complex to support X2APIC state changes.

Change-Id: Ic180fa8b36e419aba07e1754d4bf48c9dfddb2f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55258
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10 17:47:59 +00:00
Kyösti Mälkki 0cfa9110b6 cpu/x86/lapic: Add lapic_update32() helper
Change-Id: I57c5d85d3098f9d59f26f427fe16829e4e769194
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55187
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10 17:46:48 +00:00
Kyösti Mälkki 41e6216df3 cpu/x86/lapic: Regroup LAPIC accessors
Change-Id: I4347fc6542f59f56bd8400181efa30247794cf96
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55186
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10 17:45:58 +00:00
Lean Sheng Tan b89832ac6a soc/intel/elkhartlake: Fix gpio_soc_defs.h variable typo
Fix GPIO_COM2_END from GPIO_RSVD_2 to GPIO_RSVD_12.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I670f4bec8f141da73428010371754746a455df25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55334
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10 09:53:39 +00:00