Commit Graph

6004 Commits

Author SHA1 Message Date
Mathias Krause 1c80cf04fe kbd: wait longer for self-test on keyboard reset
Some keyboards take pretty long to respond to a reset command, some even
delay the ACK to the command. To make the keyboard driver more robust,
increase the timeout for this special command. Also do an interface test
after the self-test to ensure the keyboard is functioning properly.

Another point is to reenable the keyboard *after* the scancode was set,
not before. We also set the system bit when enabling the keyboard
because this seems to be what older operating systems do expect.

One of the problematic keyboards, which will work with this patch
applied, is the DELL RT7D20. Without the patch an overly optimistic
operating system, read Linux 2.4, will not recognise the keyboard
because coreboot didn't fully initialize it.

Change-Id: I28c8e05bdde61f71b7de084c96bc2447c1b9575e
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/486
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-21 16:25:20 +01:00
Marc Jones f154c01802 Persimmon audio codec verb patch.
Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
data is not required for mainboards that use G-Series HDMI. It is also a setting
the may be boards specific. This fixes issues with Windows audio on Persimmon.

Change-Id: I067506871e92078d122cf79872363d8937d47e50
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/490
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-21 01:06:16 +01:00
Peter Stuge 6eefef9f2c .gitignore util/crossgcc/build-* and unpacked source directories
Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/484
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-15 22:15:17 +01:00
Sven Schnelle d5992b8dd1 Lenovo X60/T60: add first_battery setting
The EC allows to select the order in which batteries are (dis)charged.
Make this setting available to the user.

Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/475
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14 09:41:46 +01:00
Florian Zumbiehl 009ad83d5c asus k8v-x: explicitly set RAM and bus voltages
Change-Id: I9426cafc252ee765d723af569c4a90e090d313d9
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/482
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14 08:51:58 +01:00
Florian Zumbiehl 36b53bf244 k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/481
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14 08:50:45 +01:00
Stefan Reinauer 20d9de33cc Fix console output in real mode int10 implementation.
Checking RBIL, int10 AH=0x10 does never output a character.
The two output functions are AH=0x09 and AH=0x0e.

Change-Id: Id7f4d260b63024748ef771f949e8b60f934bacbc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/483
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-13 23:46:27 +01:00
Patrick Georgi dbde809558 libpayload: add set_option() function
It allows to change CMOS values from payloads

Change-Id: I4872fc27476923adafe13504126235b92b30de85
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/445
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-13 23:22:26 +01:00
Patrick Georgi a27561c3c9 Fix CMOS handling for non-USE_OPTION_TABLE configuration
The read_option macro still emitted CMOS_VSTART_*/CMOS_VEND_* symbols,
which fail without an option table (as no option_table.h defines them).

Discard them by using a macro instead of a static inline function.

Change-Id: I8d001f971681277a344b6788725746491546b607
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/442
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-13 23:20:49 +01:00
Marc Jones 90ca14d700 Use MMCONF for all AMD family 10 CPUs.
This fixes problems in AP init when multiple APs are trying to access
PCI config space. All Fam10 CPUs setup and support MMCONF.

Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/455
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-13 01:58:36 +01:00
Alec Ari 403d2d697e Change DSDT Table ID for M4A785T-M board
Change the DSDT Table ID for M4A785T-M
from M4A785-M to M4A785T-M.

This fixes a small copypasta.

This is an updated patch set.

Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-08 22:42:04 +01:00
Kyösti Mälkki b192df4d97 Fix ldscript for bootblock .rom section
Allocation size for the section was miscalculated, so the section
did not honour its upper-bound address.

Also align the section start to 4 bytes, so it starts with code
instead of pad bytes.

Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/453
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-08 10:42:39 +01:00
Kyösti Mälkki 4c132bbc51 Fix AMD 8132 and 8151 southbridge builds
Untested, changes ramstage build for boards:
  supermicro/h8qme_fam10
  amd/serengeti_cheetah
  amd/serengeti_cheetah_fam10

AMD 8132 was not built for any mainboard due to a typo.

AMD Serengeti Cheetah:
  Chip 8151 is referenced in devicetree.cb but was not built.

AMD Serengeti Cheetah Family10:
  There are indications the board has 8151, but it is not listed
  in the devicetree.cb. The 8151 chip is not added in the build.

Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/471
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-12-06 06:20:32 +01:00
Kyösti Mälkki eafb18be43 Bootblock does not need a unique boot_cpu()
Detection of a CPU being a BSP CPU is not dependent of the existence
of northbridge and/or southbridge init code in the bootblock.

Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP
CPU of a hyper-threading CPU and needs to return actual BSP bit from
MSR.

Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/447
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-05 12:20:43 +01:00
Denis 'GNUtoo' Carikli 7519d77f72 RS780: print the vgainfo
With this commit the vgainfo is printed and looks like that on the serial console:
vgainfo:
  ulBootUpEngineClock:50000
  ulBootUpUMAClock:66700
  ulBootUpSidePortClock:0
  ulMinSidePortClock:0
  ulSystemConfig:0
  ulBootUpReqDisplayVector:0
  ulOtherDisplayMisc:0
  ulDDISlot1Config:0
  ulDDISlot2Config:0
  ucMemoryType:0
  ucUMAChannelNumber:1
  ucDockingPinBit:0
  ucDockingPinPolarity:0
  ulDockingPinCFGInfo:0
  ulCPUCapInfo: 2
  usNumberOfCyclesInPeriod:0
  usMaxNBVoltage:0
  usMinNBVoltage:0
  usBootUpNBVoltage:0
  ulHTLinkFreq:20000
  usMinHTLinkWidth:8
  usMaxHTLinkWidth:8
  usUMASyncStartDelay:100
  usUMADataReturnTime:300
  usLinkStatusZeroTime:600
  ulHighVoltageHTLinkFreq:20000
  ulLowVoltageHTLinkFreq:20000
  usMaxUpStreamHTLinkWidth:8
  usMaxDownStreamHTLinkWidth:8
  usMinUpStreamHTLinkWidth:8
  usMinDownStreamHTLinkWidth:8

Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/456
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-05 08:58:43 +01:00
Florian Zumbiehl 6cdf5a9e2e adding support for the Asus K8V-X
This pulls it all together and adds the real board-specific code.

Confirmed to be working:
- IDE
- SATA
- floppy
- USB1.1
- USB2.0
- PS/2 keyboard
- PS/2 mouse
- serial
- parport
- sound
- ethernet
- PCI slots
- AGP
- powernow
- fan speed monitoring
- flashrom write

Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/390
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
2011-12-03 13:13:36 +01:00
Rudolf Marek f22a6d0c5e Fix Asus A8V-E SE DIMM slot mapping
Fix the DIMM mappings, channel 0 is "B" on board,
and secondary channel is on 0x51,0x53

Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/449
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-03 10:49:32 +01:00
Florian Zumbiehl b5320573c3 make GPIOs and misc configurable via devicetree
Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/387
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02 23:25:58 +01:00
Florian Zumbiehl 98236ca784 make INT[EFGH]# of vt8237 configurable as gpio via devicetree
Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/386
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02 23:23:24 +01:00
Florian Zumbiehl 2138556e2a copied asus a8v-e_se to k8v-x
Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/389
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02 23:20:20 +01:00
Florian Zumbiehl 6a3e8d62f8 some black magic for initializing the old version of the k8t800
Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/388
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02 23:11:56 +01:00
Florian Zumbiehl 1b940fd424 implement usb2 termination and dpll delay setting for vt8237r
Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/385
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02 23:06:20 +01:00
Sven Schnelle 28bdd8d9eb i3100: Add HAVE_HARD_RESET
and remove it from mainboard/intel/mtarvon, as this function
is implemented in the southbridge code.

Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/469
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02 18:10:51 +01:00
QingPei Wang 45945cf445 Mirror Fix coreinfo usage of cb_info
fix cb_info.serial.ioport to cb_info.serial.baseaddr

Change-Id: I32f261e4be927555979eb833d0251fce2c6a5c47
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/441
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02 17:30:11 +01:00
Denis 'GNUtoo' Carikli 490eb86b48 M4A785T-M: fix ACPI's P-States Table
Without that fix the linux kernel cannot change the frequency
  of the CPUs with cpufreq.

Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/458
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02 17:28:00 +01:00
Denis 'GNUtoo' Carikli 96ffc55bfd Add ASUS M4A785T-M mainboard support
This mainboard is very similar to the M4A785-M, but it has
  DDR3 instead of DDR2.

That's why most of the code was copied or included from
  the m4a785-m directory

Notable changes between the two mainboards include:
 * the selection of the last microcode (mc_patch_010000b6.h)
   which made it pass the CPU init.
 * the selection of DDR3 which made it pass the ram init

This change was tested with the Trisquel 5.0 GNU/Linux distribution
  which uses the linux-libre version 2.6.38-12-generic

The mainboard boots fine, however some special care is required for
  the onboard sound CODEC, and the onboard video chip:
  * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue
    is the same than the ASUS M4A785-M mainboard:
    It causes a flood of interupts which prevents booting
  * The internal video chip currently requires pci=nocrs, else
    the graphics are frozen as soon as the radeon module loads,
    and dmesg would print the following(the card only has 256M,
    and the mainboard was equiped with 2G of RAM):
      [    3.674762] [drm] radeon: 3584M of VRAM memory ready
      [    3.679863] [drm] radeon: 512M of GTT memory ready.
    instead of :
      [   45.876088] [drm] radeon: 256M of VRAM memory ready
      [   45.876089] [drm] radeon: 512M of GTT memory ready.
  * The screen(both VGA and HDMI) flickers at high resolution
  * Sometimes the computer freeze while changing the resolution
    (even the serial console stops responding)

The following peripherals were tested:
 * The ath9k PCI wireless card was tested
 * The SATA hard disk works fine
 * the USB keyboard and mouse work fine
 * htop see 2 cores
 * serial port works under coreboot and GNU/Linux
 * power off and reboot works

CPU frequency cannot be changed yet, this is addressed
  in a new commit.

More detail are available here:
  http://www.coreboot.org/ASUS_M4A785T-M

dmesg is available here:
  http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html

The mailing list thread on the graphic problem is here:
  http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html

Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/457
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02 17:27:51 +01:00
Kyösti Mälkki 188a9b0a7f Remove obsolete TINY_BOOTBLOCK
Change-Id: I0edc69dc5f95cc32ee648eb094c9e5387f80db47
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/470
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02 17:26:18 +01:00
Kyösti Mälkki 2a830d0b98 Change AMD vendorcode build
Apply the normal method of recursively including subdirectories
for src/vendorcode. Remove redundant references under
mainboard and northbridge.

Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/468
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02 08:59:26 +01:00
Sven Schnelle 2c1f4d2d83 X60/T60: reset baudrate loglevel to sane values
Change-Id: Iaf5861e9db0a41a184da6d2e515e3b9afe0655d6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/459
Tested-by: build bot (Jenkins)
2011-12-01 11:55:43 +01:00
Kyösti Mälkki 0dbfb54a72 Remove unused code files and cosmetic changes
Following files were no longer used in the build and are deleted:
   src/arch/x86/init/entry.S
   src/arch/x86/init/ldscript.ld

Also fix ugly whitespace in code copyrights and comments.

Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/440
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-24 11:43:11 +01:00
Florian Zumbiehl 912d8919d4 vt8237: add support for setting the power state after loss of power
Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/437
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-24 00:12:41 +01:00
Florian Zumbiehl fa48b96908 k8 raminit: fix bug, improve clock selection, add clock limit for sock754
in amdk8 raminit:
- fix DDR SPD offset for (CLX - 1) (25 instead of 26)
- improve clock/CL selection algorithm
- implement load-dependent clock limiting for socket 754

Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/377
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-23 01:05:40 +01:00
Florian Zumbiehl 85392a8c98 implement hwmon fan divisor setting for w83697hf
Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/384
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
2011-11-22 23:07:03 +01:00
Florian Zumbiehl 04a8d6239f k8 raminit: add workaround for erratum #181 on non-fam-f
Disable DRAM controller on non-fam-f CPUs not using fam-f register layout.

Change-Id: I2cc87857452555011d69bfebe9f9c4c17cef8f6c
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/448
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-11-22 22:20:30 +01:00
Kyösti Mälkki 2a40ebca9c Fix post_code in 16bit entry
Relocate early post_code() so it gets executed and does not corrupt
BIST at %eax.

Change-Id: Ieeebcb23f7c327e501b410eaa60d1e49110ee988
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/439
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-22 11:17:07 +01:00
Kerry Sheh b9136ed847 mainboard: Add AMD unionstation RDK support
AMD unionstation Reference Design Kit is Designed for hd settop box application.
This platform using family14 APU, SB800 southbridge.
Vgabios is required, can download vgabios from AMD NDA website.
Verified Feature:
 HDMI, LAN, mini-pcie slots, sata, usb, analog audio and
 optical fiber digital audio output.

Change-Id: Ib1d1d8c889d6fb29f4298b57dfe5c5c1cea1431c
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-11-18 21:44:02 +01:00
Kerry Sheh b79935129a mainboard: Add AMD southstation RDK support
AMD southstation Reference Design Kit is designed for NAS application.
This platform using family14 RevC0 processor, SB850 southbridge.
Vgabios and Promise RAID Option ROM is required for hardware RAID support,
can retrieve from the AMD NDA website.
Verified feature:
 HDMI, LAN, usb and mini-pcie slot.
 RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10.

Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-11-18 21:38:59 +01:00
Florian Zumbiehl 6f7b1589fa fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit
Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/376
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-16 22:40:21 +01:00
Patrick Georgi ba9b09b89a libpayload: Enable colors in PDcurses
PDcurses wants set_blink to determine color count. Not exactly
obvious.

Change-Id: I8b2a32f0095d5900fa7e01f04f3f1d565dc2bedf
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/432
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-11 18:24:48 +01:00
Florian Zumbiehl 50dadfb1f8 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included
for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD

Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/374
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-10 23:55:11 +01:00
Florian Zumbiehl be7d8dcf8d support for different location of HT registers in old version of K8T800
Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/373
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-10 23:54:41 +01:00
Patrick Georgi 583abc2eb2 libpayload: Fix handling of CAPS LOCK key on PS/2 keyboards
The PS/2 keyboard driver set and reset the caps LED to show the
keyboard status. Unfortunately, that configuration happens over
the same path used to transmit keypresses.

In face of certain error conditions, the keyboard stopped working.
This change makes keyboard handling more robust.

Change-Id: I0489a9983ea7dab00357220e09398dd1a8538839
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/430
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-10 17:51:53 +01:00
Oskar Enoksson f5e102d810 Fixed whitespace and indentation
Code style fixes for the hp/dl145_g1 system board code.

Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/428
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-09 00:26:23 +01:00
Patrick Georgi c1a75b13c3 buildgcc: Add option to use ccache
This mimicks abuild: -y enables ccache.

Change-Id: I3ac1f809729af816efbc64f5789ab430e1a6a6b2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/400
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-09 00:25:44 +01:00
Florian Zumbiehl 4a5c62cf91 make w83697hf_set_clksel_48() non-static and add a prototype
make w83697hf_set_clksel_48() non-static and add a prototype so as to
get rid of warnings about it being unused

Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-08 21:26:30 +01:00
Stefan Reinauer ab4c218379 selfboot: Don't include unneeded ip_checksum.h
Change-Id: I09b888e70f7432f7025b0b851acfb0279553400f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/426
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-08 21:21:55 +01:00
Stefan Reinauer c6b8b7dcc4 selfboot: fix bug in valid_area()
valid_area will accept a region as valid for the payload if only a part
of coreboot fits in that region. This means if a payload reaches into a
neighboring RESERVED region, coreboot would not care and happily
overwrite that region, as long as the payload also writes to some RAM.

Change-Id: Ie263f83be18009b01a31c71e7285c998747d097f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/425
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-08 21:19:22 +01:00
Stefan Reinauer 2e2b84e420 move function from header file to .c file
http://review.coreboot.org/#change,378 introduced a function in k8x8xx.h
move this function to ctrl.c and add a prototype to the header file instead.

Change-Id: I0919ffb2030c53669b95f58b649d4a160f660923
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/429
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-08 21:15:52 +01:00
Marc Jones 36abff1dc8 Cleanup Persimmon mainboard whitespace.
Change-Id: I389bde86c5583a4fb37a699162b65b475ed94ddc
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/427
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-08 19:01:43 +01:00
Stefan Reinauer 1943629871 selfboot: cleanup
- move cbfs_load_payload to the end so we can drop the prototype
- move lb_start and lb_end to the beginning so they can be used
  in other functions.
- drop two unused function declarations
- break a 80+ characters line
- fix a comment

Change-Id: I460aa1e2ccf9d95ac12233af001076f73ab0268e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/424
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-08 12:25:26 +01:00