Fastboot support in vboot_reference is unused, unmaintained, and
produces compile errors when enabled. Since there is no current
or planned use cases for fastboot, remove it.
BUG=b:124141368, chromium:995172
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I06ea816ffb910163ec2c3c456b3c09408c806d0b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35002
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove duplicated code and instead use the IPMI KCS driver, which provides
the same functionality.
Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Advertise the register spacing used by the BMC as set by the Kconfig.
Tested on OCP Monolake.
Change-Id: Ib926d30f6a0e78fbf613a6f71f765c5f51eee77d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Add Kconfig to enable TXT
* Add possibility to add BIOS and SINIT ACMs
* Set default BIOS ACM alignment
* Increase FIT space if TXT is enabled
The following commits depend on the basic Kconfig infrastructure.
Intel TXT isn't supported until all following commits are merged.
Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 [1]
registers values from the inteltool dump, is more understandable and
makes the code much cleaner. The pad configuration in this patch was
generated using the pch-pads-parser utility [2]. The inteltool dump
before and after the patch is identical (see notes)
Notes:
1. For some reason, GPIO RX State (RO) for the GPP_F4 and GPP_G10
changed the value to 0, but this doesn't affect the motherboard
operation. Perhaps this is because PAD_CFG1_GPIO_DRIVER is set to
PAD_CFG_GPI_INT(), and the pad is not actually connected. So far I
haven't circuit diagram to check this out.
2. According to the documentation [1], the value 3h for RXEVCFG is
implemented as setting 0h.
3. If the available macros from gpio_defs.h [3] can't determine the
configuration of the pad, the utility [2] generates common
_PAD_CFG_STRUCT() macros
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
[2] https://github.com/maxpoliak/pch-pads-parser/tree/stable_1.0
[3] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
Change-Id: I01ad4bd29235fbe2b23abce5fbaaa7e63c87f529
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for the X11SSH-TF which is based on Intel KBL.
Working:
* SeaBIOS payload
* LinuxBoot payload
* IPMI of BMC
* PCIe, SATA, USB and M.2 ports
* RS232 serial
* Native graphics init
Not working:
* TianoCore doesn't work yet as the Aspeed NGI is text mode only.
* Intel SGX, due to random crashes in soc/intel/common
For more details have a look at the documentation.
Please apply those patches as well for good user experience:
Ica0c20255f661dd61edc3a7d15646b7447c4658e
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Platforms using postcar are with RELOCATABLE_RAMSTAGE=y. They
don't benefit from having low-memory set as writeback-cacheable.
This also fixes regression from CB:34893 that caused some random
hangs with more recent intel SoCs in ramstage.
BUG=b:140250314
Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Adjust CID to allow for Windows driver to attach without breaking
functionality under Linux. Same change made as to google/cyan
(which uses same Realtek RT5650 codec) in commit 607d72b.
Test: build/boot Windowns 10 on google/buddy, observe audio
drivers correctly attached to codec and Intel SST devices.
Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Increase CBFS and RAMSTAGE size to accommodate larger binary component.
BUG=b:77641795
TEST=Build and test on Gale.
BRANCH=none
Change-Id: I25f7121221ab2bb66dfedbc4a66e06976d88cef5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e4d3d2d078d0a8f705afe2b6c741118727614bf0
Original-Change-Id: I6ad16c0073a683cb66d5ae8a46b8990f3346f183
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1366388
Original-Reviewed-by: Zhihong Yu <zhihongyu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35134
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes the need for COREBOOT_BUILD_DIR in Kconfig. Since the
original files will be replaced with the tmp file, the parent directory
already needs to be writable.
Before this change, the tmp files would be created in the CWD (src) if
COREBOOT_BUILD_DIR was not specified.
BUG=b:112267918
TEST=emerge-grunt coreboot and verified no tmp files were created in the
src directory.
Change-Id: Icdaf2ff3dd1ec98813b75ef55b96e38e1ca19ec7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34244
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If KCONFIG_CONFIG is set to a full path, we should generate the tmp file
in the same directory instead of the current working directory.
BUG=b:112267918
TEST=emerge-grunt coreboot and verified with print statements that the
correct path was used.
Change-Id: Ia21e930a9b0a693f851c34bcde26b34886cbe902
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The Intel platforms using eSPI EC communication have just been enabling
the EC_GOOGLE_CHROMEEC_LPC option for simplicity. This does basically
the same, but at least marks it as eSPI in Kconfig for clarity.
BUG=b:140055300
TEST=Build tested only.
Change-Id: Ib56ec9d1dc204809a05c846494ff0e0d69cf70ea
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35128
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH
[3] supports up to 16 PCIe ports. However, ACPI contains a description
for only 12 ports. This patch adds ACPI code for missing ports
[1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2,
December 2018, Document Number: 332690-005EN
[2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2,
October 2017, Document Number: 335192-003
[3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
(PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drallion will change debug port UART from 2 to 0. Followed HW
schematic to modify it.
BUG=b:139095062
BRANCH=N/A
TEST=Build without error
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Enable acoustic noise mitgation for hatch platform, the slow slew rates
are fast time dived by 8 and disable Fast PKG C State Ramp(IA, GT, SA).
BUG=b:131779678
TEST=waveform test and reduce the noise level.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I49e834825b3f1e5bf02f9523d7caa93b544c9d17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch renames arm_tf.c and arm_tf.h to bl31.c and bl31.h,
respectively. That name is closer to the terminology used in most
functions related to Trusted Firmware, and it removes the annoying
auto-completion clash between arm64/arm_tf.c and arm64/armv8.
Change-Id: I2741e2bce9d079b1025f82ecb3bb78a02fe39ed5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Also don't define the default as this result in spurious lines in the
.config.
The only difference in config.h is on boards with the Nvidia tegra210
SOC that now select ARCH_ARM64, because its ramstage runs in that
mode. The resulting binary is identical however.
Change-Id: Iaa9cd902281e51f823717f6ea4c72e5736fefb31
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31315
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes the need to select ARCH_ARM in SOC Kconfig
Also don't define the default as this result in spurious lines in the
.config.
Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31313
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There will be inlined smm_lock() that would conflict
with this special case.
Change-Id: I6752cbcf4775f9c013f0b16033b40beb2c503f81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34874
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current HWID for drallion is reported as invalid by chrome, generate
new valid HWID with the following command and taking last 4 digits.
`printf "%d\n" 0x$(crc32 <(echo -n '$1'))`
BUG=b:140013681
Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Many (if not all) platforms have moved to using consistent
boot flow constructs where a weak car_stage_entry() is no longer
necessary to avoid the complexity of handling the numerous and
different boot flow combinations. The weak symbol is just causing
issues so remove it.
Change-Id: I7e7897c0609aac8eef96a08bb789374b2403956d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35135
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement sa_get_tseg_base and sa_get_tseg_size.
Used by Intel TXT and the new SMM API.
Tested on OCP/Wedge100S.
Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
There are no more cases that need to override this.
Change-Id: Iafa94af19eae00cc5be5d4ff7454066558e3c74f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34741
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MSRs were already named as PRMRR in broadwell, just
mismatching with the rest of the code. All later devices
use the names PRMRR and UNCORE_PRMRR for these MSRs.
Reflect the name change in structures and local variables.
Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34825
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I'm moving the .xcompile file into the $(obj) directory so we can leave
the source pristine. We need to pass the location of .xcompile into
genbuild_h.sh.
BUG=b:112267918
TEST=Ran genbuild_h with and without an .xcompile and verified it was
passed.
Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This reduces disk usage during builds by removing all object files and
other intermediate files directly after a build instead of waiting for
the entire build to pass.
Change-Id: Ic2feecd58658e8bac8c6e7a851737784e35b83ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35112
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This option removes everything in the build tree but coreboot.rom,
config.build, config.h and make.log - a useful subset of the tree for
further testing.
Change-Id: I27e559d8d7dc90d8fe5c4ed8e25249e202e5da36
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35136
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During boot sequence sometime touchscreen reset keeps failing. Also, kernel
dmesg shows "dmesg:i2c_hid i2c-GDIX0000:00: failed to reset device" message.
This adds around 4 more seconds to the boot sequence. Setting the appropriate
delay of 120ms between enable and reset for Goodix Touchscreen helps to
synchronize and address this failure. This value is 120 ms as per Goodix Spec.
BUG=b:138413748
BRANCH=None
TEST=Built and tested on Hatch system
Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34626
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
postcar_commit_mtrrs() isn't used outside the postcar_loader
compilation unit. Make it static to reduce API surface area.
Additionally the return value was not being utilized. Modify
the return type to be void to align with the current usage.
Change-Id: If07f34467941d00de731489867e485cfff80ea63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is LVDS bridge, I assume this was lost while upstreaming
or converting boards to variants.
Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Device is present in devicetree but not included in
the build.
Change-Id: I8555d94902e94c623d8fbe6f1a4ffe7637988530
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Joel Kitching