Commit graph

199 commits

Author SHA1 Message Date
Naveen Manohar
3417ee9a3f mb/google/poppy/variants/nautilus: add SPK DMIC nhlt support
Nautilus board uses max989357a speaker codec and 4CH DMIC.
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.

BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on Speaker and captures on 4CH DMIC

Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-11 14:25:08 +00:00
Furquan Shaikh
903472c3c8 mb/google/poppy/variants/nami: Add support for nami board
This change adds variant nami derived from baseboard poppy.

BUG=b:70160119

Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 07:53:37 +00:00
Furquan Shaikh
48be29e392 mb/google/poppy: Add support for DDR4 memory
This change updates memory SPD handling code in baseboard poppy to
allow variants to define either LPDDR3 or DDR4 memory types. In
addition to that, it also updates the function to print SPD info
considering offsets that might be different across the two memory
types.

BUG=b:70188937

Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 07:53:20 +00:00
Furquan Shaikh
9bfd8141fb mb/google/poppy/variants/nautilus: Fix memory params
Until now, nautilus was using the DQ-DQS mappings provided by the
baseboard. However, based on schematics, these values are not
correct. This change adds DQ-DQS mapping tables for nautilus.

BUG=b:70188533

Change-Id: Ife6ba19b8fe8873ab8cca977ca8f34a4d86e8e6e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22706
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: shkim <sh_.kim@samsung.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 07:46:03 +00:00
Julius Werner
4ec3d9d69e boardid: Switch from Kconfig to weak functions
This patch switches the board_id and ram_code helper framework to use
weak functions rather than Kconfigs to determine whether the board
supplies these IDs. This cuts down on the amount of boilerplate Kconfigs
many boards have to set and also gives them more flexibility, such as
being able to determine at runtime whether a given ID is present.

Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22695
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07 01:19:27 +00:00
Furquan Shaikh
61847bf67f mb/google/poppy: Remove variant_cros_gpios from variants
Variants nautilus and soraka currently provide the exact same
definition for variant_cros_gpios as provided by the baseboard. This
change removes the function defintions from variants so that the weak
definition in baseboard can be used.

Change-Id: Ic88623f34039792f0f9fb46842b24e4f1290981b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22705
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06 18:24:18 +00:00
Furquan Shaikh
fc20ee43d7 mb/google/poppy: Add config option for camera ACPI support
This change adds a new config option VARIANT_HAS_CAMERA_ACPI to allow
variants to define ACPI tables for camera support. It also prevents
boards that do not need this from unnecessarily providing dummy files
for camera ACPI support.

Change-Id: I91f8e407e0f021071eeadbde8c2695e2a6d69e06
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06 18:24:13 +00:00
Furquan Shaikh
e7b0dcea7d mb/google/poppy: Change POPPY_USE_* to VARIANT_HAS_*
Change the prefix for TPM options from POPPY_USE_* to
VARIANT_HAS_*. This makes it clear that these are variant specific
options.

Change-Id: I6fd120a34a5b0c1f018164d5c2b60548da1d0f61
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06 18:24:06 +00:00
Furquan Shaikh
f3b97c5a70 mb/google/poppy: Introduce VARIANT_SPECIFIC_OPTIONS_*
In order to allow variants to select different Kconfig options, this
change adds VARIANT_SPECIFIC_OPTIONS_${VARIANT_NAME} which can be
selected by each variant in Kcnonfig.name.

Change-Id: I15db2fdac5c9e55f9698c8a0c083d6467afae245
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06 18:24:02 +00:00
Furquan Shaikh
7a835189b1 mb/google/poppy: Remove dynamic disabling of TPM
This change removes the dynamic disabling of TPM based on config
options. Poppy and its variants will have only one type of TPM
supported and so there is no need to update it dynamically.

Change-Id: Ie82825fcf7092e845583edaac9ba0d3fc9d1dd80
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06 18:23:59 +00:00
Furquan Shaikh
763b406107 mb/google/poppy/variants/soraka: Disable SPI TPM
Soraka is no longer using SPI TPM. This change disables GSPI0 in
device tree and updates gpio config accordingly.

Change-Id: Ia0554ce3a0d553631123cc2b23b6dc2f6f40a1a3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06 18:23:55 +00:00
Furquan Shaikh
bea9b473d1 mb/google/poppy: Disable SPI TPM
Mainboard poppy is no longer using SPI TPM. This change disables GSPI0 in
device tree and udpates gpio configuration accordingly.

Change-Id: I713e41c45e323bf13aa79412ec679c90121a52b2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06 18:23:51 +00:00
Furquan Shaikh
9d867af725 mb/google/poppy,nautilus,soraka: Disable PD on AC_PRESENT in deep Sx
This change updates device tree deep_sx_config to disable internal
pull-down on AC_PRESENT.

BUG=b:69983729

Change-Id: I041900a5262f8fd920856f126185329242a0639a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-05 18:07:14 +00:00
Furquan Shaikh
f4c91e6613 mb/google/poppy/variants/nautilus: Disable DPTF
This change disables DPTF until the support is properly added in
dptf.asl

Change-Id: I68f2442e00718a4edbb34661d31d3a415d41c29f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-30 20:31:43 +00:00
Subrata Banik
a6802ec30f mb/google/poppy/variants/soraka: Set PCH thermal trip point to 75 degreeC
PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.

BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.

Change-Id: I6246300a4376a0194950d4de277af040b10b6c1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-30 16:27:20 +00:00
Chris Wang
94dc50e810 mb/google/nautilus: add synaptics touch screen support
Add synaptics touchscreen in the device tree so that the correct ACPI
device is created.

BUG=b:66462881
BRANCH=master
TEST=compiled/verify the touchscreen works

Change-Id: I6e89a5db0e9f8ae777eed661f3bf89d653a937e6
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-30 16:19:08 +00:00
Furquan Shaikh
ab85c45326 mb/google/poppy/variants/nautilus: Disable camera devices
This change disables camera devices until camera support is properly
added for nautilus.

Change-Id: I7de37cbf9c32fa063f55a2e54986e33b66acfa3b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-29 00:11:34 +00:00
Furquan Shaikh
6d0c7bc77a mb/google/poppy: Add variant support for camera asl
This change adds infrastructure to allow variants to define their own
camera.asl file.
- Poppy and soraka use the one provided by baseboard.
- Dummy file is added for nautilus since it does not have camera
support enabled yet.

TEST=Verified that DSDT table remains the same with and without this
change.

Change-Id: I0f0b489e74739aa4708283d58d8b7626b77a89a3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-29 00:11:26 +00:00
Chris Wang
5220e5fba6 mb/google/poppy/variants/nautilus: set I2C speed to 400KHz
Add "speed_config" for each I2C port configuration to set speed to
400KHz.

BRANCH=master
BUG=none
TEST=compiled/verified

Change-Id: Icb48733b87cefc92577547b1eab661a8cbb12be6
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-28 19:11:04 +00:00
Chris Wang
51de1802f3 mb/google/poppy/variants/nautilus: Change IA/GT/SA slow slew rate settings
Change IA/GT/SA slow slew rate settings.
System's audible noise will be reduced with them.

- Slow slew rate for IA/GT/SA : fast/16
- Fast PKG C-state ramp for IA/GT/SA: disabled

BRANCH=master
BUG=none
TEST=compiled/verified

Change-Id: Ibf11aba7bafb3b02c510905d7d904507eee6394b
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-28 19:10:55 +00:00
Divya Chellap
b96712dfd9 mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table
On shutdown, Soraka enters Deep S5 and not S5 state. Setting
pad reset config of a gpio to RSMRST will not preserve
the gpio config across deepSx and the gpio should be configured again.
The WLAN_PE_RST signal should be brought up early in the bootflow
for giving the device enough time to initialized before PCIE init in FSP-S.
Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in
early pad configuration in bootblock also.

BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot.

Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-11-28 05:37:16 +00:00
Chris Wang
ad07dc84a4 mb/google/poppy/variants/nautilus: correct the SIO_EC_ENABLE_P2SK typo
correct the typo from SIO_EC_ENABLE_P2SK to SIO_EC_ENABLE_PS2K.

BRANCH=master
BUG=b:66462881
TEST=compiled/boot to ChromeOS.

Change-Id: Iaded458e202bc975c73cd295f7b363e2c9bfa861
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 01:01:30 +00:00
Chris Wang
0e1d022e26 mb/google/poppy/variants/nautilus: remove ALS for nautilus
nautilus doesn't support ALS. remove the definition from ec.h.

BRANCH=master
BUG=b:66462881
TEST=compiled/boot to ChromeOS.

Change-Id: Ib357328799015f78b18cd260db221e524e98cef7
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 01:01:24 +00:00
Furquan Shaikh
d37107e130 mb/google/{poppy,nautilus,soraka}: Disable deep S3
Poppy and variants won't be using deep S3. This change disables deep
S3 option in devicetree.

BUG=b:69053636

Change-Id: I5fb4a6a0e4216a3648b5ed888f6dc6618f1a9fc4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22378
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 19:02:03 +00:00
Naveen Manohar
5bcb23ebbb mb/google/poppy/variants/nautilus: Enable Dialog DA7219 support
Enable Dialog DA7219 codec i2c device and add required SSDT parameters

BUG=b:68686020
TEST=With req'd driver support in kernel v4.4 verify audio on headset

Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar@intel.com>
Reviewed-on: https://review.coreboot.org/22264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07 23:37:38 +00:00
Naveen Manohar
351059a0b4 mb/google/poppy/variants/nautilus: add nhlt support
Nautilus board uses Dialog da7219 headset codec,
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.
Removes unwanted DMIC blob pick for nautilus

BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on headset and recording on headset mic

Change-Id: I104889f54da1de38854bcb72aabbc88b739d6c09
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07 23:37:19 +00:00
Divya Chellap
8fcd559ef9 soraka: update pad reset config of WLAN_PE_RST to RSMRST
In skylake based platforms, setting GPIO pad reset config
to DEEP will reset the gpio configuration across warm reset,
set it to RSMRST to preserve the configuration across warm resets.
Also, moving the configuration from early to late as appropriate.

BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S3, DeepS3, S0ix and warm/cold reboot.

Change-Id: I38940b7c7d71e60bf0e51d6978a00be148ad61bc
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03 22:00:20 +00:00
Chris Wang
36e40e40a7 google/nautilus: enable elan touchpad support
add elan touchpad in devicetree.

BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot

Change-Id: I30e6797ef06351690ff0b5c78ea76918547167a7
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03 05:32:41 +00:00
Chris Wang
cb25974f5a google/nautilus: Update GPIO table
Update GPIO settings to meet nautilus's schematic design.

BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot

Change-Id: I11930df62130431764702371a3ba84949a65ba30
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-03 05:32:33 +00:00
Chris Wang
cf24da4c53 google/nautilus: add spd data by ram id
update with nautilus memory spds.

RAM_ID = 0 => K4E8E324EB-EGCF
RAM_ID = 1 => K4E6E304EB-EGCF
RAM_ID = 2 => K4EBE304EB-EGCG

BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot

Change-Id: I29d8a76b170aee64bb0125276df0e4709012daba
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-03 05:32:27 +00:00
Furquan Shaikh
4854761ba4 mb/google/poppy: Log EC events during S0ix resume
This change adds support for logging EC events during S0ix resume.

BUG=b:67874513
TEST=Verified that EC events are correctly logged during S0ix resume:
284 | 2017-10-16 20:45:12 | S0ix Enter
285 | 2017-10-16 20:45:16 | S0ix Exit
286 | 2017-10-16 20:45:16 | Wake Source | Power Button | 0
287 | 2017-10-16 20:45:16 | EC Event | Power Button
288 | 2017-10-16 20:45:35 | S0ix Enter
289 | 2017-10-16 20:45:40 | S0ix Exit
290 | 2017-10-16 20:45:40 | Wake Source | GPIO | 112
291 | 2017-10-16 20:45:40 | EC Event | Lid Open
292 | 2017-10-16 20:50:51 | S0ix Enter
293 | 2017-10-16 20:50:59 | S0ix Exit
294 | 2017-10-16 20:50:59 | Wake Source | GPIO | 112
295 | 2017-10-16 20:50:59 | EC Event | Mode change

Change-Id: I9f6dcb8852d94ebf90bb5b63a17fde524d58d49f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:56 +00:00
Chris Wang
5547c371c1 mb/google/poppy/variants/nautilus: add nautilus board
Create Nautilus board which derives from Poppy, a KBL reference board.

BRANCH=master
BUG=b:66462881
TEST=Build (as initial setup)

Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-10 13:48:14 +00:00
Furquan Shaikh
219ebb969b skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")

This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.

BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.

Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-09 20:20:40 +00:00
Furquan Shaikh
ef1a5ede6c mb/google/poppy/variants/soraka: Add 10ms reset delay for WCOM device
Change 868b3761 (mainboard/google/soraka: Reduce Wacom resume time)
removed the delay after taking device out of reset since it seemed
unnecessary in system resume case (because there is enough time after
taking device out of reset and before communication with device
starts).

However, without the delay, kernel driver runs into issue while
talking to the device during boot-up and runtime
suspend/resume. (Observed this error in dmesg: "i2c_hid
i2c-WCOMCOHO:00: failed to change power setting."). Thus, add 10ms
delay after taking device out of reset. Verified on multiple Soraka
system that with 10ms delay, kernel driver does not run into any issue
talking to the WCOM device during boot-up, runtime suspend/resume and
system suspend/resume.

BUG=b:65358919
TEST=No more errors talking to WCOM device in kernel dmesg.

Change-Id: I485b753cbae4b653e74337e048aea4d26ffdbb81
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-08 19:38:51 +00:00
Furquan Shaikh
2749c52080 ec/google/chromeec: Add library function google_chromeec_events_init
mainboard_ec_init implemented by all x86-based mainboards using
chromeec performed similar tasks for initializing and recording ec
events. Instead of duplicating this code across multiple boards,
provide a library function google_chromeec_events_init that can be
called by mainboard with appropriate inputs to perform the required
actions.

This change also adds a new structure google_chromeec_event_info to
allow mainboards to provide information required by the library
function to handle different event masks.

Also, google_chromeec_log_device_events and google_chromeec_log_events
no longer need to be exported.

Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-08 19:38:28 +00:00
Rajneesh Bhardwaj
868b3761c7 mainboard/google/soraka: Reduce Wacom resume time
Currently the WCOMCOHO registers a reset delay of 110ms to execute their
_ON_ asl power on method. This seems to be correct as per WACOM product
design specifications but it introduces an unwanted delay in overall system
resume time. This delay should be removed from ACPI critical path since the
entire kernel resume gets blocked on this sleep call unless this is over. In
the kernel I2C communication with WACOM driver starts with the resume
callbacks of I2C HID driver which gets triggered after display is completely
resumed. The display resume process takes at least 230ms so it's safe to
reduce the delay from coreboot and unblock the critical ACPI path.

BUG=b:65358919
BRANCH=None
TEST=manual testing on Soraka board to ensure that touchscreen works at boot
and after suspend/resume. Also verify that the overall S3 resume time is
reduced by 110ms.

Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/21692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-03 20:25:39 +00:00
V Sowmya
c6c4217968 mb/google/poppy: Modify HID and add device tree support for VCM device
Modify the HID to align with ACPI spec. Add the DSD object
for the device tree support in kernel which will probe
the DW9714 device based on the HID.

BUG=b:65423422
CQ-DEPEND=CL:654383
BRANCH=none
TEST=Build and boot soraka. Verified that the VCM device
probe is successful.

Change-Id: Ic4a59dd2027267fbd3837fcd7dbc00551a69f7d6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-27 16:43:22 +00:00
Furquan Shaikh
a4ab665a55 mb/google/*: Use newly added Chrome EC boardid function
Instead of duplicating code across multiple mainboards, use newly
added helper function to read boardid from Chrome EC.

Change-Id: I1671c0a0b87d0c4c45da5340e8f17a4a798317ca
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 15:20:39 +00:00
Furquan Shaikh
8f08f5f5c7 soraka: Ensure I2C5 frequency is less than 400kHz
Update I2C5 bus parameters to obtain clock frequency <400kHz.

BUG=b:65062416
TEST=Verified using an oscilloscope that I2C5 bus frequency
in factory is ~397kHz.

Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 02:20:48 +00:00
Rizwan Qureshi
09703f6494 mb/google/{poppy,soraka}: Enable LTR for Root port
Enable LTR for Root port 0, where wifi card is connected.

BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
     by AER driver for root port 0.

Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-21 03:14:54 +00:00
V Sowmya
79f8f22499 mb/google/poppy: Add lens_focus property for OV13858 camera module
Add lens_focus property with reference to VCM device for OV13858
camera module to register the corresponding v4l2 sub-device
asynchronously.

BUG=b:64133998
BRANCH=none
TEST=Build and boot soraka. Dump DSDT and verified that it has the
required entries and verified the camera functionality.

Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-16 22:40:45 +00:00
Rizwan Qureshi
ea4649f65f mb/google/poppy: enable AER for PCIe root port 0
Enable PCIe Advanced Error Reporting for PCIe root port 0.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21425
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-15 18:20:42 +00:00
Wisley Chen
f7d0f02b36 mb/google/soraka: Update DPTF parameters
Cloned from baseboard/dptf.asl and update the parameters for soraka.

1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
   CPU: passive point:85, critial point:100
   TSR0: passive point:55, critial point:65
   TSR1: passive point:58, critial point:70
   TSR2: passive point:60, critial point:75
   TSR3: passive point:60, critial point:75

2. Set PL1 Max to 7W, and PL1 Min 4.5W

3. Change sampling period of thermal relationship table (TRT) setting
   CPU: 5 seconds
   TSR0: 30 seconds
   TSR1: 30 seconds
   TSR2: 8 seconds
   TSR3: 8 Seconds

BUG=b:65467566
TEST=build, boot on soraka, and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>

Change-Id: I6af93fa358a037df2088213ee4df5e2cfd047590
Reviewed-on: https://review.coreboot.org/21453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13 19:31:26 +00:00
Wisley Chen
1fbc1927b1 mb/google/soraka: Fine-tune USB 2.0 port4
Fine tune usb 2.0 strength for port 4 to pass eye diagram.

BUG=b:65306272
TEST=build on soraka, measure usb2.0 eye diagram, and result is pass.

Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13 19:10:10 +00:00
Harsha Priya
130b4a29eb mb/google/{poppy,soraka,eve}: Add imon and vmon params for Max98927 codec
This patch adds imon and vmon slot numbers for Maxim 98927 driver.
These values are used to confiure IV feedback for audio playback on speakers.

BUG=b:36724448
TEST=After boot, the register dump for  Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.

Change-Id: I4382da4f984507d147751c168e8177b58c88a70f
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06 19:00:52 +00:00
Rizwan Qureshi
8688536ca2 mb/google/soraka: enable AER for PCIe root port 0
Enable PCIe Advanced Error Reporting for PCIe root port 0.

Change-Id: I76742801e84449d0910ddadf31d39597df3263b9
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 16:40:01 +00:00
Naresh G Solanki
cdc9af9ebd mb/google/soraka: Camera PMIC run time power control
Currently PMIC (tps68470) is in active state even when cameras are not
in use. PMIC is put into SLEEP mode only when entering S3 via
smihandler.

With this change PMIC will be put into SLEEP mode as soon as sensors &
VCM voltage outputs are turned off. This will allow run time power
saving when camera is not in use.

PMIC will be reset in first boot & across S3 & S0ix cycles.

Also, remove the smi handler for PMIC power management & handle it as
part of sensor and VCM ACPI PowerResource.

BUG=b:63903239
TEST= Build for Soraka. Check Camera probe, Capture image across
S3 & S0ix cycles.
Also checked the following & found no regression:
1. Typical camera use cases
2. Stability tests related to camera
3. Reliability tests related to camera
4. PnP tests related to camera
5. Latency related tests with camera

Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-05 23:28:10 +00:00
Wisley Chen
d9ccb4e5f8 mainboard/google/soraka: Remove wacom digitizer
We have no wacom digitizer on I2C#3, so remove it.

TEST=build and boot on soraka.

Change-Id: I3f5a1b9ece6fc9a9443477c7a7aa77dbcdf6a703
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21309
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-02 15:30:18 +00:00
Furquan Shaikh
3ed5969661 mainboard/google/soraka: Add stop gpio control to touchscreen device
BUG=b:64987428
TEST=Verified that touchscreen works on boot-up and after
suspend/resume. No power leakage via stop gpio in suspended state.

Change-Id: Ia260eb444081dbe1646c90e82c2725661e7306bc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-08-30 16:40:17 +00:00
Furquan Shaikh
a62520bc79 mainboard/google/soraka: Remove Atmel Touchscreen
We no longer use this touchscreen device, so get rid of it.

BUG=b:64987428

Change-Id: I67af787d231317a80998fb483eed5674de19aeb4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30 16:16:19 +00:00
Furquan Shaikh
eeab2710ef mainboard/google/soraka: Tune I2C params (hcnt, lcnt, hold time)
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the
frequency does not exceed 400KHz.

BUG=b:35948024
TEST=Verified for 25 iterations that the frequency on each bus ranges
<= 400KHz.

I2C0: 393 - 397
I2C1: 393 - 400
I2C2: 392 - 400
I2C4: 392 - 400
I2C5: 392 - 400

Change-Id: I3e12c75eb7e82a83aa6a6bcfcc11c12f83f2d3d4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-08-29 20:24:18 +00:00
Furquan Shaikh
c3e4f6344d mainboard/google/poppy: Tune I2C params (hcnt, lcnt, hold time)
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the
frequency does not exceed 400KHz.

BUG=b:35948024
TEST=Verified for 25 iterations that the frequency on each bus ranges
<= 400KHz.

I2C0: 375 - 400
I2C1: 377 - 400
I2C2: 377 - 400
I2C4: 375 - 397
I2C5: 375 - 397

Change-Id: Ie30e1a12b66c4660b648a585c4dfd66faf004129
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21208
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-28 01:19:36 +00:00
Subrata Banik
c204aaa23b soc/intel/skylake: Add LPC and SPI lock down config option
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.

Remove EISS bit programming as well.

TEST=Build and boot Eve and Poppy.

Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25 17:58:08 +00:00
Furquan Shaikh
3f09b0ffef mainboard/google/poppy: Update VR config settings
Update Psi2Threshold, IccMax, ACLoadline and DCLoadline VR config
settings to match that of soraka.

BUG=b:62063434
BRANCH=None
TEST=Build and boot poppy.

Change-Id: I2c294eb14257d319e1e2d4d1e529481d921ba6f8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21105
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-08-21 04:40:02 +00:00
Furquan Shaikh
b15769186c mainboard/google/poppy: Remove MPS IMPV8 workaround
Poppy uses MPS2949 IMVP8 controller and does not need the VR
workaround similar to Eve.

Change-Id: If6fb1890e024e1488d278bbe0a71a1a63ee321af
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21104
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-08-21 04:39:57 +00:00
V Sowmya
e6aab7f120 mainboard/google/poppy: Add ACPI objects for NVMEM device GT24C16S and CAT24C16
The Giantec semiconductor GT24C16S and ON semiconductor CAT24C16
are the industrial standard electrically erasable programmable
read only memory (EEPROM's) and this patch adds ACPI objects
and power resources for NVMEM device.

Update DOVD method to set sensor IO LDO voltage and remove repetitive
code from OVFI, VCMP and NVMP power resources.

BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Read the NVMEM content via sysfs interface.

Change-Id: If49ed33b7e1de1eabf317b31ceed8568dfca0aae
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-17 16:37:15 +00:00
Sumeet Pawnikar
b4411d3c9e mb/google/poppy: Update PL2 settings
Update PL2 override setting to 15W as per KBL Power Arch Guide.

Change-Id: I4a6f875f8c3bdb012d6ff97c1429f32db5210893
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/20943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-11 19:10:02 +00:00
V Sowmya
1cda0d0e50 mainboard/google/poppy: Decrease link-frequencies for OV13858 and OV5670
Decrease the link-frequencies as recommended by Omnivision for OV13858
and OV5670 camera sensors.

BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.

Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2017-08-04 15:25:49 +00:00
Furquan Shaikh
0767f89be4 mainboard/google/soraka: Configure GPP_B8 in bootblock
GPP_B8 acts as input to the inverter whose output controls PERST#
signal to wifi module. Out of reset, GPP_B8 is configured as
input by default. Since there is no external pull-down on it, this
line is floating and results in PERST# being asserted until ramstage
where the GPIO was originally configured. Because of this the wifi
chip is not ready during the PCIe initialization step. Move the
configuration of GPP_B8 to bootblock so that wifi device is taken out
of reset as early as possible.

BUG=b:64181150,b:62726961
TEST=Verified with warm reboot and suspend-resume stress test that
wifi is still functional.

Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04 15:25:27 +00:00
Furquan Shaikh
5a89b40b15 mainboard/google/soraka: Add gpio.c to bootblock
Add gpio.c to bootblock so that the variant early_gpio_table can be
used for configuration in bootblock.

BUG=b:64181150,b:62726961

Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04 15:25:17 +00:00
Rizwan Qureshi
ca74434a8a mb/google/soraka: configure GPP_B8 to control WLAN_PE_RST
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8.
Configure GPP_B8 to drive low.

TEST=Wifi card is detected and connect to an AP.

Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-28 06:45:02 +00:00
V Sowmya
01ea8f1fcc mainboard/google/poppy: Configure GPIO.1 and GPIO.2 for daisy chain mode
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively
for TPS68470 PMIC in daisy chain mode.
* GPIO.1: Sensor SDA in daisy chain mode.
* GPIO.2: Sensor SCL in daisy chain mode.

BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.

Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27 00:32:26 +00:00
Wisley Chen
fa1d383f93 mainboard/google/soraka: pull high TOUCHSCREEN_STOP_L pin
After updating to Wacom Firmware version 501, touchscreen can't work.
Wacom FW (ver. 501) enables STOP function.
STOP Pin:
  High: Normal Operation
  Low: Stop Scanning
So pull TOUCHSCREEN_STOP_L high

BUG=b:37007801, b:37265219
BRANCH=none
TEST=manual testing on Soraka board and touchscreen works at boot
and after suspend/resume.

Change-Id: I8a2bdce1554fd99dea30cf91fa48d0529f40b7b0
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/20664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-24 06:07:04 +00:00
Rajat Jain
2671afcbbc mainboard/google/{poppy,soraka}: Enable S0ix
Enable S0ix for poppy and soraka in their device trees respectively.

BUG=b:36630881
BRANCH=none
TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations).

Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-23 04:01:04 +00:00
Furquan Shaikh
4a1d450d07 mainboard/google/poppy/variants/soraka: Update GPP_{D1,D2,B7} config
GPP_B7, GPP_D1 and GPP_D2 are not used going forward. Mark them as NC
in gpio table.

BUG=b:62322846,b:62240755

Change-Id: I7aee08314e6ce96d5913ae315bf75f5c04ab7370
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-22 05:25:01 +00:00
Furquan Shaikh
907a0cfc30 mainboard/google/poppy/variants/soraka: Define separate gpio tables
Now that soraka is starting to deviate from the baseboard w.r.t. gpio
settings, make a new copy of gpio table before we make any
variant-specific changes in it.

BUG=b:62240755,b:62322846
BRANCH=None
TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio
configuration before and after this change remains same.

Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-22 05:24:57 +00:00
Wisley Chen
a80a0eba11 mainboard/google/soraka: add wacom touchscreen support
Add wacom touchscreen support.

BUG=b:37007801, b:37265219
BRANCH=None
TEST=manual testing on Soraka board to ensue that touchscreen works
at boot and after suspend/resume.

Change-Id: I0fbae4782c6442149cda57d23c61ed87546621bb
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/20476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-13 06:38:19 +00:00
Naresh G Solanki
3d38448619 mb/google/soraka: Do not reset PMIC during sleep
1. Due to reset signal, PMIC loses its internal register state. This
   causes PMIC to be in improper state after sleep.
2. The intent of reset signal is to reset internal state of PMIC (which
   happens once during power on), hence avoid asserting reset signal
   when not needed.
3. As per PMIC (TPS68470) datasheet, device can be kept in SLEEP mode
   when not in use to save max possible power.

To fix the same, do not reset PMIC while entering sleep.

By keeping PMIC in SLEEP mode, Power consumption is < 1uW (Typ) upto
3.63uW (Max). Refs: TPS68470 datasheet.
Measured value: 0.66uW

TEST= Build the firmware for Soraka & boot to OS. Do S3 resume & check
whether PMIC internal registers state are preserved.

Change-Id: I93ce4d76b0376b64ae6d1067aca0fd7467af3582
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12 05:52:33 +00:00
Duncan Laurie
ec4a0b3b5f mainboards: Remove unused EC event for thermal overload
The Chrome EC event for "thermal overload" was never implemented and
is being repurposed as the EC event mask is out of free bits.

Remove this from the boards that were enabling it.

BUG=b:36024430
TEST=build coreboot for affected boards

Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01 02:47:30 +00:00
Rajneesh Bhardwaj
4692e2fc95 mainboard/google/soraka: Update VR config settings
Update Psi2Threshold, IccMax, AcLoadline, DcLoadline
VR config settings as per board design.

BUG=b:62063434
BRANCH=none
TEST=Build and boot soraka.

Change-Id: I254bbb88b82ddf278f0ec71bc98873df1d5e0d27
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: G Naveen <naveen.g@intel.com>
Reviewed-on: https://review.coreboot.org/20309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-27 20:46:48 +00:00
Rajneesh Bhardwaj
b3f2c9ac59 mb/google/soraka: Remove MPS IMVP8 workaround
Soraka uses MPS2949 IMVP8 controller and does not need the VR
workaroud similar to Eve.

BUG=None
TEST=Build & boot on soraka. Ensure IMVP8 controller goes to low power
mode in S3 and S0ix by measuring power.

Change-Id: Ib98bb709ecc9e362a5cef437e7319e41f398a73b
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/20255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27 20:46:40 +00:00
V Sowmya
a02b65c40b mainboard/google/poppy: Update world facing camera sensor
Update the world facing camera sensor to OV13858 and also
add delay of 5ms after xshutdown rising which indicates system
ready status.

BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successfull.

Change-Id: I0cd535e6568f104ffaa1092a13667def646df0eb
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-06-27 16:04:39 +00:00
V Sowmya
c8aa2d81f6 mainboard/google/poppy: Add clock frequency for camera sensors
Add clock frequency property into _DSD ACPI object and set it
to 19.2MHz for camera sensors. Upstream camera kernel has added
a check for clock frequency in sensor probe function and without
this property sensor probe fails.

BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successfull.

Change-Id: I147b3c932a33ae034868f7f9b616500d24ca71e3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20294
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-06-27 16:04:14 +00:00
V Sowmya
eacda2eb83 mb/google/poppy: Add camera devices power sequencing through ACPI power resources
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC,
	* TI_PMIC_POWER_OPREGION
	* TI_PMIC_VR_VAL_OPREGION
	* TI_PMIC_CLK_OPREGION
	* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
	* OVTH for CAM0
	* OVFI for CAM1
	* VCMP for VCM
* Implement _ON and _OFF methods for sensor and VCM module's power on
and power off sequences.

BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.

Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-20 05:08:41 +02:00
V Sowmya
ba03d8de63 mb/google/poppy: Configure ports and endpoints for sensor and CIO2 devices
Bind the camera sensor and CIO2 devices through the ports and endpoints
configuration available in _DSD ACPI object.

* Port represents an interface in a device.
* Endpoint represents a connection to that interface.

BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.

Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-20 05:08:30 +02:00
V Sowmya
23e88910cf mb/google/poppy: Add MIPI camera support.
This patch adds mipi_camera.asl,

* Add TPS68470 PMIC related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.

BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.

Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19 20:51:28 +02:00
V Sowmya
5dc153885b mainboard/google/{poppy,soraka}: Remove MIPI camera support from devicetree.cb
Remove MIPI camera related register entries from devicetree.cb.

BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy and soraka.

Change-Id: Ic6a6a98d4c8ed6cba760eae5fd87bc2a3f15d7d2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/19619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19 20:51:17 +02:00
Naresh G Solanki
1827ec1f4e mb/google/poppy: Add option to disable TPM
Disable TPM when VBOOT_MOCK_SECDATA is enabled.

BUG=None
BRANCH=None
TEST= Build image using USE="mocktpm" emerge-poppy coreboot depthcharge
vboot_reference chromeos-bootimage . Verify boot is successful with mock
tpm.

Change-Id: Iee527ed17cffb7d25d9089e48a194d99ac8c3cd1
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19 20:44:45 +02:00
Furquan Shaikh
296c79c9be mainboard/google/{poppy,soraka}: Disable unused GSPI1 interface
TEST=Verified that board still boots to OS without any error.

Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-14 20:29:12 +02:00
Furquan Shaikh
dec6d4e8c7 mainboard/google/{poppy,soraka}: Enable generation of SPI TPM ACPI node
Now that we dynamically disable TPM interface based on config options,
add support for generation of SPI TPM ACPI node if SPI TPM is used.

Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-14 20:20:28 +02:00
Furquan Shaikh
b2f423578e mainboard/google/poppy: Disable unused TPM interface dynamically
Based on the config options selected, decide at runtime which TPM
interface should be disabled so that ACPI tables are not generated for
that interface.

TEST=Verified that unused interface does not show up in ACPI tables.

Change-Id: Iee8f49e484ed024c549f60c88d874c08873b75cb
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20141
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-14 20:20:21 +02:00
Naresh G Solanki
5e10422df2 mb/google/soraka: Update UF camera i2c address
Update user facing camera i2c address to 0x36.

BUG=None
TEST=Build & boot on soraka. Make sure user facing camera is detected.

Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-06-09 16:15:07 +02:00
Furquan Shaikh
5677e7da4b mainboard/google/poppy: Add support for ELAN device
Add support for ELAN 5515 device.

BUG=b:62331218

Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20040
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-07 22:49:28 +02:00
Naresh G Solanki
e7cb29493d mb/google/poppy: Update camera sensor
Update camera sensor detail to OV 13858
Also update i2c address of OV5670

BUG=None
TEST= Build & boot to ChromeOS. Check for both the camera detection.

Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-04 04:05:34 +02:00
Furquan Shaikh
1581543185 mainboard/google/poppy: Enable H1 I2C TPM
Enable H1 I2C TPM in Kconfig and devicetree for poppy.

CQ-DEPEND=CL:513513,CL:*381534
BUG=b:36265511
BRANCH=None
TEST=Compiles successfully.

Change-Id: I4c6c94fa05abf9f5374505ded5956e879ac79726
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-01 17:58:34 +02:00
Furquan Shaikh
3178bdc345 mainboard/google/poppy: Power down camera rails when suspending
BUG=b:62147763

Change-Id: Iba88fed972b847448e01fcfca8c7129d950244c2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-31 19:55:23 +02:00
Furquan Shaikh
73108ded48 mainboard/google/poppy: Add PowerResource for touchscreen device
1. Do not enable touchscreen device by default in gpio configuration.
2. Select use of PowerResource for touchscreen device in devicetree so
that the ACPI subsystem can take care of powering on/off the
device. When system enters suspend, touchscreen device is powered off
and on resume, it is powered back on.

BUG=b:62028489
TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on
poppy.

Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19829
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-26 04:41:53 +02:00
Naresh G Solanki
b25b2329a9 mb/google/soraka: Update camera sensor for soraka
Soraka uses OV 13858 sensor. Hence update the same.

Change-Id: I4dd39a25da47e379cca3f8748250b3ce1ff61e50
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/19639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-24 16:29:14 +02:00
Naresh G Solanki
1d407cceaf mb/google/poppy: Update SPD data
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD),
it displays wrong part number during boot in coreboot logs.

So correct part number info within the SPD.

TEST= Build for Soraka & make sure part number is rightly printed.

Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/19692
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-24 08:02:19 +02:00
Furquan Shaikh
365d97e938 mainboard/google/poppy/variants/soraka: Add SPD for K3QFAFA0CM-AGCF
BUG=b:37712455

Change-Id: Ia3d13ac7c18be8fa92603b6501a2e5df476adcf0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19766
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19 21:24:27 +02:00
Furquan Shaikh
77be7339cd mainboard/google/poppy: Fix SPD for micron MT52L256M64D2PP-107
Fix SPD as per the vendor-provided data.

BUG=b:37712790

Change-Id: Ib87c316479f4a05e64ca4acb540d7aacfa7338e9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-19 21:24:15 +02:00
Furquan Shaikh
8888072230 mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM
1. Add a separate devicetree file for soraka variant and add H1 node.
2. Enable H1 TPM for soraka.

BUG=b:36265511

Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19519
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-05-17 06:30:06 +02:00
Furquan Shaikh
d271afc0a7 mainboard/google/poppy: Correct I2C bus number for TPM
TPM is on I2C bus 1. Fix that.

BUG=b:36265511

Change-Id: I7fb696ca7281a0c099dd325d794dd4551cf20a53
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19710
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-17 06:29:56 +02:00
Sumeet Pawnikar
c9026b2945 mb/google/poppy: Add eMMC as thermal sensor
This patch adds the eMMC as one of the thermal sensor under DPTF.
Also, updates few comments for better interpretation and mapping.

BUG=None
BRANCH=None
TEST=Built for poppy.

Change-Id: I6d05bb7a2f857dc5bc98227c8327b2ff1bd5b913
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/19524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-05-05 23:20:48 +02:00
Furquan Shaikh
730fc6c7d8 mainboard/google/poppy: Enable MODE_CHANGE event in SCI_MASK
This is required to ensure that SCI is generated whenever a host event
is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs,
eSPI SCI is generated which results in kernel handler reading host
event from the EC and thus causes the wake pin to be de-asserted.

BUG=b:37223093
TEST=Verified that wake from mode change event works fine in suspend
mode and there is no interrupt storm for GPE SCI after resume.

Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jenny Tc <jenny.tc@intel.com>
2017-05-05 18:43:01 +02:00
Furquan Shaikh
553f7fb27c mainboard/google/poppy: Add support for cr50 I2C TPM
1. Add support for using cr50 I2C TPM on poppy. This will not be
enabled until the next build.
2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding
Kconfig options are set.

BUG=b:36265511
TEST=Verified on a reworked board that I2C TPM communication works
fine.

Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03 00:29:31 +02:00
Furquan Shaikh
a118c2edcc mainboard/google/poppy: Update GPIO table for next build
Update GPIO table to match the schematics for next build.

Change-Id: I949a14bfaa7972f2257a0b11ee81dcb0771e2f7f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-05-03 00:29:15 +02:00
Furquan Shaikh
8d70b96937 mainboard/google/soraka: Add support for memory configs 1,2,7 and 8
BUG=b:37712455

Change-Id: I3209aaef774712edab5e9f656ee84bfb6917b1c1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19472
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-28 21:58:13 +02:00
Furquan Shaikh
bb70022e28 mainboard/google/poppy: Add SPDs for memory config 1 and 2
BUG=b:37712790

Change-Id: I7764b4ec55b0beea82eeb6c379ef38ceeb1fb04e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28 21:57:57 +02:00
Furquan Shaikh
8ac19c8629 mainboard/google/poppy: Enable separate MRC cache for recovery mode
Enable separate MRC cache for recovery mode. This requires change in
flash layout to accomodate another region for RECOVERY_MRC_CACHE.

BUG=b:37682566
TEST=Verified following scenarios:
1. Boot into recovery does not destroy normal mode MRC cache.
2. Once recovery MRC cache is populated, all future boots in recovery
mode re-use data from the cache.
3. Forcing recovery mode to retrain memory causes normal mode to retrain
memory as well.

Change-Id: I4c748a316436001c5a33754084ab4a74243e21df
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19457
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28 21:57:37 +02:00