boards using ck804_early_setup.c that select CK804_USE_NIC.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Additionally, make the second SMBus more accessible in romstage.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
FADT revision inconsistent with length.
Revision: 0x1
Length: 0xf4
Expected Length: 0x74
Change the FADT revision from 1 to 3 to match its length and prevent the Windows checked build assert.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges
- drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
at the same time let the user specify sources instead
of object files:
- objs becomes ramstage-srcs
- initobjs becomes romstage-srcs
- driver becomes driver-srcs
- smmobj becomes smm-srcs
The user servicable parts are named accordingly:
ramstage-y, romstage-y, driver-y, smm-y
Also, the object file names are properly renamed now, using
.ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.
Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
easily fit in the build system and aren't useful anyway.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coreystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
We don't surround the <usbdebug.h> #include with those checks in other
places either. Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
is selected that uses a chipset which actually has that functionality _and_
we have code to initialize the Debug Port in coreboot (for that chipset).
Also, remove the duplicate list of PCI IDs and just link to the wiki page at:
http://www.coreboot.org/EHCI_Debug_Port
The list is now less useful in the kconfig help as this option will only
appear for those boards where it's actually supported.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of
hardcoding their values.
- SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE.
- ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC.
- s/uint32_t/u32/.
- Cosmetics, whitespace, coding style fixes and added code comments.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to make sure MMCONF is set up before use. Otherwise, PCI config
accesses run before init_cpus() will be lost if MMCONF is enabled
(unless explicitly done as port-based accesses).
This obsoletes removal of RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78) in
mcp55_early_setup, so reinsert.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
fixes a few alignment wrinkles and sets up and registers the MMCONF area
for AMD Fam10h CPUs (where selected by mainboard configuration). It
removes a bit of code that proved troublesome in MMCONF setups from
mcp55_early_setup_car.c, as per earlier discussion.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fix the ctrl_devport_conf_clear to clear the enable bit.
A simplification:
Dynamically enable ck804s that are found instead of relying on #defines.
Removing an Opteron changes the number of ck804s that are present.
Simple changes to make it easier to compare the factory BIOS with Coreboot when
using SerialICE for boards with the Nvidia ck804 chipset:
If the mask is zero, don't read the value, just write the new value over it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
there is no free list.
Converting resource arrays to lists reduced the size of each device
struct from 1092 to 228 bytes.
Converting link arrays to lists reduced the size of each device struct
from 228 to 68 bytes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coreboot is direct. This patch does it.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning.
The 1000 ways of how the AMD code waits for the cores to be started up
are a real pain for the brain.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- cleanup reset
- some minor warning fixes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Only some assembler files still have \r\n ... Can we move that part to C
completely?
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Some other random warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(chipset_bootblock_inc and chipset_bootblock_lds) instead of using
chipset specific rules for "bigbootblock" in the generic i386 Makefile.
It also adds rules for the romstraps of
* southbridge/nvidia/ck804
* southbridge/sis/sis966
* northbridge/via/vx800
for the benefit of both image layouts.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- drop include/part and move files to include/
- get rid lots of warnings
- make resource allocator happy with w83627thg
- trivial cbmem resume fix
- fix payload and log level settings in abuild
- fix kontron mptable for virtual wire mode
- drop some dead includes and dead code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Consistently use the same wording and formatting for all license headers.
- Remove useless whitespace, add missing whitespace, fix indentation.
- Add missing "This file is part of the coreboot project." where needed.
- Change "(C) Copyright John Doe" to "Copyright (C) John Doe" for consistency.
- Add some missing "(C)" strings and copyright years where needed.
- Move random comments and file descriptions out of the license header.
- Drop incorrect file descriptions completely (e.g. lpc47m10x/Makefile.inc).
There should be no changes in _content_ of the license headers, if you spot
such changes that's a bug, please report!
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
from mainboards.
Some adaptations were necessary after the IOAPIC cleanup,
so this should fix the build.
Fix intel/d945gclf build, which was missing some ACPI component.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
of components. This patch is a rewrite of the generic IOAPIC setup code.
Additionally it drops the other 12 instances of IOAPIC setup code and
makes the components use the generic code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)
read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.
This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch also aligns the configuration of a couple of
boards more closely to what newconfig does.
Also, the romstrap inc/lds files are declared in the
Makefiles of the southbridges they belong to, instead of
some global file.
AMD CPUs have their own timer functions, so disable UDELAY_IO
for them and set HAVE_INIT_TIMER as appropriate, same for
emulation/qemu-x86.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative)
where necessary (if romstraps get in the way).
For Kconfig, the special case is set per southbridge (as these define the necessity for this
workaround), for newconfig it's added to each single board.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
now handled more generically using CBFS.
Simplify the option ROM code in device/pci_rom.c, since there are only two ways
to get a ROM address now (CBFS and the device) and add an exception for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Declare superio functions to be static and remove duplicates.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to build, but by default all the tables that are available are built.
Make PIRQ table build for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Reset the s2891 so the HT speed gets updated.
Remove some PANTA comments.
Add SATA init from non-CAR version.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Both were only really used in pre-cbfs, as the payload's size isn't
relevant for the build process anymore.
Various calculations in {no,}failovercalculation.lb are adapted
accordingly.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Whitespace fixes, remove trailing whitespace, use TABs for identation
(except in Kconfig "help" lines, which start with one TAB and two spaces
as per Linux kernel style)
- Kconfig: Standardize on 'bool' (not 'boolean').
- s/lar/cbfs/ in one Kconfig help string.
- Reword various Kconfig menu entries for a more usable and consistent menu.
- Fix incorrect comment of NO_RUN in devices/Kconfig.
- superio/serverengines/Kconfig: Incorrect config name.
- superio/Makefile.inc: s/serverengine/serverengines/.
- superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/.
- mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string.
- mainboard/via/epia-n/Kconfig: Fix "bool" menu text.
- console/Kconfig: Don't mention defaults in the menu string, kconfig
already displays them anyway.
- Kill "Drivers" menu for now, it only confuses users as long as it's emtpy.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Works on Kontron, qemu, and serengeti.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
tested on abuild only.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Major changes:
1. Separate resource allocation into:
A. Read Resources
B. Avoid fixed resources (constrain limits)
C. Allocate resources
D. Set resources
Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources. All fixed resources will end up outside (above or below)
the allocated resources.
Domains usually start with base = 0 and limit = 2^address_bits - 1.
I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources. Some platforms may want to change that, but I didn't
want to break anyone's board.
Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add initial ACPI support for M57SLI.
Activates/Enables:
* native Coreboot ACPI for M57SLI
* Soft-Power-Off
* PowerNow!
* High Precision Event Timer
* Windows booting with ACPI support
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.
Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
To ease some of my debugging pain on the unichrome, i decided i needed to
move FB size selection into cmos, so i could test a size and then reset it
to the default after loading this value so that the next reboot uses the
(working) default again. This meant implementing set_option in parallel to
get_option.
get_option was then found to have inversed argument ordering (like outb) and
passing char * and then depending on the cmos layout length, which made me
feel quite uncomfortable. Since we either have reserved space (which we
shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go. So all users of
get_option now have their arguments inversed and switched from using ints
to unsigned ints now.
The way get_cmos_value was implemented forced us to not overlap byte and to
have multibyte values be byte aligned. This logic is now adapted to do a
full uint32_t read (when needed) at any offset and any length up to 32, and
the shifting all happens inside an uint32_t as well. set_cmos_value was
implemented similarly. Both routines have been extensively tested in a
quick separate little program as it is not easy to get this stuff right.
build_opt_tbl.c was altered to function correctly within these new
parameters. The enum value retrieval has been changed strol(..., NULL, 10)
to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
now but so that we also interprete hex values correctly. The 32bit limit
gets imposed on all entries not marked reserved, an unused "user_data" field
that appeared in a lot of cmos.layouts has been changed to reserved as well.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I didn't try to remove "defined but not used" warnings because there are too
many ifdefs to be sure I wouldn't break something.
For shadowed variable declarations I renamed the inner-most variable.
The one in src/pc80/keyboard.c might need help. I didn't change the
functionality but it looks like a bug.
I boot tested it on s2892 and abuild tested it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few
include files and missing prototypes. Also, fix up the Config-abuild.lb files
to properly work for cross compiling.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
changes by file:
src/northbridge/amd/amdk8/northbridge.c:
Add high tables code ala Stefan's code for the i945.
src/southbridge/nvidia/ck804/ck804_lpc.c:
Enable High Precision Event Timers.
Add pm_base for ACPI.
src/southbridge/nvidia/ck804/ck804_fadt.c:
Since fadt is only dependent on the Southbridge, add it here.
src/southbridge/nvidia/ck804/Config.lb:
Compile in ck804_fadt.c
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code to use it. That makes the code more readable and also less
error-prone.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
secondary controller was ok). There were two problems: the master sata
controller was not being initialized, and the irqs for the secondary ports on
both controllers were not being set in the mptable.
Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem.
While all ports work reliably under a recent kernel (2.6.24), sata is about
half as fast as under the proprietary bios, according to bonnie++. That still
needs fixing...
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a compiler warning.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Don't enable pin0 for ioapic of io-4.
1. apic error in kernel for MB with mcp55+io55
2. some pcie-cards could have pci bridge there, so need to put entries
for device under them in mptable.
Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
rodata.pci_driver" warnings are coming from? We were packing those
structures into a read-only segment, but forgot to mark them const.
Despite its size, this is a fairly trivial patch created by a simple
search/replace
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
fixes the problems with PCI add-on cards not being detected or
initialized on MCP55-based systems (PCI bridge decoding change).
I have tested this on the MSI MS-7260 (K9N Neo) with a PCI VGA card,
which worked fine in any of the three PCI slots.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Reported by Robert Millan.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is tested with abuild so shouldn't break anything.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
For example: in C51/MCP55 or C51/MCP51
Will allow
1. C51 at 0x10 to 0x14, and MCP at 0 to 4
2. C51 at 1 to 4, and MCP at 7 to 0x0a
The reason is c51/mcp51/mcp55 reported unitid is 0x0f (far beyond it
needed), and will prevent us from putting them on bus 0.
Typical values for c51/mcp55 or c51/mcp51:
HT_CHAIN_UNITID_BASE = 0x10 # for C51
HT_CHAIN_END_UNITID_BASE = 0 # for mcp
If only have mcp with c51,
HT_CHAIN_UNITID_BASE = 0 # for MCP
#HT_CHAIN_END_UNITID_BASE = 0 # default value 0x20
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
that's the same as broadcom/bcm5785.
Signed-off-by: bxshi <bingxunshi@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2200 (too many names, sounds like a criminal).
1) Linuxbios loads kernel A; kernel A loads kernel B. Everything works
fine.
2) Then I push the reset button.
3) Linuxbios loads kernel A; kernel A loads kernel B. Kernel B complains
about wrong checksum of the mptable and crushes later.
An investigation showed that in 3), short after kernel A (v2.6.19.2)
sets
the Bus Master Enable bit of the nVidia's USB1 controller
(pci_set_master()),
the mptable gets two bytes at physical address 0x80 damaged.
Nothing is plugged to the USB ports. Other two Sun workstations had the
same
behavior. This does not make sense to me unless the controller has a HW
bug.
I believe, this should better be fixed in the kernel USB driver.
For now this patch offers a possibility for linuxbios to reset the USB
controller by setting HostControllerReset bit in HcCommandStatus
Register.
It is enablead by using 'register "usb1_hc_reset"="1"' in 'chip
southbridge/nvidia/ck804' section of the mainboard's Config.lb.
Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
won't compile), and breaks an unnecessary dependency on the usbdebug
code.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
same format for all CHIP_NAME() entries in LinuxBIOS (Closes#20).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Yinghai Lu <yhlu@tyan.com>
set CK804 nic mac addr in MMIO instead of pci config
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Yinghai Lu <yhlu@tyan.com>
nvidia onboard lan support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Jonathan Kollasch