Commit Graph

37407 Commits

Author SHA1 Message Date
Josie Nordrum 3f1de9add9 acpi/acpigen_dsm: fix I2C HID DSM to report correct function support
Fix DSM function 0 (query function) to correctly report function support
for its revision.  Revision 1 should return 0x3 because I2C HID supports
only 1 additional function. All other revisions should return 0.

BUG=b:170862147
BRANCH=Zork
TEST=ensure no dmesg errors; disassemble and verify SSDT

Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: Iee082ef5cf44c4cf7ab304345af56f3b5173ca56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46429
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-16 18:23:54 +00:00
Kevin Chiu efe581254e mb/google/zork: disable eMMC per FW_CONFIG for berknip
Berknip has SSD/eMMC SKU, we should turn off eMMC if storage is NVMe SSD.

BUG=b:170592992
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. Check eMMC is enabled or disabled based on the eMMC bit in
        FW_CONFIG.

Change-Id: I7aeabc98fc16bc2837c8dcdc40c3c6a80898cdc9
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-10-16 18:07:41 +00:00
Subrata Banik 3f561a8e08 mb/intel/adlrvp: Enable Hybrid storage mode
TEST=Build and test booting ADL RVP form NVMe and Optane
localhost ~ # lspci -d :f1a6
Show all the NVMe devices and be really verbose
localhost ~ # lspci -vvvd :f1a6
Print PCIe lane capabilities and configurations for all the NVMe devices.

Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16 04:03:08 +00:00
Subrata Banik 6147314344 mb/intel/adlrvp: Enable PCIE RP11 for optane
A regular M.2 NVMe SSD shows up on RP9 and runs at x4 width.

Optane memory module shows up as 2 NVMe devices in x2 config:
- NVMe storage device uses RP9
- NVMe Optane memory uses RP11

Note: These two devices are sharing CLK PINs because of same M.2 slot.

TEST=Build and boot ADL RVP board using Intel Optane card.

Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16 04:03:00 +00:00
Subrata Banik 604a104a1c mb/intel/adlrvp: Fix SSD detection issue on ADL RVP
Make PCI ClkReq-to-ClkSrc mapping correct to fix SSD detection issue
on ADL RVP.

TEST=Able to detect WD SSD card over PCH SSD RP9.

Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16 04:02:50 +00:00
Subrata Banik bf38d58420 mb/intel/adlrvp: Program GPIO for M.2 PCH SSD
This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port
Detect (GPP_A12) as per schematics.

TEST=Able to build and boot ADL RVP.

Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-16 04:02:32 +00:00
Angel Pons e0ce60c744 lib and libpayload: Add popcnt functions
Add 32-bit `popcnt` and 64-bit `popcnt64` helpers.

Change-Id: I2e6a1007e475b662a85c067d96f81326e7f02905
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-15 19:01:51 +00:00
Marc Jones e1db55b43e soc/intel/xeon_sp: Add get_system_memory_map()
Prepare for common ACPI. Add get_system_memory_map() helper
function to soc_util.c and use it in the SRAT ACPI code
to match the cpx code.

Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15 15:55:25 +00:00
Yidi Lin 42f795904c ec/google/chromeec: Update ec_commands.h
This change copies ec_commands.h from Chromium OS EC repo at 7b6cb69db.
The change also drops unneeded empty lines and coverts license header
to SPDX style.

BUG=b:147789962
BRANCH=none
TEST=emerge-asurada coreboot

Change-Id: I9816dab5edb418e76896355a0802c59307c664c4
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-15 13:44:52 +00:00
Huayang Duan 232d8a8eb5 Update bit field helpers to support more bit field operate
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I8f182fff45806912da2390939a6652932501d7c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-10-15 13:44:34 +00:00
Michael Niewöhner e4478637bd MAINTAINERS: add Michael Niewöhner to mb/clevo
Add Michael Niewöhner as another maintainer for Clevo mainboards.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Id3b35ddda13119149321e8c883e151176d8c520d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43655
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15 12:24:11 +00:00
Arthur Heymans 7af8aca246 sec/intel/txt/getsec_enteraccs.S: Save and restore MTRR_DEF_TYPE
This needs to be saved and restored, otherwise the BSP might have an
inconsistent MTRR setup with regards to the AP's which results in
weird errors and slowdowns in the operating system.

TESTED: Fixes booting OCP/Deltalake with Linux 5.8.

Change-Id: Iace636ec6fca3b4d7b2856f0f054947c5b3bc8de
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15 08:33:23 +00:00
Angel Pons 4b290b7b6f nb/intel/haswell: Account for DPR region in memory map
While MRC.bin does not allocate any memory for DPR by default, it can be
patched to do so. However, the current northbridge code does not account
for DPR and will, among other things, place CBMEM inside it. Even though
this may seem like a good thing, it renders TianoCore unable to boot and
clashes with Intel TXT support (the reason to enable DPR to begin with).

Update memmap.c so that CBMEM top does not fall within DPR. Also, report
DPR as reserved, so that OSes know that the DPR memory is not to be used.

Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-15 08:31:54 +00:00
Angel Pons 11334729c9 security/intel/txt: Use `smm_region()` to get TSEG base
This function is available for all TXT-capable platforms. Use it.
As it also provides the size of TSEG, display it when logging is on.

Change-Id: I4b3dcbc61854fbdd42275bf9456eaa5ce783e8aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-15 08:31:48 +00:00
Benjamin Doron adcb870837 soc/intel/skylake: Configure L1 substates for PCH root ports
Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration.

Tested on an Acer Aspire VN7-572G (Skylake-U).

Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-15 00:01:05 +00:00
Angel Pons 3e314636a6 soc/intel/skylake/cpu.c: Fix comment coding style
This comment does not follow any of the styles outlined in the coding
style page of the documentation. Adjust it to match the preferred style.

Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46428
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 20:44:13 +00:00
Shaunak Saha b27b0fd2ac mb/google/volteer: Disable HybridStorageMode for volteer baseboard
HybridStorageMode FSP UPD needs to be set only for optane storage.
Enabling HybridStorageMode causes some extra delay in FspSiliconInit due
to HECI command and hence is avoided for NVMe and SATA scenerios. This
change disables "HybridStorageMode" for volteer baseboard. For boards
using optane HybridStorage needs to be enabled from overwrite devicetree.
We are enabling HybridStorage for volteer and volteer2 as those plaforms
have SKU's with optane storage.

BUG=b:158573805
TEST=Build and boot non optane device and confirm that FspSiliconInit
time is reduced. This saves ~100ms.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 16:46:17 +00:00
Tim Wawrzynczak 7ded1afe0a lib and libpayload: add 64-bit versions of clz, __ffs and log2
Add 64-bit versions of clz, __ffs & log2: `__ffs64`, `__clz64`,
and `log2_64`.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iefc6e6c51f5b20607c88e38660a499a4f77ce0d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-14 15:24:59 +00:00
Subrata Banik 7223bfa47e mb/intel/adlrvp: Add ADL-P mainboard ASL code
Add required ASL files into dsdt.asl

TEST=Dump and disassemble DSDT and verify all ACPI devices are present.

Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 14:49:09 +00:00
Subrata Banik 9b4f221026 mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes:
1. Add devicetree.cb config parameters related to FSP-S UPD
2. Configure GPIO as per ADL-P RVP
3. Add files required for ramstage(ec.c, mainboard.c)
4. Add smihandler.c for SMM
5. Add devicetree changes as below
- USB OC PIN programing
- GPE configuration
- SATA port mapping
- LPSS configuration
- Audio configuration
- IA common SoC configuration
- EDP configuration
- TCSS USB configuration
- Enable S0ix

TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with
UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till
depthcharge payload.

Change-Id: I120885956c88babfa09d24ce1079d49306919b8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 14:49:01 +00:00
Aamir Bohra 522ba1ba27 soc/intel/jasperlake: Enable CAR NEM enhanced mode
TEST=Build and boot waddledoo board

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I067b13acfcea940e2e4ae6fc99b5d77458de35a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43705
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 14:46:59 +00:00
Angel Pons c004ae5656 .gitignore: Do not let git track '*.fd'
These files are usually binaries, and should never be committed.

Change-Id: I9df80f777020632e4c82a06ae3ae73c95234f3b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46322
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 09:24:25 +00:00
Angel Pons 04bf41b5aa util/lint: Capitalise lint descriptions
Most test descriptions are capitalised already. Follow suit.

Change-Id: I756331323a39643244c4adea4c440f305424d6d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-14 09:19:58 +00:00
Angel Pons 41e66ac38f nb/intel/x4x: Place raminit definitions in raminit.h
There's no need to have implementation details in a public header.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I04d8c610d3e52adecfe96cc435f0523bedf3060a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-10-14 09:19:22 +00:00
Angel Pons fd19075045 nb/intel/x4x: Move register headers into a subfolder
Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: I74dbd985b980d8a42bfaf2984820005320a803d3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45421
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 09:19:11 +00:00
Angel Pons 4cee40a19d mb/purism/librem_skl: Drop DQ and DQS byte maps
These settings are not necessary for DDR4 and can be dropped.

Change-Id: I1946be239f0c90db995a60570474039cef45cfa9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-14 09:16:21 +00:00
Angel Pons a5314b62b6 nb/intel/x4x: Clean up DMIBAR/EPBAR definitions
Several registers have been copy-pasted from i945 and do not exist on
Eagle Lake. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: I9582d159aa2344bcf261f0e4b97b15787156f6e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-10-14 08:45:19 +00:00
Angel Pons 8b8b271f12 soc/intel/broadwell/xhci.c: Align with Lynx Point
Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45721
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 08:38:42 +00:00
Angel Pons 3b8b00fd39 soc/intel/broadwell/smi.c: Drop unused functions
These aren't used anywhere, so get rid of them.

Change-Id: I267c0fd2e9d9d20ee852a73a9a916d85d6c65088
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45716
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 08:38:08 +00:00
Angel Pons d5689dd289 soc/intel/broadwell/pcie.c: Add some null checks
These are present in Lynx Point.

Change-Id: I381f3cbf5fd18c952622f757135c0bde9ed6ed0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45715
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 08:37:52 +00:00
Angel Pons 2aaf7c0a1d haswell/lynxpoint: Align cosmetics with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.

Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 08:37:36 +00:00
Angel Pons 2ead363340 soc/intel/broadwell: Align cosmetics with Haswell/Lynx Point
Tested with BUILD_TIMELESS=1, Purism Librem 13v1 does not change.

Change-Id: Icf41d9db20e492ec77a83f8413ac99a654d6c8ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45697
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 08:36:43 +00:00
Angel Pons 9bf45b43ee soc/intel/broadwell/igd.c: Rename to gma.c
This makes comparisons against Haswell a bit simpler.

Change-Id: If1c937628f702c6765a5f36b6eaf4a3c3516359a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 08:36:16 +00:00
Karthikeyan Ramasubramanian 685dbe14e9 acpi/device: Add GPIO binding property for an array of GPIOs
This change is required for use-cases like GPIO based I2C multiplexer
where more than one GPIOs are used as select lines.

BUG=b:169444894
TEST=Build and boot waddledee to OS. Ensure that the GPIO bindings for
an array of GPIOs are added to the ACPI table as follows:
Device (MUX0)
{
    ...
    Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
    {
        GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
                "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
                )
        {   // Pin list
            0x0125
        }
        GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
                "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
                )
        {   // Pin list
            0x0126
        }
    })
    Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
    {
        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
                Package (0x01)
        {
            Package (0x02)
            {
                "mux-gpios",
                Package (0x08)
                {
                    \_SB.PCI0.I2C3.MUX0,
                    Zero,
                    Zero,
                    Zero,
                    \_SB.PCI0.I2C3.MUX0,
                    One,
                    Zero,
                    Zero
                }
            }
        }
    })
}

Change-Id: I7c6cc36b1bfca2d48c84f169e6b43fd4be8ba330
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-14 05:43:00 +00:00
John Su ae763de649 mb/google/dedede/var/madoo: Update DPTF setting
Add tcc, critical, passive policy, and pl values from thermal team.

BUG=b:169215576
TEST=build and verify by thermal tool

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I4f61eaa7eab2b86b04ff0541886621afb3082b1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-10-14 05:38:29 +00:00
Divya Sasidharan 49d74de969 src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
EC being the TCPM decides the mux configuration after negotiating with the
port partner on the Type-C port. The APIs added here will give the
current essential mux state information for a given port.

BUG=None
BRANCH=None
TEST=Built coreboot image and verified that using this patch mux is being
set for display during boot

Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 05:37:40 +00:00
Brandon Breitenstein 9faab3122e soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel
PMC IPC driver API is needed to send IPC commands to the PMC to update
connection/disconnection states.

BUG=b:151731851
BRANCH=none
TEST=built coreboot image and booted to Chrome OS

Change-Id: Ide3528975be23585ce305f6cc909767b96af200f
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 05:37:17 +00:00
Bora Guvendik 7377cda608 mb/intel/tglrvp: Enable Pcie WWAN m.2
Enables Pcie M.2 support for WWAN and disable M.2 USB.
RP4 is already on and PcieRpEnable[3] is enabled. Clock source 2 is already
configured. Added missing gpio configuration.

BUG=none
TEST=Boot to OS, check WWAN functionality

Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45828
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 05:36:57 +00:00
Rob Barnes d1095c7ed7 mb/google/zork: Enable wake on wireless lan
Add generic wifi ACPI entry for wake on lan event.
Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI.

BUG=b:162605108
TEST=$ iw phy phy0 wowlan enable disconnect
     $ cat /proc/acpi/wakeup | grep WF
       WF00	  S3	*enabled   pci:0000:01:00.0
     $ powerd_dbus_suspend
     Reboot wifi router, DUT wakes up
BRANCH=zork

Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45745
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 04:47:39 +00:00
Subrata Banik 0aed4e577d soc/intel/alderlake: Enable TME for Alder Lake
List of changes:
1. Select CONFIG_INTEL_TME from SoC Kconfig
2. Set TmeEnable FSP-M UPD based on Kconfig.

TEST=Able to build and boot ADLRVP and verified from Chrome OS
that TME is enable.

Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 03:39:00 +00:00
Subrata Banik 8e251f7fce vc/intel/fsp/fsp2_0/adl: Update FSP header to version 1332.01
List of changes:
- Add FSP-M UPD 'TmeEnable'

TEST=Build and boot ADLRVP platform.

Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46295
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 03:38:49 +00:00
Duncan Laurie 6f58b991de soc/intel/tigerlake: Enable and use USB4 PCIe driver
This change enables the USB4/Thunderbolt common layer for Intel SOC,
and enables the Intel USB4 PCIe driver.  This moves the _DSD variables
from the DSDT into the SSDT and allows them to be configured for each
board if necessary.

Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44917
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 02:55:35 +00:00
Duncan Laurie ce3a9740f1 soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports
This driver will generate the ACPI _DSD for the USB4 PCIe root port
properties instead of using static ASL.

It assigns the USB4 port number and marks the port as external and
hotplug capable.

Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44915
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 02:55:20 +00:00
Duncan Laurie d6331e0884 soc/intel/common/block: Add common support for USB4/Thunderbolt
This common intel driver will add the requried ACPI _DSD entries for
enabled USB4/Thunderbolt ports' DMA devices the SSDT instead of using
hardcoded values in the DSDT.

Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-14 02:54:58 +00:00
Tim Wawrzynczak 950305de0a soc/intel/common: Add PCI driver for USB4 ports
In order to enable SSDT generation for the DMA component of Intel USB4
ports, a PCI driver is required. This patch more or less adds a
`scan_bus` callback that will handle non-PCI devices downstream.

Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-14 02:54:23 +00:00
Tony Huang 72464a4795 mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS)
Enable ALS ACPI devices for dooly.

BUG=b:168426118
BRANCH=puff
TEST=Ensure that ALS devices are enabled in ACPI tables.

Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-14 02:21:59 +00:00
Julius Werner 87feced195 sc7180: Enable bootblock compression
This patch enables bootblock compression on SC7180. In my tests, that
makes it boot roughly 10ms faster (which isn't much, but... might as
well take it).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45855
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 22:41:19 +00:00
Julius Werner 6b8305d240 drivers: snsn65dsi86: Fix link rate parsing
DP link rates are reported in an array of LE16 values. The current code
tries to parse them as 8-bit which doesn't get very far, causing us to
always drop into the fallback path. This patch should fix the issue
(+minor whitespace cleanup).

BUG=b:170630766

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1e03088ee2d3517bdb5dcc4dcc4ac04f8b14a391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2020-10-13 22:41:05 +00:00
Michael Niewöhner b73d2476dc soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig
The current Kconfig help text is confusing because it talks about
enabling the Kconfig for disabling a UPD for disabling power gating.

Rewrite and clarify the help text.

Change-Id: I9637c549db1ce29f259708f316852fc2ae9e7c38
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-13 22:21:36 +00:00
Felix Singer 63975f0e68 MAINTAINERS: Add Felix Singer to mb/clevo
Change-Id: I1d4547d02cf0d27db5c3b0c0ae46b730a198c814
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46316
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 22:15:56 +00:00