Commit Graph

39688 Commits

Author SHA1 Message Date
Seunghwan Kim 9f5c365e6d mb/google/nightfury: Update RAM IDs usage
Add support LP_16G_2133 SPD for nightfury.

BUG=None
BRANCH=firmware-hatch-12672.B
TEST=emerge-hatch coreboot

Change-Id: I3709431d8ecb600e25909f456eb0c95db3a3cde2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-22 14:27:15 +00:00
Furquan Shaikh 197c486997 types.h: Add a helper macro BITS_PER_BYTE
This change adds a helper macro `BITS_PER_BYTE` so that it doesn't
have to be defined in multiple places.

Change-Id: Idc344047a5660791eaeb1ce8012910c11f6010ba
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-22 14:26:58 +00:00
Varshit Pandya b5df56f6f2 soc/intel/alderlake: Adding Kconfig for ADL_M PCH
1. Add SOC_INTEL_ALDERLAKE_PCH_M option in Kconfig
2. Select number of I/O based on PCH

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I38783595e4b85abf5b3bec234ba01667bd9ba754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49630
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:26:44 +00:00
Varshit Pandya f4d98fdd20 soc/intel/commmon: Include Alder Lake device IDs
Add Alder Lake M specific CPU, System AGent, PCH (Alder Point aka
ADP),
IGD device IDs.

Document Number: 619501, 626817

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: Ib13fe229f9e65eae8967aa20e28e29ac5c319265
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49629
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:26:38 +00:00
Wisley Chen f2d38baa98 mb/google/volteer/var/elemi: Update dptf parameters
Update DPTF setting from thermal team.

BUG=b:177635236
BRANCH=volteer
TEST=emerge-volteer coreboot chromeos-bootimage, and verified by thermal team.

Change-Id: I87256b5c210ef12c09ef6dd948d80f406ae0500b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-01-22 14:26:19 +00:00
Hsin-Hsiung Wang d194081ba6 soc/mediatek/mt8192: pmic: Set efuses manually
Some efuse settings would not be applied automatically, so we need
set the settings manually. The low power consumption would not be
optimal without correct efuse settings.

BUG=b:172636735
BRANCH=none
TEST=see 'pmic_efuse_setting: Set efuses in 11 msecs'

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Ideb862c3cb0f1fee183804aed74fcf141bf1f5df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-22 14:26:08 +00:00
Nick Chen d6375cf556 mb/google/volteer/variants/eldrid: Configure USB2 port for Type-C
1. USB2 ports 3 and 8 assigned to Type-C connector
2. USB2 port 3 keep USB2_PORT_SHORT setting and add .type_c flag

BUG=b:177481076
TEST=tested on eldrid

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I42a39318a151bdf1f5aeb84bb1992be128cb4a4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-22 14:25:58 +00:00
Yu-Ping Wu 37765930ec soc/mediatek/mt8183: Fix pq module size config
For pq module size registers such as DISP_AAL_SIZE, the high bits
should be HSIZE, while low bits should be VSIZE. Fix the incorrect
settings for these registers where width and height are reversed.

According to MediaTek, there is no practical impact on mt8183 devices,
but it's still nice to get this fixed to avoid future confusion.

BUG=b:171167210
TEST=none
BRANCH=kukui

Change-Id: I4b6aedf9a3ca133fcbe9cb88b99a13d228233e24
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46626
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:25:46 +00:00
Arthur Heymans 279c3e1e7d mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can
also be configured with "-global mch.extended-tseg-mbytes=5" command
line argument. Note that the size in ESMRAMC needs to be 'invalid' (3)
for this to take action.

coreboot will leave TSEG at the default 1MiB.

Note that even if TSEG does not end up being used, it is likely a good
idea to not put anything there as if SMM gets locked down by something
else it will suddenly be inaccessible.

Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-22 14:25:35 +00:00
Angel Pons c89d2a2890 cpu/intel/haswell: Enable timed MWAIT if supported
Broadwell code unconditionally enables timed MWAIT, but not all Haswell
steppings support it. In preparation for merging Haswell and Broadwell,
also enable timed MWAIT on Haswell code, but only if it is supported.

Change-Id: I1d11d62f1801d65ae4d5623994fd55fd35e8f34a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46916
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:25:22 +00:00
Felix Held 8199b88222 soc/amd/common/block/smbus: always return SMBus MMIO in get_sm_mmio
The old code was broken and register 0x90 didn't even exist any more in
the config space of the SMBus PCI device, so just always return the MMIO
base address of the SMBus controller. As far as I've seen, no board in
tree uses this functionality at the moment.

Change-Id: Ib80d5c928da6022427afb8ccc969fb2aac953c2d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-22 14:24:55 +00:00
Elyes HAOUAS fc7b41d370 mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax
IASL optimizes the code differently, which changes the binary.
However, the generated `build/dsdt.dsl` remains identical.

Change-Id: Ifcc8bf4022838056bf1fff853eb2027af684064e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45554
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:24:32 +00:00
Kyösti Mälkki 23b081825d soc/intel/baytrail,broadwell: Refactor acpi_wake_source()
Change-Id: I5c277a4b8536fd79bda040d4ada9b0c454399b09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49356
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 04:30:24 +00:00
Sunway 548d350305 mb/google/kukui: Enable MT8183_DRAM_EMCP for katsu
The katsu project will be using eMCP board design.

BUG=b:176271935
TEST=Boots on chromebook katsu successfully.
BRANCH=kukui

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I733a9a79e2ea6501e26bf79bfce2b1934a295342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48893
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 03:34:34 +00:00
Julius Werner 7d4ef16efe Makefile.inc: Avoid --emit-relocs on RISC-V
There seems to be a bug[1] in the GNU linker for the RISC-V architecture
triggered by symbols that are more than 2GB offset from the program
counter. My next patch is introducing symbols like that and stuck on
this problem. The code path that runs into the issue is only taken when
passing the --emit-relocs flag, which is really only needed for building
rmodules. Since RISC-V platforms don't use any rmodules at the moment,
let's disable the flag on RISC-V until the issue can be fixed in the
toolchain.

[1]: https://sourceware.org/bugzilla/show_bug.cgi?id=27180

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I784a506034325c0ba937589416acaafbf80080e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49449
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 02:13:11 +00:00
Felix Held 88615629c0 soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16
Change-Id: I97c73324900a0677165afa3f5b182a336d534968
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-01-21 22:26:40 +00:00
Michael Niewöhner eb723f01af mb/siemens/chili: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to a bootblock gpio table for the board as a
first step. Common UART pad config code then gets dropped in CB:48829.

Change-Id: Iad40b6315a29e7aea612a3e1a169372d296d1d6c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49443
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 19:03:08 +00:00
Michael Niewöhner 70992a4335 mb/up/squared: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I357099f797be178543a9e6637335cd0a68633071
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49441
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 19:02:08 +00:00
Michael Niewöhner 18d360a582 mb/intel/kblrvp: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early gpio table for the board as a
first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I8b30eb5d70c34ae3e2ed24ab52dd1357a54c5ae7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49439
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 19:01:58 +00:00
Michael Niewöhner f6d320060d mb/intel/minnow3: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I0b956427a9cec56d06b03f7f05138f75137b4ea3
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49437
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:50:11 +00:00
Michael Niewöhner 3840bcc19e mb/intel/leafhill: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: Ibc727302109456eb1d86652c947ce85b3a64c5b2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49436
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:50:01 +00:00
Michael Niewöhner 9c27dc8d56 mb/intel/glkrvp: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I80369ab70d5510cb4f388f3029119e7148361af4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49435
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:49:21 +00:00
Michael Niewöhner bb9dda4a7a mb/intel/apollolake_rvp: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to a early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: Id6b55d7f3d3fbfc5b55497708f24006614760d03
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49434
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:49:08 +00:00
Michael Niewöhner 1d05a3bf56 mb/intel/tglrvp: do UART pad config at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I130fd26944169430a84c3609432b1b5283581c99
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49432
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:41:28 +00:00
Michael Niewöhner 4940255a40 mb/intel/jasperlake_rvp: do UART pad config at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: Ie3878b47b8e20c51b928a38df9ccedf2d50d478e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49431
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:41:17 +00:00
Michael Niewöhner beee666ad3 mb/intel/icelake_rvp: do UART pad config at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: Ib19a4f64eaf25bf2eb47ee60748a68538fc0729a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49430
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:41:05 +00:00
Michael Niewöhner a7bc5b818a mb/google/reef: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I279956f30cbb6fb031cdfe6aaa09b644b6b7d3e7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49427
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:40:46 +00:00
Michael Niewöhner 186c0eb27e mb/intel/minnow3: drop unneeded call to lpc_configure_pads
The LPC/eSPI pad configuration is already done at board-level. Thus,
drop redundant configuration by dropping the call to lpc_configure_pads.

Change-Id: Ib9e62bf19e6f1fbe32a340e4802c13504a0d6def
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49417
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:29:57 +00:00
Michael Niewöhner f9544da6c4 mb/intel/leafhill: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms by
adding an appropriate early gpio table in the bootblock.

The soc code gets dropped in CB:49410.

Change-Id: Ie1e53e72c65fdcfe4be2e01134873aa7858c28ff
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49416
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:14:09 +00:00
Michael Niewöhner fccc24f063 mb/intel/glkrvp: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms.
This is done by adding one missing pad to the early gpio table and
dropping the call to the soc function.

The soc code gets dropped in CB:49410.

Change-Id: I210633d4520fcfab59f68268bd7991557433ce38
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49415
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:13:39 +00:00
Michael Niewöhner f31c2f2b7a mb/up/squared: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms by
adding an appropriate early gpio table in the bootblock.

The soc code gets dropped in CB:49410.

Change-Id: If0693a4419c58dde3c4536698940f03c30304b9d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49414
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:13:19 +00:00
Michael Niewöhner 17721be11a mb/google/reef: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms.
This is done by adding missing pads to the bootblock gpio table.

The soc code gets dropped in CB:49410.

Change-Id: I95993b1bd4f1fd8b4ac7b21fb89ec4d196b0240a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49412
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 18:12:25 +00:00
Michael Niewöhner 3a2d4000ce mb/google/hatch: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I62ffbe36bd7b7675aa0f41a8c6e9214d04ad4ae5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49428
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 17:52:06 +00:00
Michael Niewöhner 1b77a487d6 mb/google/glados: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early gpio table for the board as a
first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I6fedcebea3bb31d992bac1e3b21382fea93a8b82
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49429
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 17:51:36 +00:00
Michael Niewöhner 1c22753996 mb/google/octopus: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: Ieeb738afd54e77ee853ee109009f611411aa0d4a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49426
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 17:49:41 +00:00
Michael Niewöhner 805b96cdc6 mb/google/dedede: do UART pad config at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I5482f44b361925b7d2dbcbf1065c1be035c68b0b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49424
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 17:49:29 +00:00
Michael Niewöhner 4bf70523b3 mb/google/drallion: do early pad configuration in early bootstage
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).

Change-Id: I7dcf88d61c305f0598a0a79f8cfa46ef5009564b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-01-21 17:49:18 +00:00
Michael Niewöhner 732e9e6382 mb/google/octopus: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms by
adding an appropriate early gpio table in the bootblock.

The soc code gets dropped in CB:49410.

Change-Id: Ie33bae481f430a1c4410a0a4e2b2a34a3e78adaa
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49411
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 17:47:53 +00:00
Angel Pons 8b0636e06f cpu/intel/haswell: Clean up CPUID definitions
The `mobile` suffix is misleading, since desktop CPUs share the same
CPUIDs. Remove unused stepping IDs and add the full CPUIDs instead.
Finally, add Broadwell CPUIDs in preparation for merging CPU code.
Note that steppings for Haswell in various comments are incorrect.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46915
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 11:27:27 +00:00
Angel Pons 8e6f162cc0 cpu/intel/haswell: Add s0ix support
Backport Broadwell's s0ix support to Haswell in preparation to unify
both platforms' CPU code. Note that only ULT variants support s0ix.

This option is currently unused, but will be put to use in subsequent
commits, when switching Broadwell mainboards to use Haswell's CPU code.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46924
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 11:27:07 +00:00
Tim Crawford e78e909180 src/drivers/smmstore: Fix SMMSTOREv1 clear command
The `clear` command for SMMSTORE version 1 does not require a parameter.

Change-Id: I992b7ce5962bf7ee62b7e1970ae7aa1b975ef42e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49724
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 11:04:04 +00:00
Kevin Chang 4ed4c2474b mb/google/volteer/variant/lindar: Enable SA GV setting
Allow MRC training in SA GV.

BUG=b:177779469
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Idc9f634135b489450f53f8cd28d80649309d0f70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-21 11:03:35 +00:00
Mathew King b35b823a59 mb/google/guybrush: Add default FMD file to the build
BUG=b:175143925
TEST=builds; binary has correct layout

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I4f3826c8ed0dfd7219eaa5f0cc285f1fe89a4e1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-21 11:03:26 +00:00
Kevin Chang 8583191e8a mb/google/volteer/variant/lindar: Configure USB2 port for type-c
Assigned USB2 port to type-c use.

BUG=b:177483060
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I9bd820406124927d56296508be05033217c0d472
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49638
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 11:03:18 +00:00
Frans Hendriks 6f468a58c1 ach/x86/postcar.c: Avoid double CBMEM initialization
On FSP1.1 platform cbmem_initiailze() is called in
chipset_teardown_car_main(). This causes double
call op cbmem_initialize().

Add call to cbmem_online() to avoid double CBMEM init.

BUG  = N/A
TEST = Build and boot on Facebook FBG1701

Change-Id: I449ddfc94f1099d7c0e9005e6a5cf509e1433bb1
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2021-01-21 11:03:04 +00:00
Frans Hendriks 162d704b57 drivers/intel/fsp1_1/temp_ram_exit.c: Initialize CBMEM
prog_locate() will load FSP, before CBMEM is initialized.
The vboot workbuffer is used for loading, but
CBMEM_ID_VBOOT_WORKBUF is not available.
A NULL pointer is returned as workbuffer resulting in error
'Ramstage was not loaded!' at second boot.

Initialize CBMEM before calling prog_locate().

BUG  = N/A
TEST = Build and boot on Facebook FBG1701

Change-Id: I2f04a326a95840937b71f6ad65a7c011268ec6d6
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-21 11:02:43 +00:00
Michal Suchanek be5cc7da5f msrtool: fix build with gcc 10.
[   84s] /usr/lib/gcc/i586-suse-linux/10/../../../../i586-suse-linux/bin/ld: msrutils.o:(.bss+0x0): multiple definition of `PresentTypes'; msrtool.o:(.bss+0x14): first defined here
[   84s] /usr/lib/gcc/i586-suse-linux/10/../../../../i586-suse-linux/bin/ld: msrutils.o:(.bss+0x4): multiple definition of `MsrTypes'; msrtool.o:(.bss+0x18): first defined here

There should be typedefs, not variable definitions.

Change-Id: I663a011e9f1fc169126570d5eac7abe82d204a90
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2021-01-21 11:02:01 +00:00
Kyösti Mälkki e05f81a3e0 soc/intel/quark: Add pwrs in <soc/nvs.h>
For the time being every soc/intel selects ACPI_SOC_NVS
and pwrs is a required field for the common initialisation
implementation of followup work.

Change-Id: I4a0c7eb35f0646898e49fad15c6448607c398731
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49493
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21 11:01:23 +00:00
Jeremy Soller 98d580b8fb soc/intel/cannonlake: Allow RP#1 usage for ClkSrc
0 is converted to not used, so use a special value to allow using PCIe
root port #1.

Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-21 11:01:08 +00:00
Furquan Shaikh 3b6b9c7b78 soc/intel/common/pcie_rp.h: Fix comment style
This change updates pcie_rp.h to reflow the comment blocks to fit
within 80 columns to match the original style of the file. This
addresses comment received on
CB:49370 (https://review.coreboot.org/c/coreboot/+/49370/comment/0f3fe10d_4e218b5f/).

Change-Id: I565ad602e0e3a2ee09e8345479d82e2ce0a31fd0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-21 11:00:54 +00:00