Commit Graph

38597 Commits

Author SHA1 Message Date
Sumeet R Pawnikar 8e57299a0d mb/intel/jasperlake_rvp: Update Power Limit2 minimum value
Update Power Limit2 (PL2) minimum value to the same as maximum value for
jasperlake rvp board. DTT does not throttle PL2, so this minimum value
change here does not impact any existing behavior on the system.

BUG=None
BRANCH=None
TEST=Build and test on jasperlake rvp board

Change-Id: I862f7106846de5fb37f74419807eedc3096ded8a
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:28:19 +00:00
Arthur Heymans ac12976f0c nb/intel/pineview: Fix clearing memory
The regions TSEG, GSM, GMS should not be marked as cacheable
resources.

Change-Id: I083b096cf3ed250bca722674abe9feffdb2436d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-09 07:28:01 +00:00
Patrick Rudolph 6e98292821 soc/intel/*/chip: Remove unused devicetree entry
InternalGfx isn't used so drop it.

Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09 07:27:38 +00:00
David Wu 2f6875518e mb/google/volteer/var/voema: config CSE LITE
Config voema to use CSE LITE

BUG=b:171755775
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic4ca82ce844e6367da70ed052445943572ae7b09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09 07:26:56 +00:00
David Wu 25f3c4d083 mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voema
BUG=b:171755775
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ibedbbe8f9ac039cbde114ace3266ec067a4003ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09 07:25:52 +00:00
Jes Klinke e94f86571c mb/google/volteer: Skip TPM detection except on SPI
Production Volteer devices have Cr50 TPM connected via SPI, depending on
Cr50 firmware version it may or may not support long enough interrupt
pulses for the SoC to safely be able to enable lowest power mode.

Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced
with Dauntless, communicating via I2C. The I2C drivers do not support
being accessed early in ramstage, before chip init and memory
mapping, (tlcl_lib_init() will halt with an error finding the I2C
controller base address.)

Since the Dauntless device under development can be made to support
longer interrupts, or a completely new interrupt signalling mode, there
is no need to try to go through the same discovery as is done via SPI.
This CL will skip the discovery, enabling the S0i3.4 sleep mode in all
cases, on the reworked test devices.

BUG=b:169526865, b:172509545
TEST=abuild -t GOOGLE_VOLTEER2 -c max -x

Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47049
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:24:54 +00:00
Karthikeyan Ramasubramanian d1c0f958d1 acpi: Call acpi_fill_ssdt() only for enabled devices
Individual drivers check whether the concerned device is enabled before
filling in the SSDT. Move the check before calling acpi_fill_ssdt() and
remove the check in the individual drivers.

BUG=None
TEST=util/abuild/abuild

Change-Id: Ib042bec7e8c68b38fafa60a8e965d781bddcd1f0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-09 07:24:13 +00:00
Johnny Li 04582e9001 mb/google/volteer/variants/volteer2: Tune I2C3 camera bus freq 400 kHz
The current I2C3 bus frequency is 341 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C3 to bring
the bus frequency closer to 400kHz.

BUG=b:153588771
TEST=Verified that I2C3 frequency is 394kHz.

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: Ie1ef95bb39d71fbb113120a0ec88305bc23e7ab9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-09 07:23:52 +00:00
Thomas Heijligen e569e3e248 libpayload: storage.c: remove unneeded #if CONFIG()
Change-Id: I6e5679f66840105b3f9628071ac7aace9128107f
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-09 07:23:20 +00:00
Tony Huang 83e41055ab mb/google/puff/var/dooly: Set default I2C0 frequency
This setting copy from puff reference board
and should measure again after whole system build.

BUG=b:155261464
BRANCH=puff
TEST=emerge-puff coreboot and check system speaker has sound output.

Change-Id: Idd5c3276e9306e81ea766d14ed1415a68dedc2ad
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47161
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 04:11:42 +00:00
Marc Jones 645bca4810 soc/intel/xeon_sp/skx: Reorder soc_util.c
Reorder soc_util.c  and remove the un-needed #if ENV_RAMSTAGE to match
cpx version in preparation for more de-duplication.

Change-Id: Iab343e903e2478709fe91739c9ca77f587286df7
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-09 03:00:45 +00:00
Subrata Banik 0a61ecef35 mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard'
List of changes:
1. Use devicetree.cb from default location
2. Create variant directory for ADL RVP with external EC as
'adlrvp_p_ext_ec'
3. Add initial overridetree.cb for 'adlrvp_p' and 'adlrvp_p_ext_ec'
to override 'devicetree.cb' as applicable.
4. Move all common files between 'adlrvp_p' and 'adlrvp_p_ext_ec'
to mainboard directory

TEST=Build and boot both ADLRVP with onboard and external EC.

Change-Id: I3591e214ed32dc9baaa49b92dff59579f29c7bd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47335
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-08 17:16:23 +00:00
Jacob Garber 85d93ffc0a libpayload: Make OHCI enums into types
The OHCI header file declares various enums as follows:

    enum { ... } enum_name;

Since the name is at the end, this is actually declaring a variable
called enum_name and *not* a type, which is causing a multiple
definition error in GCC 10. Move the enum_name before the opening brace
to prevent this.

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I452c0a1b118990942aa53f1e7e77f5e8378e8975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-08 11:37:09 +00:00
Jacob Garber c98baa7a80 libpayload: Add compiler.h to compiler parameters
Headers in libpayload define various structs like so:

    struct struct_name { ... } __packed;

However, these header files do not include the compiler.h macro that
defines what __packed is, so they are actually defining a variable named
__packed and *not* declaring a packed struct. This leads to defining the
same variable multiple times, which was caught by GCC 10. Add compiler.h
to the compiler parameters so it is included in all files automatically.

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ia67182520dc94149e06fe9e03a14b3fc2ee29973
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-08 11:37:04 +00:00
Martin Roth 3190ba863d soc/amd/common: Don't program GPIOs if the table isn't set
Currently, there's no check for the table being programmed.  This skips
programming a table if the table size is zero, or the pointer to the
table has been set to NULL.

BUG=None
TEST=Set table pointer to NULL, table doesn't run.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7d09b47e7d619428b64cc0695f220fb64c71ef4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-07 18:33:17 +00:00
Felix Held b6ef297564 soc/amd/common/psp: expand CPU family names in Kconfig help text
Expand fam17h to family 17h to make the help text slightly easier to
understand and add family 19h to the description of
SOC_AMD_COMMON_BLOCK_PSP_GEN2.

Change-Id: I9284c9c638e1d217d4605523dde004781f4343f9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-07 18:13:39 +00:00
Marc Jones fc62013fd1 mainboard/ocp/tiogapass: Add xeon_sp pch.asl
Use the xeon_sp pch.asl to include the intel common lpc.asl.

Change-Id: I22ee9d325888808a9c775ecee0591b661e2bba4e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Javier Galindo <javiergalindo@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-07 16:29:09 +00:00
Marc Jones d13d7c2735 mainboard/ocp/deltalake: Use xeon_sp pch.asl
Use the xeon_sp pch.asl to pickup the common block lpc.asl. This
allows deltalake to pick up any general pch asl updates. Currently,
generates the same asl.

Change-Id: I5005032b030d288fdf5ca2f99d21fe8e6c752037
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47304
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07 16:28:54 +00:00
Marc Jones 092245dfbb mainboard/ocp/tiogapass: Set longer BMC timeout
The BMC isn't always ready in 60 seconds if it printing debug output.
Give it 90 seconds to finish before timing out in coreboot.

Change-Id: I3932d3e8fad067e8971e82b45b499801fc78079f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Javier Galindo <javiergalindo@sysproconsulting.com>
2020-11-07 16:27:50 +00:00
Angel Pons a575759c40 sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled
Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and
setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF.
Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2.

However, current code doesn't account for this. The result is that
register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is
OBFF-capable but support is disabled, which makes no sense. Given that
reference code and Broadwell both disable OBFF, disable it here too.

Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-07 14:20:38 +00:00
Angel Pons 1464a05933 sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function
Change-Id: I957556bcb3f2d793ed2d9a9c966b2081f9be090c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47042
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07 14:20:10 +00:00
Angel Pons a7174b7c1d sb/intel/lynxpoint/lpc.c: Correct GPI routing check
Code does not match comment, but this time the comment is right.

Change-Id: I4e277a802c68c8a4e858b2e33e7ec69b41dd9773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47044
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07 14:19:44 +00:00
Angel Pons 244a425efd sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
Testing shows that these registers are backwards. Use the definitions
from Broadwell instead. All affected boards use the same value for both.

Change-Id: Ie47c9fddc2e9e15ce4c64821ea3a69356ac31b1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-07 14:19:34 +00:00
Angel Pons f47117134d sb/intel: Don't set ACPI_EN twice
It is already done once when enabling PMBASE in early init.

Change-Id: I14289c9164ee1488c192fce721d86c89fa5cc736
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-07 14:18:35 +00:00
Angel Pons 4b519f7c62 sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits
For all these southbridges, the lower nibble of PCICMD is read-only.

Tested on Asrock B85M Pro4 (Lynxpoint-H), LPC's PCICMD does not change.

Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-07 14:18:20 +00:00
Sridhar Siricilla 344a1bd43c mb/intel/adlrvp: Configure GPIOs to enable DMIC
The patch configures GPIO pins to enable DMIC.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2907737071f7d6b3c88c492d90edf8455d1fa50a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-11-07 08:56:05 +00:00
Sridhar Siricilla f2de1e7e19 mb/intel: Enable ALC711 Audio codec over SNDW0 link
The patch enables ALC711 Audio codec.

Test=Verified on ADL RVP.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I73f480dad1047cebd7ffc66e0104ff10cacc300b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-11-07 08:55:53 +00:00
V Sowmya 73caae9772 mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers
This patch enables TCSS xDCI, TBT PCIe root ports and DMA controllers
for ADLRVP.

BUG=b:170607415
TEST=Built and booted on ADLRVP.

Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47288
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07 08:55:15 +00:00
V Sowmya 14e34fb10b mb/intel/adlrvp: Configure the HPD GPIO's
This patch configures the HPD1 and HPD2 GPIO's.

BUG=b:170607415
TEST=Built and booted adlrvp. Verified the hotplug
functionality is working.

Change-Id: Ied2d4c56220212a15103e9a2fbd01ce6f0811a74
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-11-07 08:55:01 +00:00
Jonathan Zhang 9e0dd96e7e vc/intel/FSP2_0/CPX-SP: update to ww45 release and add watermark option
Intel CPX-SP FSP ww45 release annotates default values for FSP-M UPD
variables.

FSPM MemRefreshWatermark option support is present in FB's CPX-SP
FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP
FSP binary, this option takes the space of UnusedUpdSpace0[0].

For DeltaLake mainboard, if corresponding VPD variable is set, use it
to control the behavior. Such control is effective when FB's CPX-SP
FSP binary is used.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-07 00:12:35 +00:00
T Michael Turney 7bfef7d50c sc7180: Correct mmu configuration for AOP SRAM regions
NOC errors detected at runtime in AOP SRAM region
strongly suggested speculative memory accesses were occurring
in memory regions that either don't exist or are device memory
rather than SRAM.

Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Change-Id: I6611dc614c80063c7df057b59337417c8f56fd9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-11-06 22:34:25 +00:00
Felix Held ac2da047ac soc/amd/picasso: add Raven1 GPU PCI ID
Change-Id: Id4460eb596b080dec1a63a20869182170c3388af
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-06 19:59:54 +00:00
Felix Held 53c173e9ef soc/amd/picasso/cpu: add Raven1 CPUID to CPU table
The RV1 CPUID is already in the cpu.h file, but was still missing from
the CPU table in cpu.c.

Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-06 19:59:41 +00:00
Lucas Chen d8c189b669 zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board
Adjust USB2 phy si setting fine tune on DVT for Ezkinil.

BRANCH=zork
BUG=b:156315391
TEST=Measuring scope timing and test usb detection

Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-11-06 19:23:04 +00:00
Matt DeVillier ea4db9b8fb mb/purism/librem_mini: Set unused GPIO pads to PAD_NC
Set numerous pads to PAD_NC as per board schematics (they are either
NC, or connected to test pads), and adjust comments as needed.

Change-Id: I4c2ab936256d0031d7a127fbeac42c8951a0b39f
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-06 19:09:29 +00:00
Martin Roth 5632c6bc02 soc/amd/picasso: Set vboot hashing block size to 36k
On picasso's psp_verstage, the vboot hash is being calculated by
hardware using relatively expensive system calls.  By increasing the
block size, we can save roughly 150ms of boot and S3 resume time.

TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6642073357327811b415dcbcad6930ac6d2598f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06 18:53:05 +00:00
Martin Roth 03d06d3bcd soc/amd/picasso: Up stack size to 40k for vboot hash buffer
Increasing the vboot hash buffer size greatly speeds up the SHA
calculations.  Going from a standard 4k buffer to a 36k buffer
takes ~150ms of the boot and resume time.

TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibca868ad7be639c2a0ca1c4ba6d71123d8b83c92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46902
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06 18:52:49 +00:00
Wisley Chen 1597a21326 mb/google/volteer/var/elemi: Update gpio and devicetree
Update gpio and devicetree for elemi.

BUG=b:170604353
TEST=emerge-volteer coreboot and boot into kernel

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I5b8880d485ed73aa4e65c1249c58f02c8f0c6501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-06 18:35:16 +00:00
Wisley Chen 4efd7d9926 mb/google/variant/elemi: config CSE LITE
Config elemi to use CSE LITE

BUG=b:170604353
TEST=emerge-volteer coreboot

Change-Id: I31c7a743645d6a34ee34e750ba92c108b306ee09
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47019
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06 18:35:08 +00:00
Wisley Chen 5602945e9f mb/google/variant/elemi: Select USE_CAR_NEM_ENHANCED_V2 for elemi
BUG=b:170604353
TEST=emerge-volteer coreboot

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I1a1ab6f3d57d5023523b85bfb00d48d8b70a6c1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-06 18:34:59 +00:00
Martin Roth 8839b7f109 security/vboot: Add Kconfig symbol to set hashing block size
Generally, this size probably doesn't matter very much, but in the
case of picasso's psp_verstage, the hash is being calculated by
hardware using relatively expensive system calls.  By increasing the
block size, we can save roughly 140ms of boot and resume time.

TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I68eecbbdfadcbf14288dc6e849397724fb66e0b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-11-06 17:46:13 +00:00
Marc Jones 83729bd430 soc/intel/xeon_sp/skx: Fix MADT CPU indexes
The CPU index wasn't getting updated. Confirm MADT sets IOAPIC and CPU
ID numbers.

Change-Id: I72430cc48f4609ac408e723172ba1ed263cca8e3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-06 17:05:30 +00:00
Marc Jones 18960ce0c9 soc/intel/xeon_sp: Move CPU helper functions
Continue Xeon-SP de-duplication.
Move CPU helper functions from skx/ and cpx soc_util.c to common util.c.
Functions only used by util.c are updated to be static.

The following functions are moved:
 int get_threads_per_package(void);
 int get_platform_thread_count(void);
 const IIO_UDS *get_iio_uds(void);
 unsigned int soc_get_num_cpus(void);
 void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
 void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits,
   uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread);
 void xeonsp_init_cpu_config(void);

Change-Id: I118a451b9468459cf2c2194f31da1055e1435ebe
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47170
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06 17:00:14 +00:00
Marc Jones c6a6e54d05 soc/intel/xeon_sp/cpx: Reorder cpu.c .h includes
Clean up the header includes.

Change-Id: I9f61d1a82b37bc0ed803967dc64decf18f44adc9
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-11-06 16:59:33 +00:00
Zheng Bao af2efbb59b amdfwtool: Use shell command to get depend file list
The amdfwtool is not available at the beginning of the
building. So it may have error if it is missing.

Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-06 13:06:33 +00:00
Zheng Bao 795d73c6d8 soc/amd/picasso: Update coreboot UPD variable names to include units
Use command below to change the variable globally.

sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \
   --exclude-dir=build --exclude-dir=crossgcc`

BUG=b:171334623
TEST=Build

Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-06 13:02:24 +00:00
Kevin Chiu 0cae9008f0 mb/google/octopus/variants/garg: Add new LTE SKU
Add new SKU definition:
Garg360 (LTE DB,1A2C,TS, no stylus, rear camera) SKU ID - 39

BUG=b:170708728
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage

Change-Id: Ifec4e1360bd1aff3825bc6413b0a2ccd8b822075
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47015
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06 03:11:59 +00:00
Ravi Sarawadi d83e24d9d5 soc/intel/tigerlake: Disable C1 C-state Demotion
Disable C1 C-state auto demotion to decrease SoC power usage.

When set, processor will conditionally demote C3/C6/C7 requests
to C1 based on uncore auto-demote information.

BUG=b:161215906
TEST=Measure and confirm SoC power usage reduction for key use cases
 eg 'Google Meets video call'

Measured on instrumented boards for Volteer EVT and Delbin.

Below measurements for Volteer:

Google meets with 720p 	w/ auto-demotion   w/o auto-demotion
System Power 	        13.14W	              9.4W
SOC Power 	         7.9W	              5.4W

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Shweta Malik <shweta.malik@intel.com>
Change-Id: I649cafbaf03917d76521aa5f76ec58d218e1a1b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-05 22:58:27 +00:00
Felix Held 1032d22152 soc/amd/picasso: move MAX_CPUS setting from mainboard to SoC Kconfig
Since the mainboard Kconfig is sourced before the SoC one, it would
still be possible to override this setting at mainboard level, even
though that shouldn't be needed. The maximum CPU count for Picasso is 8,
since the chips have only up to 4 cores with up to two threads each.

Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05 19:57:14 +00:00
Karthikeyan Ramasubramanian b5d9f4a1cf ec/google/chromeec: Remove the check for Internal TypeC MUX
Integrated TypeC MUX is used only in certain SoCs and hence the missing
devicetree configuration is not an error. Remove the check for internal
TypeC MUX device and the associated debug statement.

BUG=b:172186858
TEST=Build and boot to OS in Drawlat.

Change-Id: Ieb76e1ccfd04f1628617b2665b05be6718a25f81
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-05 19:06:31 +00:00