decide whether the option ROM is a special VGA type.
An S3 card that I've got has the wrong class in the VGA BIOS.
(A Stealth 64 DRAM T PCI, from 1994 - BIOS V2.02)
Signed-off-by: Mark Marshall <mark.marshall@csr.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Declare superio functions to be static and remove duplicates.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
here. I think we don't ever want to drop the extra check, since it indicates
that the components involved need fixing.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Add static and const where possible.
- Turn some #warning entries into TODO comments.
- Add missing prototypes.
- Remove unused variables.
- Fix printf arguments or cast them as needed.
- Make sconfig output look better. Drop useless "PARSED THE TREE" output.
- Print "(this may take a while)" while building romcc. Add missing "\n".
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watosn <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
TODO
- x86emu need (imo) some common header with prototypes at least
- clog2, ulzma, hardwaremain prototypes added by this patch probably should
be moved to some header too.
- in src/devices/device_util.c prototype is before function because seems,
it is used only within same file, if not it should be moved to debug
section of prototypes in include/device/device.h
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
level output and make some output SPEW only.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Update the code to support that too.
Remove an unused variable.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Add helps texts to multiple user-visible Kconfig options.
- Improve some menu and option names.
- PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down
(instead of up) when changing "no payload" to "ELF payload" (more
intuitive, IMHO).
- s/cbfs/cbfstool/.
- Add some TODO items where needed.
- Put GDB_STUB in a "Debugging" menu, no options should be top-level.
There'll be more debug options later, I'm pretty sure.
- Start converting help texts which are not user-visible to #-comments.
- Re-order some options for more intuitive menus.
- Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them.
- "Maximum reboot count" should proabably not be user-selectable, or at
most if CONFIG_EXPERT (yet to be added) is enabled. It does definately
not need its own "Misc options" menu.
- Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to
run option ROMs.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- CONFIG_CBFS
- anything that's conditional on CONFIG_CBFS == 0
- files that were only included for CONFIG_CBFS == 0
In particular:
- elfboot
- stream boot code
- mini-filo and filesystems (depends on stream boot code)
After this commit, there is no way to build an image that is not using
CBFS anymore.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/socket_F/Kconfig: Remove second occurrence of CPU_SOCKET_TYPE.
src/mainboard/amd/serengeti_cheetah/Kconfig: Add HT_CHAIN_UNITID_BASE here, since it is board specific.
src/mainboard/tyan/s289X/Kconfig: Fix typo and change APIC_ID_OFFSET to match old config.
src/devices/Kconfig: Change default value of *_PLUGIN_SUPPORT to match old config.
src/southbridge/amd/amd8131/Makefile.inc: Remove check since it was a typo, and the correct variable is checked in the parent directory.
src/Makefile:Use devicetree.cb instead of Config.lb to generate static.c.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
during early coreboot_ram), pci_{read,write}_config{8,16,32} will die().
This patch changes pci_{read,write}_config{8,16,32} to use the existing
PCI access method autodetection infrastructure instead of die()ing.
Until r4340, any usage of pci_{read,write}_config{8,16,32} in
coreboot_ram before the device tree was set up resulted in either a
silent hang or a NULL pointer dereference. I changed the code in r4340
to die() properly with a loud error message. That still was not perfect,
but at least it allowed people to see why their new ports died.
Still, die() is not something developers like to see, and thus a patch
to automatically pick a sensible default instead of dying was created.
Of course, handling PCI access method selection automatically for
fallback purposes has certain limitations before the device tree is set
up. We only check if conf1 works and use conf2 as fallback. No further
tests are done.
This patch enables cleanups and readability improvements in early
coreboot_ram code:
Without this patch:
dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0x64);
With this patch:
dword = pci_read_config32(sm_dev, 0x64);
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
more rational places. The goal is to reduce the number of Config
variables defined in mainboard Kconfig files to the absolute minimum.
This has the side effect of making SERIAL_POST a menu item, which is nice.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
resources before actually validating if the resource is
a fixed one.
No harm done, except some confusion of the user (in this case: me).
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Whitespace fixes, remove trailing whitespace, use TABs for identation
(except in Kconfig "help" lines, which start with one TAB and two spaces
as per Linux kernel style)
- Kconfig: Standardize on 'bool' (not 'boolean').
- s/lar/cbfs/ in one Kconfig help string.
- Reword various Kconfig menu entries for a more usable and consistent menu.
- Fix incorrect comment of NO_RUN in devices/Kconfig.
- superio/serverengines/Kconfig: Incorrect config name.
- superio/Makefile.inc: s/serverengine/serverengines/.
- superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/.
- mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string.
- mainboard/via/epia-n/Kconfig: Fix "bool" menu text.
- console/Kconfig: Don't mention defaults in the menu string, kconfig
already displays them anyway.
- Kill "Drivers" menu for now, it only confuses users as long as it's emtpy.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
example of one.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Works on Kontron, qemu, and serengeti.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
tested on abuild only.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
more flexible. Also some minore device allocator cleanups that sneaked
in.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The major change is that the K8 registers don't get touched until the end of
resource allocation.
Fam10 code could be updated the same way.
Move VGA code before resource allocation but after device enumeration.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Major changes:
1. Separate resource allocation into:
A. Read Resources
B. Avoid fixed resources (constrain limits)
C. Allocate resources
D. Set resources
Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources. All fixed resources will end up outside (above or below)
the allocated resources.
Domains usually start with base = 0 and limit = 2^address_bits - 1.
I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources. Some platforms may want to change that, but I didn't
want to break anyone's board.
Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
if it is already in its correct location.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Any endless loop after die() can be eliminated.
Dereferencing a NULL pointer is bad. die() instead.
Replace endless loops with die().
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Last commit broke it due to leftover "void" from prototype.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This code brings a rather complete set of VGA IO routines for whoever wants it.
These consist of the by now familiar read/write/mask sets. Due to the crazy
nature of VGA, an ancient standard with bits all over the place, it makes no
sense to define individual registers. You need a vga register spec at hand if
you want to do anything anyway. These IO routines are always exposed.
It also provides code to natively set up a 640x400 VGA textmode with an 8x16
font. The native VGA mode code is behind the OPTION_VGA option, as the font
really adds to the size of the compiled/compressed rom. The font is the one
also present in the linux kernel, but this file is unlicensed. Another copy of
this is also present in coreboot in the deprecated console/btext code.
The vga console code has been cleaned up, but it still has some TODO's left
open, but that's for when i finally have found the remaining issue with the
epia-m. Right now, it is important to get parts of my work out already and to
make the remainder managable again.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- drop dead code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This also has the config tool changes in v2/util.
Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- don't make users pick the name. Names for option roms are in the v3-defined
format of pci%04x,%04x.rom with the vendor and device id filling in the
%04x.
- users pass in vendor and device id.
- users pass in a dest. If the dest is 0, the address of the ROM image in
FLASH is returned. If the address is non-zero, then the decmpressor is called,
and it will make sure the ROM image is copied to the destination (even
in the uncompressed case).
move qemu over to always using ROMFS
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Pretty simple: Find the rom in the romfs, if found, set dev properties so
that the rest of the code works.
At some point, we can remove some of the other code, i.e. the first else,
and stop requiring people to do math.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
memory must be clear with 0s because otherwise the resources of K8 will be
totally messed up.
res = probe_resource(dev, 0x100 + (reg | link));
This is called with dev = NULL and this is no good for probe_resource at all.
The attached patch fixes the potential problems and of course the problem
itself. On one particular place was missing test if the device really exists.
This was copied to fam10 and perhaps the same issue is in v3 (DID NOT check).
The rest of the patch is just very paranoid and do all checkings.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>
--This line, and those below, will be igno
red--
M src/devices/pci_ops.c
M src/northbridge/amd/amdk8/northbridge.c
M src/northbridge/amd/amdfam10/northbridge.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
horribly broken and thus never used by any platform. This needs to get
straightened out so current chipsets drivers can use the full feature set.
Create wrapper functions similar to the io pci config space ones.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
doesn't make no sense. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
with nonzero PCI bus operations, get_pbus() will get stuck in a silent
endless loop.
Detect the endless loop and break out with an error message.
Such a situation can happen if the device tree is not yet
initialized/walked completely.
This fixes the unexplainable hang if pci_{read,write}_config{8,16,32}was
used in early mainboard code for the AMD DBM690T. Instead, the code will
now die() with a meaningful error message.
Thanks to Ward Vandewege for testing my patches to track down that bug.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
sense, too). Have one u64 instead of three.
In order to use the old bios emulator, you have to do nothing. (Default, if
CONFIG_PCI_ROM_RUN is enabled)
In order to use yabel in your target, you need to add the following lines to
your config:
uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1
In order to use vm86 in your target, you need to add the following lines to
your config:
uses CONFIG_PCI_OPTION_ROM_RUN_VM86
default CONFIG_PCI_OPTION_ROM_RUN_VM86=1
Note: vm86 only works on platforms with _RAMBASE in the lower megabyte.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
hence I consider it trivial in this case). This does not include the Yabel
work.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- leave a hole for mmapped PCIe config space if CONFIG_PCIE_CONFIGSPACE_HOLE
is set.
- Mask moving bits to 32bit when resources are not supposed above 4G. Linux
does not like this, even though the resource is disabled.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Use dev_path() to have nice debug output
patch is run-time tested
Trivial, thus:
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
drove me crazy during debugging. Fix Typos. Add a warning because the
on-chipset devices are hardcoded. For newer machines, a lot more memory space
will have special meanings, and we can't hardcode them all in an ifdef desert.
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
no VGA output from coreboot, even after the boot-rom was executed
properly (CONFIG_PCI_ROM_RUN) or no boot-rom execution with
CONFIG_VGA_ROM_RUN at all. According to the header file device.h, the
class field of struct device is '3 bytes: (base,sub,prog-if)'.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Torsten Duwe <duwe@lst.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
undefined u8 type and the bitpos selection in currently unused
pnp_read_enable function.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
mine W83627EHF.
This patch introduces a concept of virtual LDN. Each virtual LDN is unique, but
maps to original LDN and bit position in register 0x30.
VirtualLDN = origLDN[7:0] | bitpos[10:8]
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
rather independent, lift the implicit (broken) assumption that
CONSOLE_VGA would also run the ROMs, and transfer it to a new
config option VGA_ROM_RUN.
This change is minimally intrusive, because all board configs
that previously assumed CONSOLE_VGA would also run the ROMs
didn't compile, they had to also specify PCI_ROM_RUN.
Based on patches by Ron Minnich (fix the compile) and Luc Verhaegen
(separate ROM_RUN from VGA console).
Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It is platform specific.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
For example: in C51/MCP55 or C51/MCP51
Will allow
1. C51 at 0x10 to 0x14, and MCP at 0 to 4
2. C51 at 1 to 4, and MCP at 7 to 0x0a
The reason is c51/mcp51/mcp55 reported unitid is 0x0f (far beyond it
needed), and will prevent us from putting them on bus 0.
Typical values for c51/mcp55 or c51/mcp51:
HT_CHAIN_UNITID_BASE = 0x10 # for C51
HT_CHAIN_END_UNITID_BASE = 0 # for mcp
If only have mcp with c51,
HT_CHAIN_UNITID_BASE = 0 # for MCP
#HT_CHAIN_END_UNITID_BASE = 0 # default value 0x20
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(SMSC) Super I/O chips.
Most of the SMSC Super I/O chips seem to be similar enough (for our
purposes) so that we can handle them with a unified driver.
So far only the ASUS A8000 has been tested on real hardware!
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
devices conflicting with the northbridge devices on PCI bus 0.
Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
For files derived from the Linux kernel we merely add a small header
which states the origin of the file and the copyright owners of the
modifications to the file.
We know all files from Linux are licensed under the GPLv2.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
when CONFIG_CONSOLE_VGA==0 and CONFIG_PCI_ROM_RUN==1
Signed-off-by: Roman Kononov <kononov@dls.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
this fix, LinuxBIOS crashes if the CONSOLE_LOG_LEVEL is high enough.
Additionally, The VGA option rom will be executed if either
CONFIG_PCI_ROM_RUN=1 or CONFIG_CONSOLE_VGA=1.
Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
un-inited vector, which we should have done.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
add devices for the lx and artecgroup/dbe61
point artecgroup at cs5536_lx as it is so different.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
manage them. Make pci_level_irq global. Add value settings for OLPC
rev_a board. Comment out no-longer-needed code in olpc mainboard.c
-- it is replaced by the settings in Config.lb, and the support
in cs5536.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- some ts5300 code. Let's push this upstream for now.
- fix a typo in device.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
provide more information. The printk_debug in that failure case is now
a printk_error.
The msm stuff is for debugging.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
store every HT device unit id base and pass those info to acpi
https://openbios.org/roundup/linuxbios/issue46
Note: This version drops the two scripts a and c and creates the dsdt on
the fly from Config.lb using makerule
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Li-Ta Lo <ollie@lanl.gov>
Correct VGA support
Make the VGA support for both VGA and no VGA cases.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Li-Ta Lo <ollie@lanl.gov>
missing commit for emulator update
Which one is more stupid? TLA or me?
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Li-Ta Lo <ollie@lanl.gov>
TLA sucks again
This is the third time I try to commit only the emulator changes.
I hope this patch contains the emulator changes only.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
x96emu update from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
Correction to the reduce emulator from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Yinghai Lu <yhlu@tyan.com>
AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- The sandpointx3+altimus has been consolidated into one directory for now.
- Added support for having different versions of the pci access functions
on a per bus basis if needed.
Hopefully I have not broken something inadvertently.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
- Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
- ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
- Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
- Start using romcc's built in preprocessor (This will simplify header compiler checks)
- Add helper functions for examining all of the resources
- Remove debug strings from chip.h
- Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
- Add the ability to catch exceptions on x86
- Add gdb_stub support to x86
- Removed old cpu options
- Added an option so we can detect movnti support
- Remove some duplicate definitions from pci_ids.h
- Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
- Minor romcc bug fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- mem.h and sizeram.h and all includes killed because the are no longer needed.
- linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
- first very incomplete stab a converting the ppc code to work with the dynamic device tree
- Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
- First stab at Pentium-M support
- add part/init_timer.h making init_timer conditional until there is a better way of handling it.
- Converted all of the x86 sizeram to northbridge set_resources functions.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
