Commit Graph

9123 Commits

Author SHA1 Message Date
Martin Roth 7b5f8ef2ea arch: Fix spelling
Change-Id: Ifea10f0180c0c4b684030a168402a95fadf1a9db
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3727
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:16:25 +02:00
Gabe Black fb370130f6 ARM: Fix the way the space for the page tables is allocated.
The page tables need to be aligned to a 16KB boundary and are 16KB in size.
The CBMEM allocator only guarantees 512 byte alignment, so to make sure
things are where they're supposed to be, the code was allocating extra space
and then adjusting the pointer upwards. Unfortunately, it was adding the size
of the table to the pointer first, then aligning it. Since it allocated twice
the space of the table, this had the effect of moving past the first table
size region of bytes, and then aligning upwards, pushing the end of the table
out of the space allocated for it.

You can get away with this if you push things you don't care about off the
end, and it happened to be the case that we were allocating a color map we
weren't using at the start of the next part of cbmem.

Change-Id: I6b196fc573801b02f27f2e667acbf06163266651
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3651
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:11:32 +02:00
Gabe Black 63dd2cb62a exynos5250: When enabling the I2S pins, turn off pull ups/downs.
These pins will be driven by the internal controller which shouldn't have pull
ups or downs in the pin fighting with them.

Change-Id: I579aed84ace45d8f5f1d3ca64c064d98de842b57
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3649
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:10:12 +02:00
Gabe Black ea9c98d454 exynos5420: Replace the 5250 GPIO code with code that should work on 5420.
Change-Id: Iac6615240e94c74037afc801169c32d3ebc4ac03
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:09:54 +02:00
Stefan Reinauer 919c804425 ARMv7: Clean up console code
- Guard console_init() with CONFIG_EARLY_CONSOLE in bootblock
 - Don't initialize console twice in the bootblock
 - remove printk in memory init that would mess up the UART
 - unconditionally run console_init() in romstage, as it is
   also unconditionally run in the bootblock.

Change-Id: I8f0d60877433162367074d0e55e01f935fd81f8e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3647
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:09:42 +02:00
Gabe Black d3163abd43 pit: Add a "pit" mainboard which is mostly a copy of "snow".
This change adds a pit mainboard which is mostly a copy of snow, except that
mentions of the 5250 were replaced with the 5420, and mentions of snow were
replaced with pit.

Change-Id: I8eb0ce379eb2fa353bb88d5656a0c5e2290afbf0
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:09:21 +02:00
Gabe Black b2d811aa9e pit: Fix some settings for the exynos5420 CPU.
Some of the settings which were defaulted to or automatically selected for the
exynos5420 which were inherited from the exynos5250 were not correct for this
SOC.

Change-Id: I11ffd8a6b80628405ac493fe2139f79c05d15d7e
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3645
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:09:07 +02:00
Gabe Black 607c0b6d63 pit: Create an exynos5420 directory which is nearly a copy of exynos5250.
This change creates an exynos5420 directory with code that will eventually
implement support for the exynos5420 cpu from Samsung. Currently it's a copy
of the exynos5250 directory with the name changed. There are going to be some
problems where headers in src/cpu/samsung/exynos-common include headers in the
exynos5250 directory directly.

Change-Id: Ia8d7244310d32499238bbc171c0c668ec48178e1
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3644
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:08:53 +02:00
Stefan Reinauer dc006c1db4 ARMv7: De-uboot-ify Exynos5250 GPIO code
The Exynos GPIO code has three different APIs that, unfortunately,
were widely used throughout the code base. This patch is cleaning
up the mess.

Change-Id: I09ccc7819fb892dbace9693c786dacc62f3f8eac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3643
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:08:29 +02:00
Stefan Reinauer 08dc357146 ARMv7: De-uboot-ify Exynos5250 code
When starting the Exynos5250 port, a lot of unneeded u-boot code
was imported. This is an attempt to get rid of a lot of unneeded
code before the port is used as a basis for further ARM ports.

There is a lot more that can be done, including cleaning up the
5250's Kconfig file.

Change-Id: I2d88676c436eea4b21bcb62f40018af9fabb3016
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3642
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:08:15 +02:00
Stefan Reinauer f73de9b975 Update 3rdparty hash for latest ARM BL1 binaries
Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3740
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-07-10 03:02:05 +02:00
Christoph Grenz 2cccacff90 w83627hf/acpi: Fix endianess error in floppy drive enumeration code
The enumeration results are stored as five DWORDs in one 20 byte buffer.
Bytes 3, 7, 11 and 15 were used to set the lowest bit of each DWORD.
ACPI uses little endian, so 1, 4, 8 and 12 are the correct indices.

Change-Id: I793225cb1bb62fd148ecfa1e61e02f5d7be62cdb
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3602
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-10 02:54:01 +02:00
Stefan Reinauer b98dec032f samsung/exynos5250: unify code
It turns out that the exynos5-common code previously imported from
u-boot is not common code at all but very specific to the 5250 and
not compatible with the 5450. Hence, unify the directories exynos5250
and exynos5-common. We will try to factor out common code while
progressing with the 5450 port.

Change-Id: Iab595e66fcd01eda8365c96fb8bef896f7602f03
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3641
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:41:23 +02:00
Stefan Reinauer 043eb0e35f Wield battle axe at ARM port
This patch unfortunately incorporates a number of changes,
all of which are making future ARM ports easier.

 - drop cruft that came in with u-boot
 - move serial console from mainboard Kconfig to Exynos Kconfig
 - factor out non-board specific wakeup code
 - move generic bootblock code from mainboard to Exynos
 - actually call arch_cpu_init()
 - remove dead code
 - fix up copyright messages
 - remove snow_ prefix from a lot of code to reduce the noise
   when creating a new mainboard based on that code.

Change-Id: Ic05326edf5a7e1a691c5ff841a604cb9e351b562
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3640
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:41:09 +02:00
Stefan Reinauer 6adef0847e Rename hardwaremain() to main()
... and drop the wrapper on ARMv7

Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3639
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:40:30 +02:00
Stefan Reinauer 2ae6d6f6de ARMv7: normalize ramstage code flow
In ram stage, all code flow should be tied to the resource allocator.
Stuff that has to happen before everything else goes into the mainboard
enable function in mainboard.c. This patch empties the main() wrapper
around hardwaremain.c, allowing to get rid of this special case in the
ARM port.

Change-Id: Ide91a23f1043b64acf64471f180a2297f0f40d97
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3638
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:40:17 +02:00
Ronald G. Minnich 78c3e33550 FUI: reorganize include files
We've got enough of a handle on this to realize some things:
drm_dp_helper.h is by design device and architecture independent
i915.h is common to most intel graphics chipsets going back several years
i915_reg.h is as well

Move these files to src/include/device, and adjust the .c files accordingly.

Change-Id: I07512b3695fea0b22949074b467986420783d62a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3637
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:39:42 +02:00
Ronald G. Minnich b2893a0169 Provide support for setting up the framebuffer from EDID
Add three functions to edid.c:

void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
takes an edid and uintptr_t, and fills in a static lb_framebuffer struct
as well as setting the static vbe_valid to 1 unless some problem
is found in the edid. The intent here is that this could be called from
the native graphics setup code on both ARM and x86.

int vbe_mode_info_valid(void)
returns value of the static vbe_valid.

void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
copies the static edid_fb to lb_framebuffer.

There is now a common vbe.h in src/include, removed the two special ones.

In general, graphics in coreboot is a mess, but graphics is always a
mess.  We don't have a clean way to try two different ways to turn on
a device and use the one that works. One battle at a time. Overall,
things are much better.

The best part: this code would also work for ARM, which also uses EDID.

Change-Id: Id23eb61498b331d44ab064b8fb4cb10f07cff7f3
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3636
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:39:28 +02:00
Gabe Black 3fb30eeb14 ChromeEC: Fix the default, depends for EC_GOOGLE_CHROMEEC_I2C.
The default for this variable should be n, it should only depend on
EC_GOOGLE_CHROMEEC, and it should be (and is) explicitly enabled when
needed. This prevents it from being turned on when the EC bus is SPI.

Change-Id: Idc6651a764be4f055341a36b9b4a58990f050b0c
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3737
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:38:55 +02:00
Kyösti Mälkki 54d6abd276 Drop some duplicates of PCI-e config functions
These are not specific to Intel. Further work needs to be done to
combine these with MMCONF_SUPPORT in arch/io.h.

Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 01:24:42 +02:00
Kyösti Mälkki 872c922296 Fix MMCONF_SUPPORT_DEFAULT for ramstage
Define at one place whether to use IO 0xcf8/0xcfc or MMIO via
MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage.

The implementation of pci_default_config() always returned with
pci_cf8_conf1. This means any PCI configuration access that did
not target bus 0 used PCI IO config operations, if PCI MMIO config
was not explicitly requested.

Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3606
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-10 00:57:09 +02:00
Denis 'GNUtoo' Carikli 20b6d91fd3 southbridge/intel/i82801gx: Make compilation possible with CONFIG_SMM_TSEG
Without that fix, and with CONFIG_SMM_TSEG, we have:
  src/southbridge/intel/i82801gx/smihandler.c: In function 'southbridge_smi_sleep':
  src/southbridge/intel/i82801gx/smihandler.c:340:3: error: implicit declaration of function 'smi_release_lock' [-Werror=implicit-function-declaration]
  cc1: all warnings being treated as errors
  make: *** [build/southbridge/intel/i82801gx/smihandler.smm.o] Error 1

The fix is modelled after src/cpu/x86/smm/smihandler.c which
  ifdefs smi_release_lock().

Change-Id: Icdc6d039b34a1d95d0e607419bba2484d21abc5e
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3281
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 00:54:03 +02:00
Denis 'GNUtoo' Carikli 1b32a51e51 i82801gx: smihandle: sync with southbridge/intel/bd82x6x/smihandler.c
Change-Id: Ic725b169061bd426aa8206dc1d6d31e67cc639f2
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3304
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 00:53:17 +02:00
Denis 'GNUtoo' Carikli b694f10c00 southbridge: i82801gx: smihandler.c: Correct outl->outw mistake.
This mistake was spoted by comparison with the
  src/southbridge/intel/bd82x6x/smihandler.c file.

Change-Id: I1516f0131d524bd7d001e6780e9a45402d1814d1
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3303
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 00:52:20 +02:00
Nico Huber d1fb5641b6 sandybridge: Add option to lock SPI regions on resume
Add an option to mark all SPI regions write protected on each S3 resume.
We were used to lock the SPI interface in the payload which isn't run on
the resume path. So we have to do it here.

For the write protection to be effective, all write opcodes in the
opmenu have to be marked correctly (as write operations) and the whole
SPI interface has to be locked. Both is already done.

Change-Id: I5c268ae8850642f5e82f18c28c71cf1ae248dbff
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3594
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 00:48:33 +02:00
Ronald G. Minnich 4f78b18749 fox_wtm2: First step support for coreboot-based graphics startup
This code is the initial version of FUI for haswell and wtm2.

The code is simplified from before in many ways. I've gotten rid of
the opcode table, because it obscured meaning and I don't think it is
needed any more. Register sets, mainly used for reset, are just lines
of code -- not many of them. There are a bunch of not-yet-documented
registers here; the VBIOS seemed to think they were necessary and
testing shows they seem to be right.

As a bit of added paranoia, we always include the VBIOS code as our
emergency recovery path. You have to run it now anyways, so this is no
regression from our current situation; and, if all goes well, in a
week (or so), you'll never have to run it again, but like the Force
and nose hair, it will be with you always.

The code can return in three ways. The first, best way is success:
panel is up and the VBIOS need not run. The second mode is that we
tried to light up the panel but could not, for some reason, but will
return with the panel partly up. In this case, it's ok not to power
cycle the panel. The third, worst case, which will NEVER happen, ha
ha, is that we have to turn the panel off and wait the required 600ms
for it to cycle. Life sucks sometimes. This failure mode is in the
'hang on we're going to fix it' category now that we have ramstage in
RW.

The Big Goal here is to create something other coreboot ports can use
as well. The guys doing the x60 report that the link FUI works,
without too many mods, on that chipset, so it seems Intel is keeping
things from changing too much over time.

Also, again, please note: this and the next 3 versions will ALWAYS fail.
The goal is to verify the correctness of the recovery path.

The bizarre tab-space formatting in drm_dp_helper.h is from the original,
as in i915_reg.h

Change-Id: I6ecf454633029d185c29d470980b5a0f3114a8ce
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-09 22:16:37 +02:00
Ronald G. Minnich 2a66d6b804 FOX_WTM2: First pass at FUI.
This lights up the display. We don't get graphics but we are missing the gttsetup
at this point, so that is no shock. The real shock is that anything works at all.

Change-Id: I03fc470334e96878aeb8465044b3cc9c90378735
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-09 22:16:09 +02:00
Benoît Legat f42b83e958 msrtool: Fix verbose ignored by cpuid().
This is a trivial patch moving cpuid() call after reading argv
so that verbose is set.

Change-Id: Ic621191ef650495614a041413c1a0f707d4469e6
Signed-off-by: Benoît Legat <benoit.legat@gmail.com>
Reviewed-on: http://review.coreboot.org/3627
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-08 19:39:00 +02:00
Andrew Wu 49f620221a Fix Vortex86EX devicetree.cb indentation.
Change-Id: If357b55b91618ee2438e6c6b2efb7018c56d26d0
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3628
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-08 17:35:49 +02:00
Peter Stuge d0b04003d0 Revert "Radio and dock support in EC on X60 and X201"
This reverts commit 7d1ebbff5a

Change-Id: I4a9d0cd31a3df3d1e092193953f334697ca65167
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3616
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-08 06:18:50 +02:00
Gabe Black 8cfa33eb7c am335x: Implement support for the UART.
This patch was started by Dave Hendricks and implements the procedure for
setting up the UART as described in the manual. Some unused code was removed.

Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3490
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-07-06 00:46:18 +02:00
Andrew Wu 8522f9940a Add support for DMP Vortex86EX PCI mainboard.
Change-Id: I8d42f765519e356d8f0cc6ed339d9b74f0a3e4d7
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3610
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-05 21:39:14 +02:00
Nico Huber f66dd6966a w83627hf/acpi: Fix offset of logical device activation
The PnP's logical device activation normally resides at 0x30. This might
have been overlooked as 0x29 looks very close to 0x30 in human eyes.

Change-Id: Id5d5a92f2683ebe1808b943f686c062151d216da
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-04 11:28:11 +02:00
Christoph Grenz 0bd5dff58c w83627hf/acpi: Fix type error in floppy drive enumeration code
The enumeration method tried to evaluate an one-byte OperationRegion
instead of a field in this OperationRegion, which resulted in an
AE_TYPE error at runtime.
Indexing the OperationRegion with a single field fixes this error.

Change-Id: I15dd7aa6ecafb3a215d165d2b721003446815025
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3603
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04 05:15:41 +02:00
Kyösti Mälkki 9e974232e4 intel/i5000: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on two boards
with i5000 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.

Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04 03:10:22 +02:00
Kyösti Mälkki 575e6817e6 Move select MMCONF_SUPPORT under northbridge (fix)
I missed the board with gm45 when I moved MMCONF_SUPPORT lines.

Also, the intel/i3100 does not have MMCONF_SUPPORT implemented
even though it was previously selected for intel/eagleheights board.

Change-Id: I9c7f6b0a150b4d54288a1e015277b9d98467fca4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3598
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04 03:06:53 +02:00
Kyösti Mälkki 032c23db08 intel/i945: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards
with i945 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.

Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3584
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-04 00:53:39 +02:00
Kyösti Mälkki fbdb085549 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards
with SandyBridge and IvyBridge. To enable MMIO style access,
add explicit PCI IO config write in the bootblock.

Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3576
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-04 00:53:06 +02:00
Kyösti Mälkki 15c4ab7adf Move select MMCONF_SUPPORT under northbridge
Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as
that feature originates from northbridge and cannot be disabled
for a single mainboard.

Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3589
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03 19:34:11 +02:00
Andrew Wu 00bf647bf6 Add support for DMP Vortex86EX PCI southbridge.
Change-Id: Iad11cb1b22e9d1e2953b12221541b1478cad9665
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03 18:31:22 +02:00
Nico Huber dd94fa93b4 winbond/w83627dhg: Fix logical device power down in ACPI
The W83627DHG has some power managements bits to power down individual
logical devices. These are called `* Power Down`. Counterintuitively and
in contrast to `Immediate Power Down` (bit to power down the whole chip),
these bits are set when the respective logical device is powered.

Unfortunately, our ACPI code set them wrong which led to disabled
devices after a S3 suspend/resume. Adding an option how to set the PM
bits and setting them to zero for the W83627DHG, corrects it.

Tested with kontron/ktqm77.

Change-Id: I8a472d480d4277721bd17c9f7c2ce44fa84e8ae2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3590
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03 17:58:20 +02:00
Nico Huber 1c81128dcd pnp: Add some default functions to enter/exit config state
Implement some common default functions to enter and exit the
configuration state. Also provide default pnp_mode_ops for common
enter()/exit() function pairs.

The following cocci ensures their use:
    @ mode_match @
    identifier enter, exit, ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = enter,
             .exit_conf_mode   = exit,
     };

    @ enter_match_8787 @
    identifier mode_match.enter, dev;
    @@
     enter(...)
     {
             outb(0x87, dev->path.pnp.port);
             outb(0x87, dev->path.pnp.port);
     }

    @ depends on enter_match_8787 @
    identifier mode_match.enter, mode_match.ops;
    @@
     struct pnp_mode_ops ops = {
    -        .enter_conf_mode  = enter,
    +        .enter_conf_mode  = pnp_enter_conf_mode_8787,
     };

    @ enter_match_55 @
    identifier mode_match.enter, dev;
    @@
     enter(...)
     {
             outb(0x55, dev->path.pnp.port);
     }

    @ depends on enter_match_55 @
    identifier mode_match.enter, mode_match.ops;
    @@
     struct pnp_mode_ops ops = {
    -        .enter_conf_mode  = enter,
    +        .enter_conf_mode  = pnp_enter_conf_mode_55,
     };

    @ depends on enter_match_8787 || enter_match_55 @
    identifier mode_match.enter;
    @@
    -enter(...) {...}

    @ exit_match_aa @
    identifier mode_match.exit, dev;
    @@
     exit(...)
     {
             outb(0xaa, dev->path.pnp.port);
     }

    @ depends on exit_match_aa @
    identifier mode_match.exit, mode_match.ops;
    @@
     struct pnp_mode_ops ops = {
    -        .exit_conf_mode   = exit,
    +        .exit_conf_mode   = pnp_exit_conf_mode_aa,
     };

    @ depends on exit_match_aa @
    identifier mode_match.exit;
    @@
    -exit(...) {...}

    @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @
    @@
     #include <device/pnp.h>
    +#include <superio/conf_mode.h>

    @ mode_match_55_aa @
    identifier ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = pnp_enter_conf_mode_55,
             .exit_conf_mode   = pnp_exit_conf_mode_aa,
     };

    @@
    identifier mode_match_55_aa.ops;
    @@
    -struct pnp_mode_ops ops = {...};

    @@
    identifier mode_match_55_aa.ops, devops;
    @@
     struct device_operations devops = {
    -        .ops_pnp_mode     = &ops,
    +        .ops_pnp_mode     = &pnp_conf_mode_55_aa,
     };

    @ mode_match_8787_aa @
    identifier ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = pnp_enter_conf_mode_8787,
             .exit_conf_mode   = pnp_exit_conf_mode_aa,
     };

    @@
    identifier mode_match_8787_aa.ops;
    @@
    -struct pnp_mode_ops ops = {...};

    @@
    identifier mode_match_8787_aa.ops, devops;
    @@
     struct device_operations devops = {
    -        .ops_pnp_mode     = &ops,
    +        .ops_pnp_mode     = &pnp_conf_mode_8787_aa,
     };

Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3484
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-03 16:13:11 +02:00
Paul Menzel abe6847cd2 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`
Use the same indentation, comment placement and spelling of words.
Run `indent -linux …`.

Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3220
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-02 21:07:44 +02:00
Dave Frodin 59158b2fb0 Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900
The MAX_PIRQ_LINKS is defined in src/Kconfig with a default value
of 4. The src/northbridge/via/vx900/Kconfig also defines
MAX_PIRQ_LINKS with a default of 8 and it ends up giving us
a value of 8 for non-VIA platforms.

Change-Id: Iee1938d38a93ab7c35c8cb6fe9656a92cf3fa21e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3586
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-02 16:24:04 +02:00
Christoph Grenz dda4095101 w83627hf: Add comments about parallel port modes in superio.asl
Add comments in PAR0._PRS explaining which dependent resource
descriptor puts the parallel port into EPP or SPP mode.

Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3495
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-01 23:22:41 +02:00
Stefan Tauner e978fc265d cbmem: Fix makefile
The .dependencies rule did not use the CPPFLAGS variable which led
to funny behavior: a spurious termination message the first time
(after checkout/make distclean) one executes make. Afterwards the
(wrongly) empty .dependencies file hides the problem and the binary
is created anyway.

$ make
cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory
compilation terminated.
cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
cc   cbmem.o   -o cbmem

$ make
make: Nothing to be done for `all'.

$ make clean
rm -f cbmem *.o *~

$ make
cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
cc   cbmem.o   -o cbmem

$ make distclean
rm -f cbmem *.o *~
rm -f .dependencies

$ make
cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory
compilation terminated.
cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
cc   cbmem.o   -o cbmem

I fixed that by adding the CPPFLAGS variable to the .dependencies recipe, just
like Stefan Reinauer did in Chromium (Ia9d2e10a3ef122f30d681d16c2291eb108ead835),
hence the split sign-off for this tiny change. :)

Change-Id: Icd11b146ad762cbdf9774630b950f70e1253a072
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3548
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-01 23:12:22 +02:00
Gabe Black 595ab4f955 beaglebone: Enable the clocks and pins for the configured UART.
Set up the pinmux to enable the pins and the clocks for whichever UART is
currently configured.

Change-Id: Iac13f16d9d84320555b99734ea83eafd0a2803fe
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3573
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-01 21:31:46 +02:00
Gabe Black 94f631cdc9 am335x: Fix the address of the pinmux registers.
The pinmux register data structure describes a subset of the control module
registers, but the address which pointed to the base of the pinmux registers
was actually being set to the beginning of all the control module registers,
not just those having to do with the pinmux. With this address fixed, the UART
now works on the beaglebone black.

Change-Id: I7c99b6f37d7da359af074127cd0c1a86fda2d9a0
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3574
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-01 18:31:28 +02:00
Kyösti Mälkki caaf0bf483 usbdebug: Support i82801dx/ex southbridge
Tested on i82801dx system with board aopen/dxplplusu.

Change-Id: I522455ac79c87b9b6fc9cd8c4dc0da3563dfbfad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3381
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-01 17:11:32 +02:00
Kyösti Mälkki 54c586c7e7 usbdebug: Unify Intel southbridge builds
EHCI controller enable is identical on the affected chipsets.

Change-Id: I91830b6f5144a70b158ec1ee40e9cba5fab3fbc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3424
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-01 17:11:14 +02:00