Commit Graph

40252 Commits

Author SHA1 Message Date
Kyösti Mälkki 4ff99a2655 sb,soc/intel: Add HPTS() for HPET visibility
Based on the detected OS the HPET ACPI device needs to
be hidden sometimes.

Change-Id: I4c6f87f30ea0de5c073b1fcf57794bb9e19d4d91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 06:27:21 +00:00
Julius Werner a39c577257 trogdor: Add fingerprint power sequencing
Some Trogdor variants will include a fingerprint sensor, so this patch
adds support for its power sequencing. There is a requirement that the
fingerprint power needs to be *off* for at least 200ms, and when it is
turned back on it needs to stabilize for at least 3.5ms before taking
the FPMCU out of reset. We meet these timing requirements by splitting
the sequence across bootblock, romstage and ramstage. On current Trogdor
boards we measured <end of bootblock> to <end of romstage> at ~430ms and
<end of romstage> to <start of ramstage> at 12ms, so we easily meet the
required numbers this way.

BRANCH=trogdor
BUG=b:170284663

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-02-12 22:17:53 +00:00
Felix Held 43ccd6a4ad mb/amd/majolica/devicetree: add CPU cluster
Change-Id: I8d8b7f3ea2502e4e49a1290b07d84d5bbb2924a7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50506
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 22:03:31 +00:00
Felix Held 34fc29ae96 soc/amd: add and use fch_enable_hpet_decode
On Picasso we missed setting this bit in coreboot and since the default
after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge
and Cezanne have the HPET decode enable bit in the same position in the
same register. In the ACPI table entry written by
southbridge_write_acpi_tables the HPET entry gets added, so we should
make sure that we enable the decode.

TEST=HPET still works on Mandolin.

Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:49:10 +00:00
Felix Held 1b33205909 soc/amd/common: add and use fch_enable_ioapic_decode
The default value of this bit is 0, so set it right before calling
setup_ioapic to make sure that it's set and not to have to rely on FSP
doing the right thing.

Change-Id: Ife886451a6927965769282fc5644c2085abb9585
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50513
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:48:28 +00:00
Felix Held 428a682abe soc/amd/cezanne: drop PWRS from GNVS
A copy of Picasso's include/nvs.h was added to Cezanne right before the
commit d6ccbb9d48 that removed it for the
other mainboards and SoCs, so apply the equivalent change here as well
to keep everything in sync.

Change-Id: I76b551c05b3c3028a3afb3bc3b77df2401aed7a8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-12 20:47:35 +00:00
Raul E Rangel ffab5e64d1 soc/amd: Move MADT IRQ override settings into common_config
This is another common ACPI setting.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iefecabae1d83996a9a4aaadd2a53c2432441e1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50558
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:45:59 +00:00
Raul E Rangel 1c88b10be2 soc/amd: Move fadt device tree settings into common_config
This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:45:37 +00:00
Raul E Rangel 0e560e7015 soc/amd: Move acpi_fill_mcfg into common/blocks/acpi
This is common between stoney, picasso, and cezanne.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fb40e8c6817773212c5fbd66c5c06bd2bae1eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50556
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:45:17 +00:00
Raul E Rangel 0f3bc81210 soc/amd: Move southbridge_write_acpi_tables
This is common between all the chipsets.

It's also required by common/block/lpc/lpc.c.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 20:44:48 +00:00
Raul E Rangel 48c99db6d6 mb/amd/majolica: Add FCH IRQ routing
I left most everything as NC since we don't expose the values to the
OS yet.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c3195ef27091f1bc61892c475ffe09137b63083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50511
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:43:09 +00:00
Raul E Rangel a6529e789f soc/amd/cezanne: Add PCI IRQ Router definitions
These definitions were identical to picasso. The only thing I changed
was that I renamed Misc1 and Misc2 to HPET_L and HPET_H.

This change still doesn't write the PCI_IRQ register for all the PCI
devices. We need to refactor the picasso pci_gpp code first.

TEST=Boot majolica and see FCH IRQs being programmed.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50451
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:42:35 +00:00
Angel Pons 77ef99be22 mb/google/slippy: Factor out SPD indexing
The code to read the SPD file and index it is not variant-specific.

Change-Id: Ifaedc39b683901b60abbb1d984f1d38c1ed364e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50542
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:52:50 +00:00
Angel Pons 9a094c4b63 nb/intel/haswell/pei_data.h: Define `SPD_LEN`
Change-Id: I34561372bcdd00b1b3e4dcd6be89fa47d2af9b42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50541
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:49:16 +00:00
Angel Pons fb95555088 nb/intel/haswell: Drop unused function declaration
Change-Id: Ica612bcdac373ac013a877bb96b77b2a3f522f7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50540
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:48:52 +00:00
Angel Pons a3c6ed0dff haswell boards: Correct USB config indentation
Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:48:34 +00:00
Angel Pons 33b59c9170 haswell: Drop `mainboard_fill_pei_data`
Use global variables to provide mainboard USB settings, and have the
northbridge code copy it into the `pei_data` struct. For now.

To minimize diffstat noise, this patch does not reindent the now-global
mainboard USB configuration arrays. This is cleaned up in a follow-up.

Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:48:26 +00:00
Angel Pons 3b0a4899d8 mb/msi/h81m-p33: Add new mainboard
This is a µATX mainboard with a LGA1150 socket and two DDR3 DIMM slots.

Working:
 - Both DIMM slots
 - Serial port to emit spam
 - Some USB ports
 - Integrated graphics (libgfxinit)
 - DVI
 - Realtek GbE
 - All PCIe ports
 - At least one SATA port
 - RAM initialization with MRC binary
 - Flashing with flashrom
 - S3 suspend/resume
 - VBT
 - SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)

Broken:
 - Audio. It doesn't work on stock firmware either.
   I suspect the codec hardware on my board is dead.

Untested:
 - PS/2 mouse
 - EHCI debug
 - Front USB headers
 - Non-Linux OSes
 - TPM header
 - VGA

Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41260
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:39:25 +00:00
Angel Pons 11235d6875 cpu/intel/haswell/acpi.c: Correct `get_cores_per_package`
CPUID result does not change when HyperThreading is disabled on
HT-enabled CPUs, which breaks `generate_cpu_entries`. Use MSR 0x35
instead, which returns the currently-enabled core and thread count.
Also rename the function to `get_logical_cores_per_package, which is
more accurate. Based on commit 920d2b77f2 (cpu/intel/206ax/acpi.c: Fix
get_cores_per_package). The MSR definition is the same for Sandy Bridge
and Haswell.

Change-Id: I5e1789d3037780b4285c9e367ff0e2b0d4365b39
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49099
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:29:07 +00:00
Daniel Kang a554122553 mb/google/volteer: Correct AT24 NVM address size
Currently, the address size field of AT24 NVM is incorrect, and
Linux v5.4 kernel logs the message below:

    at24 i2c-PRP0001:02: Bad "address-width" property: 13

The valid size of the AT24 NVM is 16 bits so modify the value from
0x0D to 0x10.

BUG=b:177655681
BRANCH=none
TEST=Boot volteer and check the kernel log and see "Bad address-width"
error message is not shown.

Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Ice6c3eac1e023b981217e1d7dc06587fc46b1a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bingbu Cao <bingbu.cao@linux.intel.com>
2021-02-12 16:59:57 +00:00
Felix Held d51fd30eef soc/amd/cezanne/smihandler: add psp_notify_smm call
TEST=Majolica still gets to SeaBIOS. Like before this patch the PSP
still has the recovery flag set in its return value, but we likely still
have some problem in the amdfw part or miss some PSP initialization in
FSP.

Change-Id: I9f343452ef2ea6b01f9b2fd0cf6371218d046046
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 15:29:35 +00:00
Felix Held 7cd81b91ac soc/amd/cezanne: select RTC
The RTC functionality will be used by elog.

Change-Id: I3a8d0a353620f64207d5ba8e17c145090f0c7506
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 14:40:13 +00:00
Felix Held 1a39aa01d1 soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar
The same functionality will eventually be needed on Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 14:39:53 +00:00
Felix Held 9d5e724010 soc/amd: select ACPI_AMD_HARDWARE_SLEEP_VALUES in common ACPI code
Change-Id: Ib03c6799017c9f51f3ffac8400c85675ac5d63f1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 14:39:30 +00:00
Felix Held ec54445cd4 soc/amd/picasso/psp: move to common code and rename to psp_smm_gen2
Change-Id: I771a7d36eea7307754386824190624a09c0e38f7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 14:39:09 +00:00
Patrick Georgi 007cf382f8 Revert "abuild: Allow disabling mainboards"
This reverts commit 3ac3c4ebac ("abuild: Allow disabling mainboards").

This mechanism helped getting Chrome OS' coreboot divergence sorted
out in the 2015/2016 timeframe but hasn't been used by anybody since
then. Let's not encourage people to push non-working builds without
good reason and discussion (the result of which could be that we
re-introduce this mechanism).

Change-Id: I8e2f2e1a5d4617baa49cbcb1a640a1ea270007ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50518
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 10:52:24 +00:00
Matt DeVillier 218038428e mb/purism/librem_mini: move mainboard asl under variant
Upcoming librem_cnl variant(s) won't share mainboard asl.

Change-Id: I9c2c43e5ae5efe161cc2135c920a1b9dee5a1317
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-12 10:33:28 +00:00
Elyes HAOUAS 1493e2d6ee Makefile.inc: Don't ignore _HID & _ADR coexisting in Broadwell ASL code
Issue fixed in commit d152837 so don't allow use of _HID and _ADR at same time.

Change-Id: I52beba66230a3542a7039f496b51be0aa4bdcce4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50384
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 10:33:11 +00:00
Patrick Rudolph 90c27e9611 mb/up/squared: Select NO_UART_ON_SUPERIO
Change-Id: I4c1cadb6d38ffd3f9eddcd1292c2e6aea08791d0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49395
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 08:00:03 +00:00
Angel Pons 6f5f376b95 mb/gigabyte/ga-h61m-series: Drop useless `mainboard.asl`
Was copy-pasted from another board and is completely useless.

Change-Id: Iedb03284b4509597cff5d39dda4f98669f2e814b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:59:13 +00:00
Angel Pons b27e7db0dc mainboard: Drop unneeded `default_brightness_levels.asl`
Desktop boards do not have any backlight control.

Change-Id: Ie9f5f4d7e6ae09b3d664d53e4c03157fd4ed088e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:58:43 +00:00
Angel Pons ecbd1a0f06 my boards: Do not include `superio.asl` twice
The southbridge ASL already includes this file.

Change-Id: I492d4c860a50ac98acbcb3a51fa4d47c94baade3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:58:06 +00:00
Angel Pons 22ad95394e sb/intel/x/lpc.c: Drop commented-out `gpio_init` call
Change-Id: I4255c63f87e8243237204ac86eb85e34b5aaa225
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12 07:56:57 +00:00
Angel Pons 6324759784 sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing`
The southbridge common SPI support already does this.

Tested on Asrock B85M Pro4, internal flashing and MRC cache still work.

Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12 07:56:48 +00:00
Angel Pons 9382f0c251 sb/intel/lynxpoint: Do not mask out TCO status bits
Not all TCO status bits have a corresponding enable bit. Masking out the
status register with the enable register causes these events to be lost.

Tested on Asrock B85M Pro4, BIOSWR_STS events are now detected.

Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12 07:56:33 +00:00
Angel Pons 04f1de3e14 sb/intel/lynxpoint: Only generate SerialIO SSDT for PCH-LP
Lynxpoint PCH-H does not have SerialIO, so do not generate its SSDT.

Change-Id: Ie816ebd470df93a45826498bf21be59ff0a813bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:56:04 +00:00
Angel Pons 1afe46913a sb/intel/lynxpoint/pch.h: Guard macro parameters
Guard against unintended operator precedence and associativity issues.

Tested on Asrock B85M Pro4, still boots.

Change-Id: I2b22af17816e5383c7eb215a773eb6750d4ed9bc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:55:24 +00:00
Angel Pons 06f1fed3a1 sb/intel/common: Move named packages out of method
IASL complains that creation of named objects within a method is highly
inefficient. Avoid this by moving these named objects out of the method.

Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:54:55 +00:00
Angel Pons 3529024071 nb/intel/common/fixed_bars.h: Add casts to `uintptr_t`
64-bit builds need this, as the Kconfig values fit in a 32-bit integer.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I570374f92394f839a97e28fabc8fa07a7e673e83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-12 07:52:37 +00:00
Angel Pons f95b9b4b09 nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-12 07:52:25 +00:00
Angel Pons ea573b04d8 sandybridge MRC boards: Drop channel disable masks
Platform code will overwrite these values anyway, so do not program them
in mainboards.

Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 07:52:01 +00:00
Angel Pons 64c6a746ac soc/intel/broadwell: Use southbridge common RCBA
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I94953bed3f331848271464bee829f8209167f150
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-12 07:51:22 +00:00
Angel Pons 75439de2d9 util/superiotool: Add ITE IT8616E/IT8656E support
Datasheet is not publicly available. Derive which registers to dump from
IT8625E, since there are mainboards that can use either chip depending
on BOM configuration. Default values are taken from an HP 280 G2 running
a coreboot build that does not configure the Super I/O.

Change-Id: Icc8c56e9cd19e940e85176ac51b8ef978275eb71
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-12 07:49:43 +00:00
Angel Pons 86afb171b6 util/superiotool: Add ITE IT8625E support
Values as per "IT8625E Preliminary Specification V0.3 (For D Version)".

Change-Id: Ic3ff13d93f66d09a1f2ea953736336b201a7114c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-12 07:49:33 +00:00
Karthikeyan Ramasubramanian e49dfb6c44 mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx

BUG=b:172846122
TEST=./util/abuild/abuild

Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-12 07:48:54 +00:00
Karthikeyan Ramasubramanian 6bcaf6f908 mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx

BUG=b:172846122
TEST=./util/abuild/abuild

Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-12 07:48:42 +00:00
Jakub Czapiga b3a7c84b43 tests: Add lib/stack-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-02-12 07:48:24 +00:00
Felix Held e22eef7c51 soc/amd/*/Kconfig: remove redundant SMM_TSEG condition
Since SMM is in TSEG on the platforms which is the default, drop the
SMM_TSEG condition for the default of SMM_TSEG_SIZE.

Change-Id: I7bd965c0794efa12ea4886a55522cc5193a1d3ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50498
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 00:42:32 +00:00
Ritul Guru 8c80d9e612 3rdparty/blobs: advance submodule pointer.
This adds the apcb binary for Bilby.

Change-Id: I1487369bc72734e875c5a701f27ed2d6af41cd01
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-11 21:34:52 +00:00
Patrick Georgi fe5cf51258 util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS
Sometimes boards enable it by default, making the Kconfig option
impossible to disable without messing with the Kconfig files. This
shouldn't happen, so report on such occurrences early.

TEST=Tried building GOOGLE_KOHAKU through abuild with -x, without
-x and both cases after having added a "select CHROMEOS" for testing
and it failed in the "without -x with select" scenario while properly
configuring and passing all other builds.

Change-Id: Ieb6bcbf3e9ca8cd4ced85c7c9ffaa39505f5a9b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 20:49:27 +00:00